A more complete appreciation of the present invention and many of the attendant advantages thereof, will be readily apparent as the present invention becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.
Each of the first and second substrates 12 and 14 has an active area 18 emitting visible light and an inactive area 20 surrounding the active area 18 within an area surrounded by the seal members 16. An electron emission unit 22a for emitting electrons is provided on the active area 18 of the first substrate 12 and a light emission unit 24 for emitting the visible light is provided on the active area 18 of the second substrate 14.
When the electron emission regions 32 are formed on the first electrodes 28, the first electrodes 28 are cathode electrodes applying a current to the electron emission regions 32 and the second electrodes 30 are gate electrodes inducing the electron emission by forming the electric field around the electrode emission regions 32 according to a voltage difference between the cathode and gate electrodes. On the contrary when the electron emission regions 32 are formed on the second electrodes 30, the second electrodes 30 are cathode electrodes and the first electrodes 28 are gate electrodes.
Among the first and second electrodes 28 and 30, the electrodes arranged along rows of the light emission device 10A function as scan electrodes and the electrodes arranged along columns function as data electrodes.
Openings 261 and 301 are formed through the insulating layer 26 and the second electrode 30 at crossed regions of the first and second electrodes 28 and 30 to partly expose the surface of the first electrodes 28. The electron emission regions 32 are formed on the first electrodes 28 through the openings 261 of the insulating layer 26.
The electron emission regions 32 are formed of a material emitting electrons when an electric field is applied thereto under a vacuum atmosphere, such as a carbon-based material or a nanometer-sized material. The electron emission regions 32 can be formed of carbon nanotubes, graphite, graphite nanofibers, diamonds, diamond-like carbon, C60, silicon nanowires or a combination thereof. The electron emission regions 32 can be formed through a screen-printing process, a direct growth, a chemical vapor deposition, or a sputtering process. Alternatively, the electron emission regions can be formed in a tip structure formed of a Mo-based or Si-based material.
A resistive layer 34a is formed on a portion of the insulating layer 26, which is not covered by the second electrodes 30 so that a surface of the insulating layer 26 cannot be exposed to the vacuum environment. The resistive layer 34a has specific resistance lower than that of the insulating layer 26. In one embodiment, the resistive layer 34a has specific resistance within the range of about 106-1012 Ωcm. Since the resistive layer 34a is a high resistive body, no electric current is applied between the second electrodes 30 through the resistive layer 34a.
The resistive layer 34a is formed between the second electrodes 30 at the active area 18 of the first substrate 12 and formed having a predetermined width to surround the edge of the active area 18 at the inactive area 20 of the first substrate. As shown in
The resistive layer 34a may be formed of amorphous silicon doped with n-type or p-type ions. Alternatively, the resistive layer 34a may be formed of a mixture of insulation material and conductive material. In this case, the conductive material may be selected from the group of metal nitride such as aluminum nitride (AlN), metal oxide such as Cr2O3, a carbon-based conductive material such as graphite, or a mixture thereof. The resistive layer 34a may be formed through a screen-printing process or a plasma-enhanced chemical vapor deposition.
The resistive layer 34a has an electric charge preventing function by which electric charges are not accumulated on a surface thereof. The resistive layer 34a may be grounded through an external circuit (not shown) or applied with a negative DC voltage.
One overlapping region of the first and second electrodes 28 and 30 may correspond to one pixel region of the light emission device 10A. Alternatively, two or more overlapping regions of the first and second electrodes 28 and 30 may correspond to one pixel region of the light emission device 1A. In this case, two or more first electrodes 28 and/or two or more second electrodes 30 that are placed in one pixel region are electrically connected to each other to receive a common driving voltage.
The light emission unit 24 includes a phosphor layer 36 and an anode electrode 38 formed on the phosphor layer 36. The phosphor layer 36 may be formed by a white phosphor layer or a combination of red, green and blue phosphor layers. When the phosphor layer 36 is the white phosphor layer, the phosphor layer may be formed at the entire active area 18 of the second substrate 14, or divided in a plurality of sections each corresponding to each pixel region. The red, green and blue phosphor layers are formed in a predetermined pattern in each pixel region. In
The anode electrode 38 may be formed by a metal such as Aluminum and cover the phosphor layer 36. The anode electrode 38 is an acceleration electrode that receives a high voltage to maintain the phosphor layer 38 at a high electric potential state. The anode electrode 38 functions to enhance the luminance by reflecting the visible light, which is emitted from the phosphor layers 36 to the first substrate 12, toward the second substrate 14.
Disposed between the first and second substrates 12 and 14 are spacers (not shown) for uniformly maintaining a gap between the first and second substrates 12 and 14 against the outer force.
The above-described light emission device 10A is driven by applying drive voltages to the first and second electrodes 28 and 30 and applying thousands volt of a positive high DC voltage (e.g., several thousand volts) to the anode electrode 38.
Then, an electric field is formed around the electron emission regions 32 at pixel regions where a voltage difference between the first and second electrodes 28 and 30 is higher than a threshold value, thereby emitting electrons from the electron emission regions 32. The emitted electrons are accelerated by the high voltage applied to the anode electrode 38 to collide with the corresponding phosphor layer 38, thereby exciting the phosphor layer 38. The light emission intensity of the phosphor layer 38 at each pixel corresponds to an electron emission amount of the corresponding pixel.
In the above-described driving process, since the exposed surface of the insulating layer 26, which is not covered by the second electrodes 30, is covered by the resistive layer 34a, the exposed surface of the insulating layer 26 is not electrically charged. Therefore, the arcing due to the electric charge can be minimized.
Since a relatively high voltage, for example, above 10 kv can be applied to the anode electrode 38 as compared with the convention field emission type backlight unit, the light emission intensity can be enhanced without damaging the internal structure of the light emission device.
In one embodiment, the gap between the first and second substrates 12 and 14 may be within the range of, for example, 5-20 mm that is greater than that of a conventional field emission type backlight unit. The anode electrode 38 receives a high voltage above 10 kV, preferably, about 10-15 kV, through an anode voltage applying unit 40, shown in
According to this embodiment, even when the electrons emitted from the electron emission regions 32 collide with the sidewalls of the openings 261, the electric charges are not accumulated on the sidewalls of the openings 261, rather, they flow out to the external side through the resistive layer 34c. Therefore, the light emission device 10C of this embodiment can prevent the arcing by suppressing the accumulation of the electric charges on the sidewalls of the insulating layer openings 261 with which a relatively large amount of electrons collide.
That is, an additional insulating layer 42 is formed on the insulating layer 26 while covering the second electrodes 30 and the resistive layer 34d is formed on the additional insulating layer 42. At this point, openings 341 and 421 communicating with the openings 301 and 261 of the second electrodes 30 and the first insulating layer 26 are formed through the resistive layer 34d and the additional insulating layer 42.
In this embodiment, since the resistive layer 34d does not directly contact the second electrodes 30 by the additional insulating layer 42, it may be formed of a low specific resistance material having specific resistance within the range of about 102-104 Ωcm. In one embodiment, a conductive layer may be formed instead of the resistive layer 34d.
The resistive layer 34d has an electric charge preventing function for suppressing arcing. As the resistance of the resistive layer 43d is lowered, the effect of the anode electric field on the electron emission regions can be more effectively lowered. Therefore, in the light emission device 10D of this embodiment, the arcing and the diode emission due to the anode electric field can be effectively suppressed even when the anode voltage is above 10 kV.
Referring to
The insulating layer 26 has two longitudinal side edges and two lateral side edges. The conductive layer 44 is formed on three side edges of the insulating layer 26, except for one side edge where second electrode leads 46 extending from the second electrodes 30 are formed. That is, the conductive layer 44 is formed on both longitudinal side edges and one lateral side edge of the insulating layer 26.
A resistive layer 34e is formed on an exposed portion of the insulating layer 26, which is not covered by the second electrodes 30 and the conductive layer 44 so that the exposed portion of the insulating layer 26 cannot be exposed to the vacuum. The resistive layer 34e continuously transmits electric charges accumulated on the surface of the insulating layer 26 to the conductive layer 44. The conductive layer 44 is grounded through an external circuit, therefore, the arcing can be effectively suppressed.
The sealing member 16 includes a support frame 161 formed of glass or ceramic and a pair of adhesive layers 162 respectively formed on a first surface of the support frame 161 facing the first substrate 12 and a second surface of the support frame 161 facing the second surface 14 to integrally adhere the first substrate 12, the support frame 161, and the second substrate 14 to each other. In this case, the second resistive layer 48 may be provided on an inner surface of the support frame 161.
The second resistive layer 48 may be electrically connected to the resistive layer provided on the first substrate 12 after the vacuum vessel is assembled, or to the conductive layer formed on the first substrate 12. That is, the second resistive layer 48 is grounded through the resistive layer provided on the first substrate 12, or the conductive layer provided on the first substrate. A negative DC voltage is applied to the second resistive layer 48 through the conductive layer.
In
The second resistive layer 48 functions to suppress the arcing by preventing electric charges from accumulating on the inner surface of the sealing member 16. Particularly, when the negative DC voltage is applied to the second resistive layer 48, the second resistive layer 48 provides repulsive force to electrons that are emitted from the edge of the active area and spread widely, thereby guiding the electrons to the phosphor layer 36 of the corresponding pixel region. In this case, the light emission efficiency of the light emission device 10F is improved through the second resistive layer 48.
Referring to
The display panel 60 may be a liquid crystal display panel or any other non-self emissive display panel. In the following description, a liquid crystal display panel is exampled.
The display panel 60 includes a thin film transistor (TFT) substrate 62 comprised of a plurality of TFTs, a color filter substrate 64 disposed on the TFT substrate 62, and a liquid crystal layer (not shown) disposed between the TFT substrate 62 and the color filter substrate 64. Polarizer plates (not shown) are attached on a top surface of the color filter substrate 64 and a bottom surface of the TFT substrate 62 to polarize the light passing through the display panel 60.
The TFT substrate 62 is a glass substrate on which the TFTs and pixel electrodes are arranged in a matrix pattern. A data line is connected to a source terminal of one TFT and a gate line is connected to a gate terminal of the TFT. In addition, a pixel electrode is connected to a drain terminal of the TFT.
When electrical signals are input from circuit board assemblies 66 and 68 to the respective gate and data lines, electrical signals are input to the gate and source terminals of the TFT. Then, the TFT turns on or off according to the electrical signals input thereto, and outputs an electrical signal required for driving the pixel electrode to the drain terminal.
RGB color filters are formed on the color filter substrate 64 so as to emit predetermined colors as the light passes through the color filter substrate 64. A common electrode is deposited on an entire surface of the color filter substrate 64.
When electrical power is applied to the gate and source terminals of the TFTs to turn on the TFTs, an electric field is formed between the pixel electrode of the TFT substrate 62 and the common electrode of the color filter substrate 64. Due to the electric filed, the orientation of liquid crystal molecules of the liquid crystal layer can be varied, and thus the light transmissivity of each pixel can be varied according to the orientation of the liquid crystal molecules.
The circuit board assemblies 66 and 68 of the display panel 60 are connected to drive IC packages 661 and 681, respectively. In order to drive the display panel 60, the gate circuit board assembly 66 transmits a gate drive signal and the data circuit board assembly 68 transmits a data drive signal.
The number of pixels of the light emission device 10 is less than that of the display panel 60 so that one pixel of the light emission device 10 corresponds to two or more pixels of the display panel 60. Each pixel of the light emission device 10 emits light in response to the highest gray value among the corresponding pixels of the display panel 60. The light emission device 10 can represent 2-8 bits gray value at each pixel.
For convenience, the pixels of the display panel 60 will be referred to as first pixels and the pixels of the light emission device 10 will be referred to as second pixels. In addition, a plurality of first pixels corresponding to one second pixel will be referred to as a first pixel group.
In order to drive the light emission device 10, a signal control unit (not shown) for controlling the display panel 60 detects a highest gray value among the first pixels of the first pixel group, calculates a gray value required for the light emission of the second pixel according to the detected gray value, converts the calculated gray value into digital data, and generates a driving signal of the light emission device 10 using the digital data. The drive signal of the light emission device 10 includes a scan drive signal and a data drive signal.
Circuit board assemblies (not shown), that is a scan circuit board assembly and a data circuit board assembly, of the light emission device 10 are connected to drive IC packages 521 and 541, respectively. In order to drive the light emission device 10, the scan circuit board assembly transmits a scan drive signal and the data circuit board assembly transmits a data drive signal. One of the first and second electrodes receives the scan drive signal and the other receives the data drive signal.
Therefore, when an image is to be displayed by the first pixel group, the corresponding second pixel of the light emission device 10 is synchronized with the first pixel group to emit light with a predetermined gray value. The light emission device 10 has pixels arranged in rows and columns. The number of pixels arranged in each row may be 2 through 99 and the number of pixels arranged in each column may be 2 through 99.
As described above, in the light emission device 10, the light emission intensities of the pixels of the light emission device 10 are independently controlled to emit a proper intensity of light to each first pixel group of the display panel 60. As a result, the display device 100 of the present invention enhances the dynamic contrast of the screen.
Although exemplary embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concept taught herein still fall within the spirit and scope of the present invention, as defined by the appended claims.
Number | Date | Country | Kind |
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10-2006-0045223 | May 2006 | KR | national |
10-2006-0054000 | Jun 2006 | KR | national |
10-2006-0054001 | Jun 2006 | KR | national |
10-2006-0054455 | Jun 2006 | KR | national |