Patent Application
20240355967
This application claims the benefit of priority of Singapore application No. 10202301118T filed Apr. 21, 2023, the contents of it being hereby incorporated by reference in its entirety for all purposes.
Various embodiments of this disclosure may relate to a light emission device. Various embodiments of this disclosure may relate to a method of forming a light emission device.
The ability to have an electrically pumped low-threshold laser on silicon (Si) promises to enable a range of exciting technologies, from ultra-compact, low-cost Light Detection and Ranging (LiDAR) chips to ultra-fast optical interconnects for data centers. For this reason, the realization of a Si compatible laser diode is often referred to as the ‘holy grail’ of Si photonics, owing to its unique potential in unlocking the full power of photonic-integrated circuits. However, Si compatible materials are naturally poor emitters of light due to their indirect bandgap nature, which has prevented any practical realization of an on-chip Si compatible laser.
Various embodiments may provide a light emission device. The light emission device may include a substrate. The light emission device may also include a stacked arrangement over the substrate, the stacked arrangement having a first pad region, a second pad region and a bridge region extending between the first pad region and the second pad region, the bridge region having a lateral width smaller than a lateral width of the first pad region, and smaller than a lateral width of the second pad region. At least a portion of the first pad region may include a portion of a first doped layer. At least a portion of the second pad region may include a further portion of the first doped layer, a portion of a second doped layer, and a portion of an intrinsic layer, the portion of the intrinsic layer between the further portion of the first doped layer and the portion of the second doped layer. The first doped layer may include germanium (Ge) or germanium-tin (GeSn), and may be of a first electrical conductivity type. The second doped layer may include germanium (Ge) or germanium-tin (GeSn), and may be of a second electrical conductivity type different from the first electrical conductivity type. The intrinsic layer may include germanium-tin (GeSn), such that a percentage concentration of tin (Sn) of the intrinsic layer is higher than a percentage concentration of tin (Sn) of the first doped layer, and is higher than a percentage concentration of tin (Sn) of the second doped layer. The light emission device may additionally include a first tensile stressed metal pad in contact with the portion of the first doped layer. The light emission device may also include a second tensile stressed metal pad in contact with the portion of the second doped layer, such that first tensile-stressed metal pad and the second tensile-stressed metal pad cause a tensile strain in the bridge region.
Various embodiments may relate to a method of forming a light emission device. The method may include forming a stacked arrangement over a substrate, the stacked arrangement having a first pad region, a second pad region and a bridge region extending between the first pad region and the second pad region, the bridge region having a lateral width smaller than a lateral width of the first pad region, and smaller than a lateral width of the second pad region. At least a portion of the first pad region may include a portion of a first doped layer. At least a portion of the second pad region may include a further portion of the first doped layer, a portion of a second doped layer, and a portion of an intrinsic layer, the portion of the intrinsic layer between the further portion of the first doped layer and the portion of the second doped layer. The first doped layer may include germanium (Ge) or germanium-tin (GeSn), and may be of a first electrical conductivity type. The second doped layer may include germanium (Ge) or germanium-tin (GeSn), and may be of a second electrical conductivity type different from the first electrical conductivity type. The intrinsic layer may include germanium-tin (GeSn), such that a percentage concentration of tin (Sn) of the intrinsic layer is higher than a percentage concentration of tin (Sn) of the first doped layer, and is higher than a percentage concentration of tin (Sn) of the second doped layer. Forming the light emission device may also include forming a first tensile stressed metal pad in contact with the portion of the first doped layer. Forming the light emission device may further include forming a second tensile stressed metal pad in contact with the portion of the second doped layer, such that first tensile-stressed metal pad and the second tensile-stressed metal pad cause a tensile strain in the bridge region.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale, emphasis instead generally being placed upon illustrating the principles of various embodiments. In the following description, various embodiments of the invention are described with reference to the following drawings.
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.
In the context of various embodiments, the articles “a”, “an” and “the” as used with regard to a feature or element include a reference to one or more of the features or elements.
In the context of various embodiments, the term “about” or “approximately” as applied to a numeric value encompasses the exact value and a reasonable variance, e.g. within 10% of the specified value.
As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
By “comprising” it is meant including, but not limited to, whatever follows the word “comprising”. Thus, use of the term “comprising” indicates that the listed elements are required or mandatory, but that other elements are optional and may or may not be present.
By “consisting of” is meant including, and limited to, whatever follows the phrase “consisting of”. Thus, the phrase “consisting of” indicates that the listed elements are required or mandatory, and that no other elements may be present.
Embodiments described in the context of one of the light emission devices are analogously valid for the other light emission devices. Similarly, embodiments described in the context of a method are analogously valid for a light emission device, and vice versa.
In recent years, there has been extensive interest in converting one of the Si compatible materials, germanium (Ge), into a direct bandgap material, to realize such an on-chip laser. Two approaches are conventionally utilized to transform Ge into an efficient light emitter: tensile strain engineering and tin (Sn) alloying. Recently, an exciting hybrid approach combining tensile strain engineering and germanium tin (GeSn) alloys have shown the best lasing characteristics with ultra-low lasing thresholds. The crucial next step towards the realization of a practical on-chip laser is to add the last major functionality via electrical injection.
In other words, various embodiments may relate to a light emission device with a stacked arrangement 104. The stacked arrangement 104 may include three layers, with the middle layer 104c being a GeSn layer having a concentration of tin (Sn) higher than the other two layers 104a, 104b. The light emission device may also include metal pads 106a, 106b configured to cause a tensile strain in a bridge region of the light emission device. The layer 104a may be of a first electrical conductivity type, while the second layer 104b may be of a first electrical conductivity type.
For avoidance of doubt,
In various embodiments, the light emission device may be configured to emit light upon application of a potential difference between the first tensile stressed metal pad 106a and the second tensile stressed metal pad 106b.
In various embodiments, at least a portion of the bridge region may include an additional portion of the first doped layer 104a, a further portion of the second doped layer 104b and a further portion of the intrinsic layer 104c. The further portion of the intrinsic layer 104c may be between the additional portion of the first doped layer 104a and the further portion of the second doped layer 104b.
In various embodiments, the light emission device may also include one or more buffer layers between the substrate 102 and the stacked arrangement 104. In various embodiments, the one or more buffer layers may include a first buffer layer including silicon dioxide (SiO2) and/or aluminum nitride (AlN). The one or more buffer layers may further include a second buffer layer on the first buffer layer, the second buffer layer including aluminum oxide (Al2O3) or silicon dioxide (SiO2). In various embodiments, a portion of the second buffer layer under the bridge region may be removed, and the bridge region (e.g. the additional portion of the first doped layer 104a) may be in contact with the first buffer layer. Contacting the bridge region with the first buffer layer may help improve thermal management.
In various other embodiments, the one or more buffer layers may include a virtual substrate (VS) layer including germanium (Ge). The one or more buffer layers may further include a first buffer layer on the virtual substrate layer, the first buffer layer including germanium-tin (GeSn). The one or more buffer layers may further include a second buffer layer on the first buffer layer, the second buffer layer also including germanium-tin (GeSn). A percentage concentration of tin (Sn) of the second buffer layer may be higher than a percentage concentration of tin (Sn) of the first buffer layer.
In various embodiments, the bridge region may be over a gap between the first buffer layer and the substrate 102. The gap may result from the under-etching of a portion of the virtual substrate layer.
In various other embodiments, the bridge region may be in contact with the substrate 102. A portion of the first buffer layer and a portion of the second buffer layer under the bridge region may also be removed (in addition to the under-etching of the portion of the virtual substrate layer). The additional portion of the first doped layer 104a in the bridge region may be in contact with the substrate 102, due to bridge region (of the stacked arrangement) being directly laid on the substrate 102 after under-etching of the portion of the virtual substrate layer, the portion of the first buffer layer and the portion of the second buffer layer.
In various embodiments, a metal pad having residual stress, such as the first tensile stressed metal pad 106a or the second tensile stressed metal pad 106b, may be due to the mismatch in a thermal expansion coefficient of the metal pad and a thermal expansion coefficient of the underlying layer. For instance, the first metal pad 106a may be tensile stressed due to a mismatch in a thermal expansion coefficient of the first metal pad 106a and a thermal expansion coefficient of the first doped layer 104a under and in contact with the first metal pad 106a. The second metal pad 106b may be tensile stressed due to a mismatch in a thermal expansion coefficient of the second metal pad 106b and a thermal expansion coefficient of the second doped layer 104b under and in contact with the second metal pad 106b. The metal of the metal pad may initially be deposited at a higher temperature (e.g. exceeding room temperature), followed by a gradual cooling to a lower temperature (e.g. room temperature). This process may induce residual stress in the metal pad due to the thermal expansion coefficient mismatch between the metal and its underlying layer. Furthermore, the level of stress in the metal may be varied or customized by adjusting factors such as the deposition temperature, the composition of the metal, or the thickness of the metal pad.
The first tensile stressed metal pad 106a and the second tensile stressed metal pad 106b may also serve to allow for electrical pumping of the light emission device.
In various embodiments, the first tensile stressed metal pad 106a and/or the second tensile stressed metal pad 106b may include any suitable metal, providing that the coefficient of thermal expansion of the metal pad and the coefficient of thermal expansion of the underlying layer are taken into account. The first tensile stressed metal pad 106a may include any suitable metal having a thermal expansion coefficient higher than a thermal expansion coefficient of the underlying first doped layer 104a. The second tensile stressed metal pad 106a may include any suitable metal having a thermal expansion coefficient higher than a thermal expansion coefficient of the underlying second doped layer 104b. For instance, the first tensile stressed metal pad may include gold and/or chromium, and the second tensile stressed metal pad may also include gold and/or chromium.
In various embodiments, the first pad region may include a first reflector. The second pad region may include a second reflector. The first reflector may be a distributed Bragg reflector or a corner cube mirror. The second reflector may be a distributed Bragg reflector or a corner cube mirror.
In various embodiments, the first electrical conductivity type may be p-doped, while the second electrical conductivity type may be n-doped. In various other embodiments, the first electrical conductivity type may be n-doped (or p-type), while the second electrical conductivity type may be p-doped (or n-type). A Ge or GeSn layer may be n-doped by introducing dopants such as phosphorus (P), arsenic (As) or antimony (Sb). A Ge or GeSn layer may be p-doped by introducing dopants such as boron (B), gallium (Ga) or indium (In). In various embodiments, the light emission device may be a laser diode. In various other embodiments, the light emission device may be a light emitting diode (LED).
In other words, the method may include forming the stacked arrangement as well as the first tensile stressed metal pad and the second tensile stressed metal pad.
For avoidance of doubt,
In various embodiments, at least a portion of the bridge region may include an additional portion of the first doped layer, a further portion of the second doped layer and a further portion of the intrinsic layer. The further portion of the intrinsic layer may be between the additional portion of the first doped layer and the further portion of the second doped layer.
In various embodiments, the portion of the first pad region including the portion of the first doped layer is formed by etching an overlying portion of the second doped layer and an overlying portion of the intrinsic layer.
In various embodiments, the method may include forming one or more buffer layers between the substrate and the stacked arrangement. In various embodiments, the one or more buffer layers may be formed before forming the stacked arrangement.
In various embodiments, the one or more buffer layer may include a first buffer layer including silicon dioxide (SiO2) and/or aluminum nitride (AlN). The one or more buffer layers may further include a second buffer layer on the first buffer layer, the second buffer layer including aluminum oxide (Al2O3) or silicon dioxide (SiO2).
In various other embodiments, the one or more buffer layers may include a virtual substrate (VS) layer including germanium. The one or more buffer layers may further include a first buffer layer on the virtual substrate layer, the first buffer layer including germanium-tin (GeSn). The one or more buffer layers may further include a second buffer layer on the first buffer layer, the second buffer layer also including germanium-tin (GeSn).
In various embodiments, the method may include under etching a portion of the virtual substrate layer between a portion of the first buffer layer and the substrate to form a gap under the bridge region of the stacked arrangement, or further under etching a portion of the first buffer layer and the portion of the second buffer layer under the bridge region to allow the bridge region to be in contact with the substrate.
In other words, in various embodiments, the bridge region may be over a gap between the first buffer layer and the substrate due to under etching of the portion of the virtual substrate layer. In various other embodiments, the method may include further under etching a portion of the first buffer layer and a portion of the second buffer layer under the bridge region, and directly laying the bridge region (of the stacked arrangement) on the substrate (such that the additional portion of the first doped layer in the bridge region is in contact with the substrate) after under etching the portion of the virtual substrate layer, the portion of the first buffer layer and the portion of the second buffer layer.
In various embodiments, the method may include forming a first reflector in the first pad region. The method may also include forming a second reflector in the second pad region.
In various embodiments, the first reflector may be a distributed Bragg reflector or a corner cube mirror. The second reflector may be a distributed Bragg reflector or a corner cube mirror.
In various embodiments, forming the first tensile stressed metal pad and/or the second tensile stressed metal may include depositing a suitable metal under a first temperature on a layer (e.g. first doped layer for the first tensile stressed metal pad, second doped layer for the second tensile stressed metal pad), and allowing the deposited metal to cool to a second temperature lower than the first temperature. Due to the mismatch of the thermal expansion coefficients between the metal and the underlying layer, the resulting metal pad formed may be tensile stressed. The level of stress in the metal may be varied or customized by adjusting factors such as the deposition temperature, the composition of the metal, or the thickness of the metal pad.
Various embodiments may provide aspects required for an efficient and Si-compatible on-chip emission device or laser. Various embodiments may have a unique stressed electrode design that provides key dual functionalities such as electrical pumping and tensile strain engineering. Various embodiments may have a highly strained and uniform GeSn gain medium with high material quality. Various embodiments may have an excellent optical cavity which does not interfere with the strain field. Various embodiments may have superior thermal management by employing unique dual-insulator layers.
The stressed electrode laser structure may offer numerous advantages over the current state-of-the-art technology. As metal stressors introduce the tensile strain, the laser structure may naturally be optimized for electrical pumping, which may be a strict requirement for a practical device. Stressed electrodes may currently provide the only route towards electrically pumped strained GeSn lasers, which in turn may be the most promising route towards a practical on-chip laser. Additionally, by using the GeSn on dual insulator (GeSnODI) material platform according to various embodiments, the thermal management and optical confinement may be drastically improved compared to other structures which place the GeSn in contact with air or Si. This superior thermal management may allow for room temperature and continuous-wave operation of the laser structure, another strict requirement for a practical device that no other technology currently satisfies. The stressed electrodes and GeSnODI may be combined with the fact that the entire fabrication procedure is fully compatible with the industry-standard complementary metal-oxide-semiconductor (CMOS) process. In view of the abovementioned, various embodiments may be currently the most viable candidate for a market-ready laser.
Conventional tensile strain engineering on suspended bridge structures relies on the fact that Ge grown on Si has an initially tensile strain. By releasing two tensile strained Ge pads (achieved by etching away the layer underneath Ge), an enhanced tensile strain is imparted into the narrow bridge.
However, in the case of GeSn, which is grown on Si using a Ge buffer layer, the GeSn layer has an initially compressive strain. Therefore, the previously described method would only introduce enhanced compressive strain, which may in turn harm the lasing. To overcome this issue, the laser structure according to various embodiments may use tensile-stressed metal pads deposited onto the partially etched GeSn pad region, which after subsequent releasing, impart a tensile strain into the GeSn nanowire bridges, despite the initial compressive strain in GeSn.
Both uniaxial and biaxial strain can be introduced by merely altering the geometry of the pads and bridge, making the strain engineering platform extremely versatile. By combining a relatively low Sn-content GeSn with high tensile strain, a much higher material quality may be achieved (relative to high-Sn content layers which introduce many defects). Additionally, a direct bandgap configuration can be achieved, resulting in an excellent gain medium for lasing.
An optical cavity may be introduced by placing Distributed Bragg Reflectors (DBRs) or corner cube mirrors in the pad regions still containing GeSn. Photons resonate between these mirrors which exhibit a large degree of optical confinement, resulting in stimulated emission and lasing. After releasing the GeSn bridge and stressed metal pads, the entire device may be brought into contact with the underlying insulator layers (SiO2/AlN), thereby resulting in superior thermal management whilst maintaining excellent optical confinement. The metal pads can have etching holes to facilitate faster release and higher tensile strain by reducing the distance of release.
The GeSn on dual insulator (GeSnODI) material platform or structure may be created using low-temperature wafer bonding techniques. By using two buffer or insulator layers, the buffer or insulator layer underneath the GeSn can be selectively removed, and the GeSn can subsequently be brought into contact with the other buffer or insulator layer. Various embodiments may therefore offer drastic improvements in thermal management compared to the conventional method of suspending the GeSn in the air, due to enhanced thermal conduction paths into the Si substrate.
The GeSnODI may utilize silicon dioxide and/or aluminum nitride (SiO2/AlN) as the first buffer or insulation layer, and aluminum oxide (Al2O3) or silicon dioxide (SiO2) as the second buffer or insulation layer on the first buffer or insulation layer. The AlN may have a thermal conductivity that is two orders of magnitude higher than SiO2, resulting in superior thermal management. Furthermore, AlN has only a slightly higher refractive index of 1.8 at the target lasing wavelengths, still offering excellent optical confinement.
Both optically pumped lasers and electrically pumped lasers may be created using this method. Not only do the metal pads apply the tensile strain to the nanowire, the metal pads can also simultaneously inject electrical current into the active gain medium.
The vertical PIN heterojunction may include Ge or GeSn with barrier layers 604a, 604b that have a lower Sn-content. Contact holes can be made by a partial etch to make metal contacts to both the p-type layer 604a and the n-type layer 604b in the pad regions as denoted by ‘A’ and ‘C’. The bridge region (alternatively referred to as nanowire) may be denoted by ‘B’.
Electrons may be injected into the n-type layer 604b, and holes may be injected into the p-type layer 604a, both of which are subsequently confined in the intrinsic layer 604c (alternatively referred to as intrinsic active gain medium) in the nanowire, resulting in the emission of photons. The photons may be trapped between the two mirrors 610a, 610b, which cause stimulated emission of photons, and once threshold is reached, lasing may be achieved. To induce the tensile strain, portions of the tensile stressed metal pads 606a, 606b may be placed on the p-type layer 604a and the n-type layer 604b, respectively. In various embodiments, a thin layer of Al2O3 may also be inserted in between the GeSn stacked arrangement 604 and the SiO2/AlN layer 608 (as shown in
Electrically pumped light emitting diodes (LEDs) may be created by a sophisticated fabrication process.
Complementary Metal Oxide Semiconductor (CMOS)-compatible short- and mid-wave infrared emitters are highly coveted for the monolithic integration of silicon-based photonic and electronic integrated circuits to serve a myriad of applications in sensing and communications. In this regard, a group IV germanium-tin (GeSn) material epitaxially grown on silicon (Si) emerges as a promising platform to implement tunable infrared light emitters. Indeed, upon increasing the Sn content, the bandgap of GeSn narrows and becomes direct, making this material system suitable for developing an efficient silicon-compatible emitter. With this perspective, microbridge PIN GeSn LEDs with a small footprint of 1,520 μm2 are demonstrated and their operation performance is investigated. The spectral analysis of the electroluminescence emission exhibits a peak at 2.31 μm and it red-shifts slightly as the driving current increases. It is found that the microbridge LED may operate at a dissipated power as low as 10.8 W at room temperature and just 3 W at 80 K. This demonstrated low operation power may be comparable to that reported for LEDs having a significantly larger footprint reaching 106 μm2. The efficient thermal dissipation of various embodiments may help to reduce the heat-induced optical losses, thus enhancing light emission. Further performance improvements may be envisioned through thermal and optical simulations of the microbridge design. The use of GeSnOI substrate for developing a similar device may be expected to improve optical confinement for the realization of electrically driven GeSn lasers.
Reducing the footprint of CMOS-compatible optical interconnects is a key paradigm to address the relentless course toward the very dense integration of chips while maintaining high bandwidth and low power consumption. In fact, as future electronic chips require further device scaling, the associated miniaturization of metal interconnects suffers fundamental limits leading to high impedance and joule heating, which consequently limits the bandwidth. This stimulates a remarkable interest in merging silicon photonics with silicon-based integrated circuits for more efficient inter-chip and intra-chip communication, besides added multifunctional abilities such as on-chip optical modulation, spectroscopy, and sensing applications. However, the development of CMOS-compatible on-chip light sources remains a huge challenge owing to the lack of direct bandgap group IV semiconductors. Recently, GeSn has become a promising solution to overcome this limitation since GeSn becomes a direct bandgap material when sufficient Sn content is incorporated in Ge lattice. Indeed, the indirect-direct bandgap crossover occurs at a Sn content of around 8 atomic percent (at. %) in relaxed GeSn. Increasing the Sn content beyond this threshold improves the bandgap directness and lowers its energy. Photodetector devices made of chemical vapor deposition (CVD) and molecular beam epitaxy (MBE) grown layers and heterostructures have been demonstrated to operate at wavelengths up to 4.6 μm in the mid-infrared (MIR) spectral range. While optically pumped GeSn-based lasers have been reported by many researchers recently, experimental attempts to develop the electrically injected counterparts remain relatively scarce.
To achieve the dense integration of Si-based integrated circuits and silicon photonics, emitters with a small footprint and reduced power consumption are strongly desired. Several efforts have been expended toward this goal. While early GeSn LEDs feature low power consumption of 3.75 W, these devices have a remarkably large footprint area of around 106 μm2. Other LED devices reported later on have two orders of magnitude smaller device sizes of around 31, 400 μm2, but they require more than 4-fold higher power consumption. Various embodiments may relate to a GeSn microscale LED with a record-small footprint of around 1,520 μm2 yet operating at a low dissipated power around 3 W at 80 K and around 10.8 W at room temperature. This may be realized through a cavity LED utilized in a microbridge structure.
The GeSn LED samples may be grown using a low-pressure chemical vapor deposition (CVD) reactor following a multilayer growth to control lattice strain and Sn content.
The microbridge device characterization started by measuring the I-V curves using a source meter unit over a wide bias range of up to 5 V in the forward and reverse biases as shown in
To measure and analyze the LED light emission, a Fourier transform infrared spectroscopy (FTIR) setup may be utilized to measure the spectral emission from the microbridge devices. The setup may include a Bruker Fourier Transform Infrared (FTIR) spectrometer, an indium antimonide (InSb) liquid nitrogen cooled photodetector (PD), a 40× reflective objective lens, and a translation stage. To amplify the InSb PD signal, the spectral emission was fed into a current preamplifier and a lock-in amplifier. The signal was re-entered into the FTIR for data processing. The lock-in technique requires the LED light to take the form of pulses either by mounting a mechanical chopper in the light path or by applying alternating current (AC) drive current to the LED.
The device was also characterized at a cryogenic temperature of 80 K, showing that a clear signal can be measured at a driving current as low as 1 mA.
To investigate why the cavity effect is not achieved in the LEDs and provide a viable pathway towards achieving cavity effects and possibly lasing, thermal and optical simulations may be performed for the LED devices.
The GeSn PIN homojunctions may be grown epitaxially on silicon wafers using step-graded buffer layers allowing the simultaneous control of the Sn incorporation, the lattice strain, and the interface abruptness, while confining the extended defects mainly below the active device layer. This growth protocol may ensure that the PIN homojunctions are of good crystalline quality despite having a Sn content significantly above the equilibrium content. The grown material was used to implement vertical GeSn microbridge LEDs. The operation performance of these LEDs was assessed using electrical and optical characterization. The emission peak was found to be around 2.31 μm at room temperature, which agrees with the estimated Sn content and strain revealed from the XRD RSM measurements. Low-temperature analysis showed an emission peak at a shorter wavelength around 2.08 μm. It was found that the microbridge LED has power dissipation as low as 3 W (at 80K) and 10.8 W (at room temperature), as well as a small footprint of 1,520 μm2. To optimize the device design and layer structure, thermal and optical simulations were performed. The simulations indicate that the efficient thermal dissipation of the current design may help reduce the heat-induced optical losses, and may thus enhance light emission. According to thermal and optical simulations, various embodiments with the GeSnOI substrate may be promising for lasing.
Various embodiments may relate to an electrically pumped emission device. Various embodiments may operate using a direct bandgap configuration. Various embodiments may use a dual insulator material platform, thereby providing superior thermal management. Various embodiments may be free of misfit dislocation or may have fewer misfit dislocation compared to conventional devices and/or may have higher material quality, as various embodiments may use wafer bonding techniques and may have lower Sn content. In various embodiments, the stacked arrangement may be in contact with a solid layer instead of air, thereby providing more thermal conduction paths.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10202301118T | Apr 2023 | SG | national |
