This application claims the priority benefits of Taiwan application serial no. 100135995, filed on Oct. 5, 2011, and Taiwan application serial no. 101104422, filed on Feb. 10, 2012. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of specification.
1. Field of the Invention
The invention relates to a flat panel display technique. Particularly, the invention relates to a light-emitting component (for example, OLED) driving circuit and a related pixel circuit and applications using the same.
2. Description of Related Art
With rapid progress of multimedia society, techniques of semiconductor devices and display devices are also greatly improved. Regarding the displays, since an active matrix organic light-emitting diode (AMOLED) display has advantages of no viewing-angle limitation, low fabrication cost, high response speed (about a hundred times higher than a liquid crystal display), power saving, self luminous, direct current (DC) driving suitable for portable devices, large working temperature range, light weight, and miniaturization and thinness along with hardware equipment, etc. to cope with feature requirements of displays of the multimedia age, the AMOLED has a great development potential to become a novel planar display of a next generation to replace the liquid crystal displays (LCD).
Presently, there are two methods for fabricating an AMOLED panel, and one is to use a low temperature polysilicon (LTPS) thin film transistor (TFT) process technique for fabrication, and another one is to use an a-Si TFT process technique for fabrication. Since the LTPS TFT process technique requires more optical mask processes to cause a high fabrication cost, the LTPS TFT process technique is mainly used in fabrication of middle and small size panels, and the a-Si TFT process technique is mainly used in fabrication of large size panels.
Generally, in the AMOLED panel fabricated according to the LTPS TFT process technique, a type of a TFT in a pixel circuit thereof can be a P-type or an N-type, and sine the P-type TFT has a better driving capability of conducting a positive voltage, the P-type TFT is generally used for implementation. However, in case that the P-type TFT is used to implement the OLED pixel circuit, a current flowing through the OLED is not only changed along with a power supply voltage (Vdd) which may be influenced by an IR drop, but is also changed along with a threshold voltage (Vth) shift of a TFT used for driving the OLED. Therefore, brightness uniformity of the OLED display is accordingly influenced.
Accordingly, an exemplary embodiment of the invention provides a light-emitting component driving circuit including a power unit, a driving unit and a data storage unit. The power unit receives a power supply voltage, and transmits the power supply voltage in response to a light enable signal in a light enable phase. The driving unit is coupled between the power unit and a first end of a light-emitting component, and includes a driving transistor coupled to a first end of the light-emitting component. The driving unit controls a driving current flowing through the light-emitting component in the light enable phase.
The data storage unit includes a storage capacitor, and stores a data voltage (Vdata) and a threshold voltage (Vth) related to the driving transistor through the storage capacitor in a data-writing phase. In the light enable phase, the driving unit generates the driving current flowing through the light-emitting component in response to a cross voltage of the storage capacitor, and the driving current flowing through the light-emitting component is not influenced by the power supply voltage and the threshold voltage of the driving transistor.
In an exemplary embodiment of the invention, a second end of the light-emitting component is coupled to a reference voltage, and in case that the power supply voltage is a variable power supply voltage, the power unit includes a power conduction transistor, where a source thereof receives the variable power supply voltage, and a gate thereof receives the light enable signal.
In an exemplary embodiment of the invention, in case that the power supply voltage is the variable power supply voltage, a first drain/source of the driving transistor is coupled to a drain of the power conduction transistor, a second drain/source of the driving transistor is coupled to the first end of the light-emitting component, and a gate of the driving transistor is coupled to a first end of the storage capacitor. Moreover, a second end of the storage capacitor is coupled to the variable power supply voltage.
In an exemplary embodiment of the invention, in case that the power supply voltage is the variable power supply voltage, the data storage unit further includes a writing transistor and a collection transistor. A gate of the writing transistor receives a writing scan signal, a drain of the writing transistor receives the data voltage, and a source of the writing transistor may be coupled to the second drain/source of the driving transistor and the first end of the light-emitting component (or the source of the writing transistor may be coupled to the first drain/source of the driving transistor and the drain of the power conduction transistor). A gate of the collection transistor receives the writing scan signal, a source of the collection transistor is coupled to the gate of the driving transistor and the first end of the storage capacitor, and a drain of the collection transistor may be coupled to the first drain/source of the driving transistor and the drain of the power conduction transistor (or the drain of the collection transistor may be coupled to the second drain/source of the driving transistor and the first end of the light-emitting component). The light-emitting component is, for example, an organic light-emitting diode, where the first end of the light-emitting component is an anode of the OLED, and the second end of the light-emitting component is a cathode of the OLED. In this case, a level of the reference voltage is substantially not less than a highest level of the data voltage minus a conduction voltage of the OLED (or the level of the reference voltage is substantially not less than the highest level of the data voltage minus the threshold voltage of the driving transistor and the conduction voltage of the OLED). Moreover, the provided light-emitting component driving circuit is an OLED driving circuit.
In an exemplary embodiment of the invention, in case that the power supply voltage is the variable power supply voltage, the data storage unit further initializes the storage capacitor in response to a reset scan signal in a reset phase. In this case, the data storage unit further includes a reset transistor, where a gate and a source thereof are coupled with each other to receive the reset scan signal, and a drain thereof is coupled to the gate of the driving transistor, the source of the collection transistor and the first end of the storage capacitor.
In an exemplary embodiment of the invention, in case that the power supply voltage is the variable power supply voltage, the driving transistor, the power conduction transistor, the writing transistor, the collection transistor and the reset transistor are all P-type transistors.
In an exemplary embodiment of the invention, if the variable power supply voltage is changed to a constant power supply voltage, the first end of the storage capacitor is coupled to the reference voltage before the light enable phase and is coupled to the constant power supply voltage during the light enable phase in response to a switching means.
In an exemplary embodiment of the invention, the second end of the light-emitting component is coupled to a reference voltage, and the power supply voltage can be a constant or a variable power voltage. In this case, the power unit includes a power conduction transistor, where a drain thereof receives the constant or the variable power supply voltage, and a gate thereof receives the light enable signal.
In an exemplary embodiment of the invention, in case that the power supply voltage is the constant or variable power supply voltage, the drain of the driving transistor is coupled to the source of the power conduction transistor, the source of the driving transistor is coupled to the first end of the light-emitting component, and the gate of the driving transistor is coupled to a first end of the storage capacitor. Moreover, a second end of the storage capacitor is coupled to the reference voltage.
In an exemplary embodiment of the invention, in case that the power supply voltage is the constant or variable power supply voltage, the data storage unit further includes a writing transistor and a collection transistor. A gate of the writing transistor receives a writing scan signal, a drain of the writing transistor receives the data voltage, and a source of the writing transistor is coupled to the source of the driving transistor and the first end of the light-emitting component. A gate of the collection transistor receives the writing scan signal, a drain of the collection transistor is coupled to the gate of the driving transistor and the first end of the storage capacitor, and a source of the collection transistor is coupled to the drain of the driving transistor and the source of the power conduction transistor. The light-emitting component is, for example, an organic light-emitting diode, where the first end of the light-emitting component is an anode of the OLED, and the second end of the light-emitting component is a cathode of the OLED. In this case, a level of the reference voltage is substantially not less than a highest level of the data voltage minus a conduction voltage of the OLED.
In an exemplary embodiment of the invention, in case that the power supply voltage is the constant or variable power supply voltage, the data storage unit further initializes the storage capacitor in response to a reset scan signal in a reset phase. In this case, the data storage unit further includes a reset transistor, where a gate and a source thereof are coupled with each other to receive the reset scan signal, and a drain thereof is coupled to the gate of the driving transistor, the drain of the collection transistor and the first end of the storage capacitor.
In an exemplary embodiment of the invention, in case that the power supply voltage is the constant or variable power supply voltage, the driving transistor, the power conduction transistor, the writing transistor, the collection transistor and the reset transistor are all N-type transistors.
In an exemplary embodiment of the invention, the light-emitting component driving circuit is an OLED driving circuit, and the OLED driving circuit sequentially enters the reset phase, the data-writing phase, and the light enable phase.
Another exemplary embodiment of the invention provides an OLED pixel circuit having the aforementioned OLED driving circuit.
Another exemplary embodiment of the invention provides an OLED display panel having the aforementioned OLED pixel circuit.
Another exemplary embodiment of the invention provides an OLED display having the aforementioned OLED display panel.
According to the above descriptions, the invention provides an OLED pixel circuit, and in case that the circuit configuration (5T1C) thereof collocates with suitable operation waveforms, the current flowing through the OLED may not be changed along with the power supply voltage (Vdd) which may be influenced by the IR drop, and may not be varied along with the threshold voltage (Vth) shift of a TFT used for driving the OLED. In this way, the brightness uniformity of the applied OLED display can be substantially improved.
In order to make the aforementioned and other features and advantages of the invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
In the present exemplary embodiment, the power unit 105 receives a power supply voltage Vdd, and transmits the power supply voltage Vdd in response to a light enable signal LE in a light enable phase. Here, the power supply voltage Vdd can be a variable power supply voltage, so that the power supply voltage Vdd is referred to as the variable power supply voltage Vdd hereinafter.
Moreover, the driving unit 107 is coupled between the power unit 105 and an anode of the OLED 101 (i.e. a first end of the light-emitting component), and includes a driving transistor T1 directly coupled to the anode of the OLED 101. The driving unit 107 controls a driving current IOLED flowing through the OLED 101 in the light enable phase.
Moreover, the data storage unit 109 includes a storage capacitor Cst. The data storage unit 109 stores a data voltage Vdata and a threshold voltage Vth(T1) related to the driving transistor T1 through the storage capacitor Cst in a data-writing phase. Moreover, the data storage unit 109 initializes/resets the storage capacitor Cst in response to a reset scan signal S[n−1] in a reset phase. The reset scan signal S[n−1] can be a signal on a previous scan line, and is provided by a gate driving circuit of an (n−1)th stage.
In the present exemplary embodiment, the driving unit 107 generates the driving current IOLED flowing through the OLED 101 in response to a cross voltage of the storage capacitor Cst in the light enable phase, and the driving current IOLED is not influenced by the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1. In other words, the driving current IOLED is non-related to the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1.
Besides, the power unit 105 includes a power conduction transistor T2. Moreover, the data storage unit 109 further includes a writing transistor T3, a collection transistor T4 and a reset transistor T5.
In the present exemplary embodiment, the driving transistor T1, the power conduction transistor T2, the writing transistor T3, the collection transistor T4 and the reset transistor T5 are all P-type transistors, for example, P-type thin film transistors (P-type TFTs). Moreover, an OLED display panel applying the OLED pixel circuit 10 can be fabricated by a TFT process technique of low temperature polysilicon (LTPS), a-Si or a-IGZO, though the invention is not limited thereto.
Moreover, in a circuit configuration of the OLED pixel circuit 10 of
A gate of the writing transistor T3 receives a writing scan signal S[n] (the writing scan signal S[n] can be a current scan line signal, and is provided by a gate driving circuit of an nth stage), a drain of the writing transistor T3 receives the data voltage Vdata, and a source of the writing transistor T3 is coupled to the second drain/source of the driving transistor T1 and the anode of the OLED 101. A gate of the collection transistor T4 receives the writing scan signal S[n], a source of the collection transistor T4 is coupled to the gate of the driving transistor T1 and the first end of the storage capacitor Cst, and a drain of the collection transistor T4 is coupled to the first drain/source of the driving transistor T1 and the drain of the power conduction transistor T2. A gate of the reset transistor T5 is coupled to a source thereof to receive the reset scan signal S[n−1], and a drain of the reset transistor T5 is coupled to the gate of the driving transistor T1, the source of the collection transistor T4 and the first end of the storage capacitor Cst.
In this case, a cathode (i.e. a second end of the light-emitting component) of the OLED 101 is coupled to a reference voltage Vss, where a level of the reference voltage Vss is substantially not less than a highest level of the data voltage Vdata minus a conduction voltage (Voled_th) of the OLED 101, i.e. Vss≧Vdata−Voled_th.
Moreover, during an operation process of the OLED pixel circuit 10 of
Moreover, the light enable signal LE has the high voltage level VH in the reset phase P1 and the data-writing phase P2, and has a second low voltage level VL2 (for example, −6V, though the invention is not limited thereto) different to the first low voltage level LV1 in the light enable phase P3. Furthermore, the reset scan signal S[n−1] has the second low voltage level VL2 in the reset phase P1, and has the high voltage level VH in the data-writing phase P2 and the light enable phase P3. Besides, the writing scan signal S[n] has the second low voltage level VL2 in the data-writing phase P2, and has the high voltage level VH in the reset phase P1 and the light enable phase P3.
In other words, it is obvious in
Therefore, in the reset phase P1, since only the reset scan signal S[n−1] is enabled, a voltage at the gate of the driving transistor T1 is equal to VL2+Vth(T5) in response to a turn-on state of the reset transistor T5, where Vth(T5) is a threshold voltage of the reset transistor T5. Meanwhile, the power conduction transistor T2 is in a turn-off state in response to disabling of the light enable signal LE, which avails avoiding a miss operation of sudden light up of the OLED 101 and maintaining a contrast of a display image. Moreover, the writing transistor T3 and the collection transistor T4 are also in the turn-off state in response to disabling of the writing scan signal S[n].
Then, in the data-writing phase P2, since only the writing scan signal S[n] is enabled, the writing transistor T3 and the collection transistor T4 are both in the turn-on state. In this case, the data voltage Vdata is transmitted to the storage capacitor Cst through the writing transistor T3 and the diode-connected driving transistor T1, so that the voltage at the gate of the driving transistor T1 is equal to Vdata−Vth(T1). In the data-writing phase P2, the second drain/source of the driving transistor T1 is substantially regarded as a source, and the first drain/source of the driving transistor T1 is substantially regarded as a drain.
Meanwhile, the reset transistor T5 and the power conduction transistor T2 are both in the turn-off state in response to disabling of the reset scan signal S[n−1] and the light enable signal LE. In addition, since the level of the reference voltage Vss is substantially not less than the highest level of the data voltage Vdata minus the conduction voltage (Voled_th) of the OLED 101, i.e. Vss≧Vdata−Voled_th, the OLED 101 is avoided to have the miss operation of sudden light up in the data-writing phase P2.
It should be noticed that the level of the reference voltage Vss of
Finally, in the light enable phase P3, since only the light enable signal LE is enabled, the writing transistor T3, the collection transistor T4 and the reset transistor T5 are all in the turn-off state, and the driving transistor T1 and the power conduction transistor T2 are in the turn-on state. Meanwhile, since the second drain/source of the driving transistor T1 is changed to the drain, and the first drain/source of the driving transistor T1 is changed to the source, such that in response to the turn-on state of the power conduction transistor T2, the voltage of the source of the driving transistor T1 is substantially equal to VH, and the voltage of the gate of the driving transistor T1 is increased to Vdata−Vth(T1)+(VH−VL1) in response to a capacitor coupling effect of the storage capacitor Cst. In this way, the driving transistor T1 generates the driving current IOLED that is not influenced by the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1 to flow through the OLED 101.
In detail, in the light enable phase P3, the driving current IOLED generated by the driving transistor T1 can be represented by a following equation 1:
Where, K is a current constant related to the driving transistor T1.
Moreover, since a source gate voltage (Vsg) of the driving transistor T1 is already known, i.e.: Vsg=VH−[Vdata−Vth(T1)+(VH−VL1)].
Therefore, substituting the known source gate voltage (Vsg) of the driving transistor T1 into the equation 1, the equation 1 can be rewritten as:
and the equation 2 can be further simplified as a following equation 3:
Therefore, the driving transistor T1 can generate the driving current IOLED that is not influenced by the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1 in the light enable phase P3.
In other words, according to the equation 3, it is known that the driving current IOLED flowing through the OLED 101 is non-related to the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1, and is related to the data voltage Vdata. In this way, a threshold voltage variation of the TFT caused by process factors can be compensated, and meanwhile the problem that the power supply voltage Vdd is changed due to influence of the IR drop is resolved.
On the other hand,
The gate of the writing transistor T3 receives the writing scan signal S[n], the drain of the writing transistor T3 receives the data voltage Vdata, and the source of the writing transistor T3 is coupled to the first drain/source of the driving transistor T1 and the drain of the power conduction transistor T2. The gate of the collection transistor T4 receives the writing scan signal S[n], the source of the collection transistor T4 is coupled to the gate of the driving transistor T1 and the first end of the storage capacitor Cst, and the drain of the collection transistor T4 is coupled to the second drain/source of the driving transistor T1 and the anode of the OLED 101. The gate and the source of the reset transistor T5 are coupled with each other to receive the reset scan signal S[n−1], and the drain of the reset transistor T5 is coupled to the gate of the driving transistor T1, the source of the collection transistor T4 and the first end of the storage capacitor Cst.
In this case, the cathode of the OLED 101 is coupled to the reference voltage Vss, and the level of the reference voltage Vss is substantially not less than the highest level of the data voltage Vdata minus the threshold voltage Vth(T1) of the driving transistor T1 and the conduction voltage Voled_th of the OLED 101, i.e. Vss≧Vdata−Vth(T1)−Voled_th.
It should be noticed that the operation waveforms of
Then, in the data-writing phase P2, since only the writing scan signal S[n] is enabled, the writing transistor T3 and the collection transistor T4 are both in the turn-on state. In this case, the data voltage Vdata is transmitted to the storage capacitor Cst through the writing transistor T3 and the diode-connected driving transistor T1, so that the voltage at the gate of the driving transistor T1 is equal to Vdata−Vth(T1). In the data-writing phase P2, the second drain/source of the driving transistor T1 is substantially regarded as a source, and the first drain/source of the driving transistor T1 is substantially regarded as a drain.
Meanwhile, the reset transistor T5 and the power conduction transistor T2 are both in the turn-off state in response to disabling of the reset scan signal S[n−1] and the light enable signal LE. In addition, since the level of the reference voltage Vss is substantially not less than the highest level of the data voltage Vdata minus the threshold voltage Vth(T1) of the driving transistor T1 and the conduction voltage (Voled_th) of the OLED 101, i.e. Vss≧Vdata−Vth(T1)−Voled_th, the OLED 101 is avoided to have the miss operation of sudden light up in the data-writing phase P2.
Finally, in the light enable phase P3, since only the light enable signal LE is enabled, the writing transistor T3, the collection transistor T4 and the reset transistor T5 are all in the turn-off state, and the driving transistor T1 and the power conduction transistor T2 are in the turn-on state. Meanwhile, since the second drain/source of the driving transistor T1 is changed to the drain, and the first drain/source of the driving transistor T1 is changed to the source, such that in response to the turn-on state of the power conduction transistor T2, the voltage of the source of the driving transistor T1 is substantially equal to VH, and the voltage of the gate of the driving transistor T1 is increased to Vdata−Vth(T1)+(VH−VL1) in response to the capacitor coupling effect of the storage capacitor Cst. In this way, the driving transistor T1 generates the driving current IOLED (shown as the equations 1-3) that is not influenced by the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1 to flow through the OLED 101. Obviously, the circuit configuration of
On the other hand,
Moreover, the second end of the storage capacitor Cst is respectively coupled to the constant power supply voltage Vdd and the reference voltage Vss through a first switching transistor T6 and a second switching transistor T7 (which are P-type transistors, for example, P-type TFTs, though the invention is not limited thereto). A gate of the first switching transistor T6 receives the light enable signal LE, a source of the first switching transistor T6 is coupled to the constant power supply voltage Vdd, and a drain of the first switching transistor T6 is coupled to the second end of the storage capacitor Cst. A gate of the second switching transistor T7 receives a complementary signal
Similarly, the gate of the writing transistor T3 receives the writing scan signal S[n], the drain of the writing transistor T3 receives the data voltage Vdata, and the source of the writing transistor T3 is coupled to the second drain/source of the driving transistor T1 and the anode of the OLED 101. The gate of the collection transistor T4 receives the writing scan signal S[n], the source of the collection transistor T4 is coupled to the gate of the driving transistor T1 and the first end of the storage capacitor Cst, and the drain of the collection transistor T4 is coupled to the first drain/source of the driving transistor T1 and the drain of the power conduction transistor T2. The gate and the source of the reset transistor T5 are coupled with each other to receive the reset scan signal S[n−1], and the drain of the reset transistor T5 is coupled to the gate of the driving transistor T1, the source of the collection transistor T4 and the first end of the storage capacitor Cst.
In this case, the cathode of the OLED 101 is coupled to the reference voltage Vss, and the level of the reference voltage Vss is substantially not less than the highest level of the data voltage Vdata minus the conduction voltage Voled_th of the OLED 101, i.e. Vss≧Vdata−Voled_th.
Moreover, in the operation process of the OLED pixel circuit 10 of
Meanwhile, the power conduction transistor T2 is in the turn-off state in response to disabling of the light enable signal LE, which avails avoiding the miss operation of sudden light up of the OLED 101 and maintains a contrast of a display image. Moreover, the first switching transistor T6 is in the turn-off state in response to disabling of the light enable signal LE. In addition, the writing transistor T3 and the collection transistor T4 are also in the turn-off state in response to disabling of the writing scan signal S[n].
Then, in the data-writing phase P2, since the writing scan signal S[n] and the complementary signal
Meanwhile, the reset transistor T5 and the power conduction transistor T2 are both in the turn-off state in response to disabling of the reset scan signal S[n−1] and the light enable signal LE. In addition, since the level of the reference voltage Vss is substantially not less than the highest level of the data voltage Vdata minus the conduction voltage (Voled_th) of the OLED 101, i.e. Vss≧Vdata−Voled_th, the OLED 101 is avoided to have the miss operation of sudden light up in the data-writing phase P2.
Finally, in the light enable phase P3, since only the light enable signal LE is enabled, the writing transistor T3, the collection transistor T4, the reset transistor T5 and the second switching transistor T7 are all in the turn-off state, and the driving transistor T1 and the power conduction transistor T2 and the first switching transistor T6 are in the turn-on state. Meanwhile, since the second drain/source of the driving transistor T1 is changed to the drain, and the first drain/source of the driving transistor T1 is changed to the source, such that in response to the turn-on state of the power conduction transistor T2, the voltage of the source of the driving transistor T1 is substantially equal to VH, and the voltage of the gate of the driving transistor T1 is increased to Vdata−Vth(T1)+(VH−VL1) in response to the capacitor coupling effect of the storage capacitor Cst. In this way, the driving transistor T1 generates the driving current IOLED (shown as the equations 1-3) that is not influenced by the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1 to flow through the OLED 101. Obviously, the circuit configuration of
On the other hand,
Similarly, the second end of the storage capacitor Cst is respectively coupled to the constant power supply voltage Vdd and the reference voltage Vss through the first switching transistor T6 and the second switching transistor T7. A gate of the first switching transistor T6 receives the light enable signal LE, a source of the first switching transistor T6 is coupled to the constant power supply voltage Vdd, and a drain of the first switching transistor T6 is coupled to the second end of the storage capacitor Cst. A gate of the second switching transistor T7 receives a complementary signal
The gate of the writing transistor T3 receives the writing scan signal S[n], the drain of the writing transistor T3 receives the data voltage Vdata, and the source of the writing transistor T3 is coupled to the first drain/source of the driving transistor T1 and the drain of the power conduction transistor T2. The gate of the collection transistor T4 receives the writing scan signal S[n], the source of the collection transistor T4 is coupled to the gate of the driving transistor T1 and the first end of the storage capacitor Cst, and the drain of the collection transistor T4 is coupled to the second drain/source of the driving transistor T1 and the anode of the OLED 101. The gate and the source of the reset transistor T5 are coupled with each other to receive the reset scan signal S[n−1], and the drain of the reset transistor T5 is coupled to the gate of the driving transistor T1, the source of the collection transistor T4 and the first end of the storage capacitor Cst.
In this case, the cathode of the OLED 101 is coupled to the reference voltage Vss, and the level of the reference voltage Vss is substantially not less than the highest level of the data voltage Vdata minus the threshold voltage Vth(T1) of the driving transistor T1 and the conduction voltage Voled_th of the OLED 101, i.e. Vss≧Vdata−Vth(T1)−Voled_th.
It should be noticed that the operation waveforms of
Meanwhile, the power conduction transistor T2 is in the turn-off state in response to disabling of the light enable signal LE, which avails avoiding the miss operation of sudden light up of the OLED 101 and maintains a contrast of a display image. Moreover, the first switching transistor T6 is in the turn-off state in response to disabling of the light enable signal LE. In addition, the writing transistor T3 and the collection transistor T4 are also in the turn-off state in response to disabling of the writing scan signal S[n].
Then, in the data-writing phase P2, since the writing scan signal S[n] and the complementary signal
Meanwhile, the reset transistor T5 and the power conduction transistor T2 are both in the turn-off state in response to disabling of the reset scan signal S[n−1] and the light enable signal LE. In addition, since the level of the reference voltage Vss is substantially not less than the highest level of the data voltage Vdata minus the threshold voltage Vth(T1) of the driving transistor T1 and the conduction voltage (Voled_th) of the OLED 101, i.e. Vss≧Vdata−Vth(T1)−Voled_th, the OLED 101 is avoided to have the miss operation of sudden light up in the data-writing phase P2.
Finally, in the light enable phase P3, since only the light enable signal LE is enabled, the writing transistor T3, the collection transistor T4, the reset transistor T5 and the second switching transistor T7 are all in the turn-off state, and the driving transistor T1 and the power conduction transistor T2 and the first switching transistor T6 are in the turn-on state. Meanwhile, since the second drain/source of the driving transistor T1 is changed to the drain, and the first drain/source of the driving transistor T1 is changed to the source, such that in response to the turn-on state of the power conduction transistor T2, the voltage of the source of the driving transistor T1 is substantially equal to VH, and the voltage of the gate of the driving transistor T1 is increased to Vdata−Vth(T1)+(VH−VL1) in response to the capacitor coupling effect of the storage capacitor Cst. In this way, the driving transistor T1 generates the driving current IOLED (shown as the equations 1-3) that is not influenced by the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1 to flow through the OLED 101. Obviously, the circuit configuration of
On the other hand,
Moreover, regarding a circuit configuration of the OLED pixel circuit 10 of
The gate of the writing transistor T3 receives the writing scan signal S[n], the drain of the writing transistor T3 receives the data voltage Vdata, and the source of the writing transistor T3 is coupled to the source of the driving transistor T1 and the anode of the OLED 101. The gate of the collection transistor T4 receives the writing scan signal S[n], the source of the collection transistor T4 is coupled to the gate of the driving transistor T1 and the first end of the storage capacitor Cst, and the drain of the collection transistor T4 is coupled to the drain of the driving transistor T1 and the source of the power conduction transistor T2. The gate and the source of the reset transistor T5 are coupled with each other to receive the reset scan signal S[n−1], and the drain of the reset transistor T5 is coupled to the gate of the driving transistor T1, the source of the collection transistor T4 and the first end of the storage capacitor Cst.
In this case, the cathode of the OLED 101 is coupled to the reference voltage Vss, and the level of the reference voltage Vss is substantially not less than the highest level of the data voltage Vdata minus the conduction voltage Voled_th of the OLED 101, i.e. Vss≧Vdata−Voled_th.
Moreover, during an operation process of the OLED pixel circuit 10 of
Similarly, it is obvious in
Therefore, in the reset phase P1, since only the reset scan signal S[n−1] is enabled, the voltage at the gate of the driving transistor T1 is equal to VH−Vth(T5) in response to a turn-on state of the reset transistor T5. Meanwhile, the power conduction transistor T2 is in a turn-off state in response to disabling of the light enable signal LE, which avails avoiding a miss operation of sudden light up of the OLED 101 and maintaining a contrast of a display image. Moreover, the writing transistor T3 and the collection transistor T4 are also in the turn-off state in response to disabling of the writing scan signal S[n].
Then, in the data-writing phase P2, since only the writing scan signal S[n] is enabled, the writing transistor T3 and the collection transistor T4 are both in the turn-on state. In this case, the data voltage Vdata is transmitted to the storage capacitor Cst through the writing transistor T3 and the diode-connected driving transistor T1, so that the voltage at the gate of the driving transistor T1 is equal to Vdata+Vth(T1).
Meanwhile, the reset transistor T5 and the power conduction transistor T2 are both in the turn-off state in response to disabling of the reset scan signal S[n−1] and the light enable signal LE. In addition, since the level of the reference voltage Vss is substantially not less than the highest level of the data voltage Vdata minus the conduction voltage (Voled_th) of the OLED 101, i.e. Vss Vdata−Voled_th, the OLED 101 is avoided to have the miss operation of sudden light up in the data-writing phase P2.
Finally, in the light enable phase P3, since only the light enable signal LE is enabled, the writing transistor T3, the collection transistor T4 and the reset transistor T5 are all in the turn-off state, and the driving transistor T1 and the power conduction transistor T2 are in the turn-on state. Meanwhile, the driving current IOLED that is not influenced by the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1 is generated in response to the high voltage level VH of the constant power supply voltage Vdd to flow through the OLED 101. Since the voltage of the gate of the driving transistor T1 is Vdata+Vth(T1), and the voltage of the source of the driving voltage T1 is substantially the conduction voltage Voled_th of the OLED 101, in the light enable phase P3, the driving current IOLED generated by the driving transistor T1 can be represented by a following equation 4:
Where, K is a current constant related to the driving transistor T1.
Moreover, since a gate source voltage (Vgs) of the driving transistor T1 is already known, i.e.: Vgs=Vdata+Vth(T1)−Voled_th.
Therefore, substituting the known gate source voltage (Vgs) of the driving transistor T1 into the equation 4, the equation 4 can be rewritten as:
and the equation 5 can be further simplified as a following equation 6:
Therefore, the driving transistor T1 can generate the driving current IOLED that is not influenced by the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1 in the light enable phase P3.
In other words, according to the equation 6, it is known that the driving current IOLED flowing through the OLED 101 is non-related to the power supply voltage Vdd and the threshold voltage Vth(T1) of the driving transistor T1, and is substantially only related to the data voltage Vdata. In this way, a threshold voltage variation of the TFT caused by process factors can be compensated, and meanwhile the problem that the power supply voltage Vdd is changed due to influence of the IR drop is resolved.
On the other hand, the drain of the power conduction transistor T2 of
Therefore, the circuit configuration of the OLED pixel circuit 10 disclosed by the aforementioned exemplary embodiment is 5T1C (i.e. 5 TFTs+1 capacitor), and in collaboration with suitable operation waveforms (shown in
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Number | Date | Country | Kind |
---|---|---|---|
100135995 | Oct 2011 | TW | national |
101104422 | Feb 2012 | TW | national |