Patent Grant
7463224
The Japanese priority applications Numbers 2003-177267 and 2004-170835 upon which this patent application is based are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a display device, and in particular to a digital display device having a display element such as an emissive element in each pixel and in which the elements are operated using digital signals to represent gradations.
2. Description of the Related Art
Because electroluminescence (hereinafter simply referred to as “EL”) display devices in which a self-emitting EL element, for example, is used as an emissive element in each pixel have advantages such as that the device is thin, self-emitting, and consumes less power, EL display devices have attracted much attention as alternatives to display devices such as liquid crystal display (LCD) and cathode ray tube (CRT) display devices.
In particular, a high resolution display can be achieved by an active matrix EL display device in which a switching element such as a thin film transistor (hereinafter simply referred to as “TFT”) for individually controlling an EL element is provided in each pixel and the EL element in each pixel is controlled.
In an active matrix EL display device, a plurality of pixels, a plurality of selection lines (gate lines) extending along a horizontal scan direction (row direction), a plurality of data lines and power supply lines extending along a vertical scan direction (column direction) are provided over a substrate, and each pixel has an organic EL element, a selection TFT, a driver TFT, and a storage capacitor. In this structure, a selection signal is output to a selection line so that each of the selection TFTs connected to this line is switched on, a data signal (analog voltage signal) output onto the data line is supplied to the storage capacitor and to the driver TFT, the storage capacitor stores a voltage corresponding to the data signal for a predetermined period, and the driver TFT is operated to control electric current to be supplied from the power supply line through the organic EL element.
In addition to a method for driving each organic EL element with an analog data signal, a method is reported in which each organic EL element is driven with a digital data signal as shown in
The driver TFT 22 is switched on and off according to the digital data signal applied to its gate and the current on-off TFT 26 controls whether or not to supply the current flowing through the driver TFT 22 to the organic EL element 28 to allow the organic EL element 28 to emit light. The current on-off TFT 26 is controlled to be switched on and off a plurality of times during one frame period (one screen display period) through time divisional control corresponding to a number of bits in the digital data, to thereby control the total cumulative light emission period during one frame period for the organic EL element 28. Because light emission intensity as recognized by a viewer differs depending on the length of light emission period within one frame period, with the time divisional light emission control as described, it is possible to represent gradations. In other words, light emission gradation can be represented by merely controlling the length of light emission period of an organic EL element 28 during one frame period.
When a pixel circuit as shown in
In a circuit structure as shown in
In a matrix type display device, a plurality of pixels each having a circuit structure as shown in
In addition, in the time divisional digital gradation driving method it is necessary to provide subfield periods each determined by dividing one frame period by a number equal to a number of data bits determined corresponding to the number of display gradations and to output a data signal in each subfield period. Therefore, compared to a method for achieving a gradation display with an analog signal, for example, the transmission speed of the data signal must be increased and a higher and higher transmission speed would be required as the number of display gradations is increased. However, as described above, the parasitic capacitance connected to the data line to which the data signal is to be output is large, and, thus, it is difficult to output a data signal having a large amplitude to allow sufficient control to switch on and off the driver transistor 22 with a sufficiently high speed, to the data line to which a large parasitic capacitance is connected. Therefore, it is not possible to drive the data line with a high speed in order to increase the number of display gradations and the number of gradations that can be displayed is limited.
The present invention therefore provides a digital light emitting device or display device in which a simple driver circuit is employed and to a digital light emitting device or display device which can be driven at a high speed and in which gradation display can be easily achieved.
According to one aspect of the present invention, there is provided a light emitting device comprising a driver transistor provided between an emissive element and a power supply, for controlling supply of power from the power supply to the emissive element to drive the emissive element; a control transistor for receiving a digital data signal on a gate and for controlling whether or not to fix a gate potential of the driver transistor to a predetermined potential based on the digital data signal; and a control capacitor connected between a gate of the driver transistor and a control line to which a control pulse signal for controlling a light emission period of the emissive element is supplied, wherein during the light emission period defined by the control pulse signal, the gate potential of the driver transistor is controlled to be shifted or not shifted to a potential corresponding to the control pulse signal based on a digital data signal supplied to the gate of the control transistor and a supply operation of power through the driver transistor to the emissive element is controlled.
According to another aspect of the present invention, there is provided a display device comprising a driver transistor having a first conductive region connected to a display element and a second conductive region connected to a power supply; a control transistor for receiving a digital data signal on a gate and for controlling electrical connection between the power supply and a gate of the driver transistor; and a control capacitor electrically connected between a control line to which a control pulse signal for controlling an element operation period of the display element is applied and a point between a gate of the driver transistor and the control transistor; wherein during the element operation period defined by the control pulse signal a gate potential of the driver transistor is controlled to be shifted or not shifted to a potential corresponding to the control pulse signal based on a digital data signal supplied to the gate of the control transistor and a supply operation of power through the driver transistor to the display element is controlled.
According to another aspect of the present invention, there is provided a display device having a plurality of pixels, wherein each pixel comprises a selection transistor connected to a selection line to which a selection signal is supplied and a data line to which a digital data signal is supplied; an emissive element; a driver transistor provided between the emissive element and a power supply and for controlling supply of power from the power supply to the emissive element to drive the emissive element; a control transistor for receiving a digital data signal on a gate through the selection transistor and for controlling whether or not to fix a gate potential of the driver transistor to a predetermined potential based on the digital data signal; and a control capacitor connected between the gate of the driver transistor and a control line to which a control pulse signal for controlling an element operation period of the emissive element is applied. In addition, during the element operation period defined by the control pulse signal, the gate potential of the driver transistor is controlled to be shifted or not shifted to a potential corresponding to the control pulse signal based on the digital data signal supplied to the gate of the control transistor and s supply operation of power through the driver transistor to the emissive element is controlled.
As described, according to the present invention, it is not necessary to directly control an operation of a driver transistor for controlling, with a digital data signal, supply of power to a display element such as, for example, an organic EL element (power supply operation). With the present invention, the digital data signal is only required to control the operation of the control transistor, that is, switching on and off of the control transistor, to control whether or not the gate potential of the driver transistor is to be fixed to a predetermined potential such as a power supply. In other words, the digital data signal only needs an amplitude for controlling switching on and off of the control transistor and, thus, the amplitude can be reduced compared to a structure in which the operation of the driver transistor is directly controlled. Therefore, it is possible to employ a simple circuit at the processor and output sections for a data signal and the power consumption can be reduced.
In addition, because it is possible to drive the device using a digital data signal having a smaller amplitude, for example, a voltage resistance and a charge supply capability of the selection transistor in each pixel placed on a signal supply route of the digital data signal need not be significantly increased. In addition, even when a storage capacitor for storing a voltage corresponding to the digital data signal for a predetermined period is to be provided, it is possible to use a capacitor with a small capacitance. These transistor and storage capacitor correspond to parasitic capacitances (capacity load) electrically connected to the data line. With the present invention, it is possible to reduce the parasitic capacitance, and thus, it is easy to increase the transfer speed of the data signal. As a result, the requirements for increasing the number of display gradations are simplified.
According to another aspect of the present invention, it is preferable that, in the light emitting device or in the display device, the digital data signal is a digital signal having a plurality of bits, one frame period corresponding to one screen display period is divided into a number of subfield periods, the number corresponding to a number of bits of the digital data signal, and a digital signal of each bit in the digital data signal is supplied to the control transistor in each subfield period.
Moreover, the subfield period may be correlated to each bit of the digital data signal, and a signal having a pulse width corresponding to an element operation period within each subfield period can be supplied to the control line as a control pulse signal. In this structure, it is possible to effectively represent a multi-gradation by assigning weights to each bit in the digital data. It is possible to set the element operation period (light emission period or display period), that is, the pulse width of the control pulse signal, during the subfield period to a width corresponding to a bit of the digital data signal, more specifically, the digit of the bit to accommodate this configuration.
The amplitude of the control pulse signal (in particular, level of the pulse signal) may be set to an amplitude necessary to shift the gate potential of the driver transistor when the potential is not fixed by the control transistor and to switch on and off the power supply operation to the emissive element by the driver transistor around the shifting operation. The control pulse signal is common to all pixels and is required to be output only once each subfield period, and, even when the amplitude of the control pulse signal is large, because the frequency as a pulse signal is low, it is possible to inhibit an increase in the power consumption.
As described, according to the present invention, in a device which emits light for which achieves a display based on digital data, it is only necessary to supply a digital data signal of a minimum amplitude to a data line in which the parasitic capacitance is maintained low, and thus, it is possible to employ a simple driver circuit to realize such a device. Because of this, it is also possible to reduce the power consumption of the device.
Moreover, because it is possible to output a digital data signal at a high speed, a multi-gradation display can be achieved and it is possible to further increase the number of gradations.
A preferred embodiment of the present invention will now be described referring to the drawings.
In the structure illustrated in
The driver TFT 36 is connected between the anode of the organic EL element 40 and the EL power supply and controls supply of the current, that is, whether or not current is to be supplied, from the EL power supply to the organic EL element 40 based on a voltage applied to a gate of the driver TFT 36. In the present embodiment, the driver TFT 36 is formed from a p-channel TFT and has a source (first conductive region) connected to the EL power supply and a drain (second conductive region) connected to the anode of the organic EL element 40.
The control TFT 32 in the illustrated structure is made of a p-channel TFT and receives, on a gate, a voltage corresponding to a digital data signal supplied through the selection TFT 30, that is, data of “1” or “0”. A source (first conductive region) of the control TFT 32 is connected to a predetermined constant voltage power supply and a drain (second conductive region) of the control TFT 32 is connected to the gate (control terminal) of the driver TFT 36. Because of this, when the control TFT 32 is switched on, the gate of the driver TFT 36 is connected to the constant potential power supply through the source and drain of the control TFT 32 and a gate voltage V2 of the driver TFT 36 is fixed to this constant voltage. The constant voltage may be a constant voltage which fixes the driver TFT 36 to an on state or an off state (in the illustrated structure, off state). In the structure of
The storage capacitor 34 for maintaining a gate voltage V1 of the gate of the control TFT 32 at a voltage corresponding to the supplied digital data signal for a predetermined period (at least for one subfield period which will be described) is connected to the gate of the control TFT 32. More specifically, in the illustrated structure of
In the illustrate structure, the selection TFT 30 is an n-channel TFT. A gate of the selection TFT 30 is connected to a gate line GL, a drain of the selection TFT 30 is connected to a data line DL, and a source of the selection TFT 30 is connected to the gate of the control TFT 32 and to the storage capacitor 34.
In addition, a control capacitor 38 is connected between a point between the drain of the control TFT 32 and the gate of the driver TFT 36 and a control line CPL. The control capacitor 38 maintains, while the control TFT 32 is switched on and the gate of the driver TFT 36 is connected to the EL power supply Pvdd, a potential difference between the gate of the driver TFT 36, that is, the EL power supply Pvdd, and the control line CPL (prevents short-circuiting between the control line CPL and the EL power supply) When the control TFT 32 is switched off, the gate of the driver TFT 36 is disconnected from the EL power supply Pvdd, and the gate voltage V2 becomes a non-fixed state, the gate voltage V2 is set to the potential of the control line CPL, that is, a voltage corresponding to the control pulse signal. Therefore, when a control pulse signal having a pulse width for defining the light emission period of the organic EL element 40 is output to the control line CPL, the gate voltage V2 is shifted by an amount corresponding to the amplitude of the pulse signal and is maintained at this voltage until the next changing of the pulse signal voltage.
An operation of the pixel circuit of the present embodiment will now be described in more detail referring to a timing chart shown in
Each subfield period includes a write period WP, in which the digital data signal of corresponding bit is written to each pixel, and a display (light emission) period DP, in which the written data is displayed (light is emitted). The write period WP is constant for every subfield period and the length of the display period DP is set based on the corresponding bit.
As shown in
The time divisional digital gradation display takes advantage of vision persistence of human eyes. More specifically, as described above, the total length of the cumulative period of light emission during one frame period is adjusted so that the recognized brightness is controlled corresponding to the length of the light emission period. Because a light emission period DP in the subfield period is longer for an upper bit, a plurality of writing period must be provided in each frame period and the total display period is limited. However, with such a structure, it is possible to represent gradations which are bright and have sufficient brightness difference.
When, during a first subfield period SF1, a selection signal on the gate line GL connected to the pixel of interest becomes an H level as shown in
The digital data signal may be maintained in the “1” level or “0” level to be written to the corresponding pixel during the entire period (one horizontal scan period) in which the selection signal (here, H level) is output to the corresponding gate line. Alternatively, when data is to be sequentially written to pixels of each column connected to one horizontal scan line (one gate line) in order, it is also possible to output a digital data signal to the corresponding data line in the same order.
With this configuration, data for one frame of each pixel in the data video signal is stored using, for example, a desired frame memory and the stored data is output to the corresponding data line in order from the lower bit.
Returning to the pixel of interest, as shown in
After the write period WP in the first subfield period (SF1) is completed and the control pulse signal on the control line CPL changes to the L level, the gate voltage V2 of the driver TFT 36 which has been fixed to the H level corresponding to the H level of the control pulse signal as described above becomes L level following the level change of the control pulse signal. With this process, the driver TFT 36 becomes an on state and a current is supplied from the EL power supply Pvdd through the source and drain of the driver transistor 36 to the organic EL element 40, so that light is emitted from the organic EL element 40. When the light emission period DP is completed, the timing moves to the next subfield period (SF2), the control pulse signal on the control line CPL again becomes the H level, the gate voltage V2 of the driver TFT 36 becomes the desired H level corresponding to the control pulse signal, the driver TFT 36 is switched off, and emission of light by the organic EL element 40 is stopped.
When the supplied digital data signal is “0”, the gate voltage V1 of the control TFT 32 becomes L level. In this configuration, the control TFT 32 is switched on and the gate and the source of the driver TFT 36 are short-circuited and are set to the EL power supply voltage Pvdd. Thus, the gate voltage V2 of the driver TFT 36 maintains the H level even when the control pulse signal becomes the L level during the display period DP, and, because the off state is maintained, no light is emitted from the organic EL element 40.
Therefore, only in a pixel to which a digital data signal of “1” is supplied, the driver TFT 36 is switched on corresponding to the L level of the control pulse signal and light is emitted from the organic EL element 40 during the period when the control pulse signal on the control line CPL becomes an L level, that is, during the period corresponding to the pulse width of the control pulse signal designating an element operation period.
As an example configuration, the H level of the selection signal and the control pulse signal may be set to 8V and the L level of the selection signal and the control pulse signal may be set to −4V, the H level or “1” of the digital data signal may be set to 5V, and the L level or “0” of the digital data signal may be set to 0V. When the gate voltage of the driver TFT is directly controlled with a digital data signal as described referring to
When the timing moves to the second subfield period (SF2) and a selection signal of H level is applied to the gate line, because the second bit of the digital data signal for the pixel of interest is “0”, the voltage of the digital data signal applied through the selection TFT 30 and stored in the storage capacitor 34 becomes a predetermined L level corresponding to “0”. Therefore, during the second subfield period SF2, that is, during the period until the gate line becomes the H level during the next, third subfield period SF3 and a digital data signal of the next bit is written, the gate voltage V1 of the control TFT 32 is maintained at the L level and the control TFT 32 is maintained in the on state. Thus, the gate of the driver TFT 36 is fixed to the same potential as that of the EL power supply.
Therefore, even when the control pulse signal on the control line CPL becomes an L level in this state, because the gate of the driver TFT 36 is connected to the EL power supply, the gate voltage V2 is maintained at the H level. Thus, the driver TFT 36 maintains its off state, no current is supplied to the organic EL element 40, and no light is emitted from the organic EL element.
Then, when the timing moves to the third subfield period (SF3) and a selection signal of H level is again applied to the gate line, because the third bit of the digital data signal for the pixel of interest is “1” similar to the SF1 period, during the SF3 period, the gate voltage V1 of the control TFT 32 is maintained at the H level by the storage capacitor 34 and the off state of the control TFT 32 is maintained. Because of this configuration, when the control pulse signal on the control line CPL becomes the L level corresponding to the SF3 period, during this period (DP), the driver TFT 36 is switched on and light is emitted from the organic EL element 40. Here, the length of the display period DP in the SF3 period, that is, the L level period of the control pulse signal is set to four times the length of the display period DP of the SF1 period as described above. Therefore, the length of the light emission period of the organic EL element 40 in the SF3 period is four times that in the SF1 period.
When the timing moves to the fourth subfield period (SF4) and a selection signal of H level is again applied to the gate line, because the fourth bit of the digital data signal is “0” similar to the SF2 period, the control TFT 32 is maintained in its on state, the driver TFT 36 is maintained in its off state even when the control pulse signal changes to the L level, and no light is emitted from the organic EL element 40.
In a pixel to which a digital data signal of “0101” is supplied, light is emitted from the organic EL element 40 for five unit periods during one frame period which comprises subfields SF1-SF4. When the supplied digital data signal is “1111”, for example, light is emitted from the organic EL element 40 during all display periods DP in subfields SF1-SF4 so that a fifteenth gradation which represents the maximum brightness is realized. When, on the other hand, the supplied digital data signal is “0000”, no light is emitted and a zeroth gradation which represents the minimum brightness is realized. In this manner, according to the present embodiment, each pixel can display any one of 16 gradations (displays of 16 different brightness) in one frame period, and, for example, in the pixel of interest described referring to
According to the present embodiment, the control TFT 32 is the structure which is switched on and off by a digital data signal. The control TFT 32 is only required to control the gate potential of the driver TFT 36 to which the control capacitor 38 is connected to fix the gate potential to a very high EL power supply Pvdd, or to not fix the gate potential, or, in the example circuit of
By setting the amplitude of the control pulse signal to be applied to the control line CPL to a sufficiently large amplitude, it is possible to sufficiently switch off or on the driver TFT 36. In particular, by setting the voltage of the L level of the control pulse signal which defines the display period to a voltage which is sufficiently lower than the voltage of the EL power supply, it is possible to switch the driver TFT 36 fully on in a voltage region in which the on resistance is sufficiently small (saturation region). Therefore, it is possible to control the amount of light emission by the organic EL element 40 without being affected by a variation in operation threshold values among the driver TFTs 36 in the pixels. As described before, the control line CPL may be formed to be common to all pixels, and thus, a control pulse signal for defining the write period and display (light emission) period during each subfield period may be output to all pixels.
Although the amplitude of the control pulse signal maybe larger than that of the data signal, it is only required for the control pulse signal that the level of the control pulse signal is inverted during switching between the write period and the display period in each subfield and, therefore, the inversion period is relatively long. Therefore, the load of the control pulse signal on the output circuit is relatively small, and a circuit with a simple structure may be used.
In the present embodiment, a p-channel TFT is employed as the driver TFT 36, but an n-channel TFT may alternatively be employed. In this case, the power supply connected to the source of the control TFT 32 is changed to a constant power supply voltage with a low voltage (for example, the cathode power supply) and the polarity of the control pulse signal is inverted so that the pulse signal which becomes H level during the display period is used. Alternatively, it is also possible to employ an n-channel TFT as the control transistor 32. In this configuration, the polarity of the data signal may be inverted for “1” and “0”. In the present embodiment, an n-channel TFT is utilized as the selection TFT 30, but a p-channel TFT may alternatively be employed. In this case, the polarity of the selection signal is inverted.
In the present embodiment, the present invention has been described referring to an example organic EL display device which uses an organic EL element 40 as a display element in each pixel. The present invention is not limited to this structure, however, and similar advantages can be obtained by employing a similar structure in each pixel in an active matrix display device which uses a light emitting element other than the organic EL element 40, such as an organic EL element and other display elements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-177267 | Jun 2003 | JP | national |
| 2004-170835 | Jun 2004 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6730966 | Koyama | May 2004 | B2 |
| 6777710 | Koyama | Aug 2004 | B1 |
| 6858991 | Miyazawa | Feb 2005 | B2 |
| 6861810 | Rutherford | Mar 2005 | B2 |
| 7109952 | Kwon | Sep 2006 | B2 |
| Number | Date | Country |
|---|---|---|
| 2002-149112 | May 2002 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20050024351 A1 | Feb 2005 | US |
