Patent Application
20160042688
1. Field of the Invention
The present invention relates to a light-emitting device and an image forming apparatus.
2. Description of the Related Art
In recent years, image forming apparatuses have been developed which use, as exposure means, a line head with many organic electroluminescence elements (hereinafter, referred to as “organic EL elements”) disposed in one line. This line head includes the plurality of organic EL elements and a plurality of pixel circuits including transistors for driving these organic EL elements. The luminance of each organic EL element is controlled by controlling the amount of current to be flowed into the organic EL element by means of the corresponding pixel circuit.
Japanese Patent Application Laid-Open No. 2009-006718 discloses a line head using organic EL elements disposed in a line. The line head described in Japanese Patent Application Laid-Open No. 2009-006718 is such that a plurality of pixels disposed in a line are divided into a plurality of pixel blocks, and data signals are supplied in a time-division manner to pixel circuits connected to the pixels while the pixel blocks are sequentially selected by means of control signals from a shift register.
In Japanese Patent Application Laid-Open No. 2009-006718, the control signals for sequentially selecting the pixel blocks are each inputted as a common signal to all the pixel circuits in the pixel block. When the control signal is inputted into the pixel circuit at an end of the pixel block, the control signal travels through a control signal line and is inputted into the adjacent pixel circuit. The control signal is then inputted sequentially into the following adjacent pixel circuits, and the control signal is eventually supplied to all the pixel circuits in the pixel block.
Here, as the control signal travels through the control signal line, the waveform of the control signal is gradually deformed due to the parasitic impedance of the interconnection line such that the waveform is different between the first pixel circuit the control signal is inputted and the last pixel circuit the control signal is inputted. Such a difference influences the writing of a data signal to each pixel circuit and makes it difficult to accurately control the amount of current to be flowed into each organic EL element.
The influence of the deformation of the waveform of the control signal as described above occurs not only on light-emitting devices using organic EL elements but similarly on light-emitting devices using other light-emitting elements such for example as inorganic EL elements, e.g., light-emitting diodes (LEDs).
An object of the present invention is to provide a light-emitting device accurately controlling the amount of current to be flowed to each light-emitting element by reducing the deformation of the waveforms of control signals, and also to provide an image forming apparatus with such a light-emitting device capable of fine image formation.
According to one aspect of the present invention, there is provided a light-emitting device including a pixel block including a plurality of light-emitting elements disposed on a long substrate and aligned in a longitudinal direction of the substrate, a plurality of pixel circuits connected to the plurality of light-emitting elements, respectively, a control signal line connected to the plurality of pixel circuits, and a pixel block select circuit connected to the control signal line and configured to output a control signal to the plurality of pixel circuits, in which the plurality of pixel circuits are divided into a plurality of groups, the control signal line includes a first interconnection portion and a second interconnection portion, the first interconnection portion is disposed along the longitudinal direction of the substrate and connected to the plurality of pixel circuits, the second interconnection portion is disposed in a region between the plurality of groups and connected to the pixel block select circuit, and the first interconnection portion and the second interconnection portion are connected to each other in the region between the plurality of groups.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
Preferred embodiments of the present invention will now be described in detail in accordance with the accompanying drawings.
A light-emitting device according to a first embodiment of the present invention will be described with reference to
First, the configuration of the light-emitting device according to the present embodiment will be described with reference to
The light-emitting device according to the present embodiment is applicable as, but not particularly limited to, for example, an exposure head in an image forming apparatus such as a laser printer, etc. for irradiating a photosensitive drum with light to form a latent image thereon.
As illustrated in
The plurality of pixels 1 are disposed on a long substrate not illustrated and aligned side by side in the longitudinal direction of the substrate.
The plurality of pixel circuits 2 are disposed on the substrate and aligned side by side adjacently to and in parallel with the line of pixels 1. The pixel circuits 2 are configured to control drive current for the light-emitting elements of the pixels 1, and one pixel circuit 2 is connected to one pixel 1.
The plurality of pixels 1 and the plurality of pixel circuits 2 are divided into n pixel blocks PB (pixel blocks PB(1), PB(2), . . . , PB(n-1), and PB(n)) each including m pixels 1 and m pixel circuits 2. In
Data signal lines through which to supply data signals inputted from an external circuit not illustrated are connected to the pixel circuits 2. The number of data signal lines corresponds to the number of pixels (m) in one pixel block. In the example of
Each pixel block PB further includes a pixel block select circuit 3. The pixel block select circuit 3 is connected to the pixel circuits 2 in the corresponding pixel block PB through control signal lines P1, P2, and P3. Thus, control signals outputted from the pixel block select circuit 3 can be inputted into the pixel circuits 2 in the corresponding pixel block PB through the control signal lines P1, P2, and P3. The control signal lines P1, P2, and P3 are disposed along the direction in which the pixel circuits 2 are aligned, and pass through the region where the pixel circuits 2 are disposed.
More specifically, control signal lines P1(1), P2(1), and P3(1) are each connected as a common line to each pixel circuit 2 in the pixel block PB(1). Also, control signal lines P1(2), P2(2), and P3(2) are each connected as a common line to each pixel circuit 2 in the pixel block PB(2). Similarly, control signal lines P1(n-1), P2(n-1), and P3(n-1) are each connected as a common line to each pixel circuit 2 in the pixel block PB(n-1). Also, control signal lines P1(n), P2(n), and P3(n) are each connected as a common line to each pixel circuit 2 in the pixel block PB(n).
Note that while the present embodiment has illustrated the example where each pixel circuit 2 is driven with three control signals (control signals inputted through the control signal lines P1, P2, and P3), the number control signals may be any number. The number of control signals can be optionally changed in accordance with the number of pixels 1 included in each pixel block PB, for example.
A clock signal line CLK and control signal lines S1, S2, and S3 are connected to each pixel block select circuit 3. Thus, a clock signal CLK and control signals S1, S2, and S3 can be inputted into the pixel block select circuit 3 from an external control circuit not illustrated.
A start pulse signal line SP is connected to the pixel block select circuit 3 of the pixel block PB(1) so that a start pulse signal can be inputted thereinto from the external control circuit not illustrated. The pixel block select circuits 3 of the adjacent pixel blocks PB are connected to each other. Each pixel block select circuit 3 includes a shift register (not illustrated) formed therein. Thus, the start pulse signal inputted into the pixel block select circuit 3 of the pixel block PB(1) is transferred sequentially to the next pixel block select circuit 3 in accordance with the clock signal CLK. In the pixel block select circuit 3, logic gates therein perform logic operations with transfer pulses and control signals to generate P1, P2, and P3 control signals. The P1, P2, and P3 control signals are control signals configured to select the pixel block PB in the order starting from the pixel block PB(1) to the pixel block PB(n).
A power supply line VDD and a power supply line VSS are connected to all the pixel block select circuits 3 so that a power supply voltage can be supplied to the pixel block select circuits 3. Further, a power supply line VOLED is connected to all the pixel circuits 2 so that a power supply voltage can be supplied to the pixel circuits 2. Furthermore, a power supply line VOCOM is connected to all the pixels 1 so that a power supply voltage can be supplied to the pixels 1.
The data signal lines Vdata0 to Vdata7, the clock signal line CLK, the control signal lines S1, S2, and S3, the power supply line VDD, the power supply line VSS, the power supply line VOLED, and the power supply line VOCOM are connected to terminal portions not illustrated provided on the substrate. Note that if there are any other necessary power supply lines, signal lines, and the like, these and their terminal portions may be disposed as appropriate.
The pixel circuits 2 in each pixel block PB are divided into two groups, and a space 4 is provided between these two groups. In the example of
The control signal lines P1, P2, and P3 and the pixel block select circuit 3 in each pixel block PB are connected to each other through lead portions led out from the control signal lines P1, P2, and P3 in a direction which crosses the control signal lines P1, P2, and P3. These lead portions and the control signal lines P1, P2, and P3 are connected to each other in the space 4. To put it differently, each of the control signal lines P1, P2, and P3 includes a first interconnection portion disposed to extend through the region of the pixel circuits 2 in the direction in which the pixel circuits 2 are aligned, and a second interconnection portion disposed to extend from the pixel block select circuit 3 to the inside of the region between the groups (space 4). Moreover, the first interconnection portion and the second interconnection portion are connected to each other at the region between the groups (space 4).
Connecting the control signal lines P1, P2, and P3 and the pixel block select circuit 3 in this manner can shorten the longest interconnection length between the pixel block select circuit 3 and the pixel circuit 2 as compared to a case where signals are caused to travel sequentially from the pixel circuit 2 at an end of the pixel block PB. For example, in the example of
Next, an example of the configuration of each pixel circuit 2 in the light-emitting device according to the present embodiment will be described with reference to
As illustrated in
One of the source and drain of the switch transistor M7 is connected to the common power supply line VOLED. The other of the source and drain of the switch transistor M7 is connected to the source of the driving transistor M1, one of the source and drain of the switch transistor M8, and one of the source and drain of the switch transistor M5. The other of the source and drain of the switch transistor M5 is connected to the data signal line Vdata.
The other of the source and drain of the switch transistor M8 is connected to one of the terminals of the holding capacitor C1 and one of the source and drain of the switch transistor M2. The other of the source and drain of the switch transistor M2 is connected to a reference voltage line Vref.
The gate of the driving transistor M1 is connected to the other terminal of the holding capacitor C1, one of the source and drain of the switch transistor M3, and one of the source and drain of the switch transistor M4. The other of the source and drain of the switch transistor M3 is connected to a pre-charge voltage line Vini.
The drain of the driving transistor M1 is connected to the other of the source and drain of the switch transistor M4 and one of the source and drain of the switch transistor M6. The other of the source and drain of the switch transistor M6 is connected to the anode of an organic EL element EL. The cathode of the organic EL element EL is connected to the common power supply line VOCOM. Here, the organic EL element EL is a light-emitting element which constitutes the pixel 1.
Note that the reference voltage line Vref and the pre-charge voltage line Vini are not illustrated in
Next, the operation of the light-emitting device according to the present embodiment will be described with reference to the timing chart in
First, the description will be given for the pixel block PB(1). Note that while the following description will explain data writing to one pixel 1 in the pixel block PB(1), the data writing is performed on the plurality of pixels 1 in the pixel block PB(1) simultaneously through similar steps.
Immediately before a time to, a control signal P1(1), a control signal P2(1), and a control signal P3(1) are at Low (L) levels.
At the time t0, the control signal P3(1) shifts from the L level to an High (H) level. As a result, the switch transistors M6 and M7 switch from ON states to OFF states, so that the supply of current to the organic EL element EL stops. Also, the switch transistors M2 and M5 switch from OFF states to ON states, so that the source of the driving transistor M1 is connected to the data signal line Vdata and the one terminal of the holding capacitor C1 is connected to the reference voltage line Vref.
Also, at the time t0 again, the control signal P1(1) shifts from the L level to an H level. As a result, the switch transistor M3 switches from an OFF state to an ON state, so that the gate (illustrated as “M1−Vg(1)” in
Vgs=Vini−Vdata
and is set to a gate-source voltage that can drive a high current (pre-charge period).
Then, at a time t1, the control signal P1(1) shifts from the H level to the L level and the control signal P2(1) shifts from the L level to an H level. As a result, the switch transistor M3 switches from the ON state to the OFF state and the switch transistor M4 switches from an OFF state to an ON state.
Consequently, a current is supplied from the driving transistor M1 in accordance with the driving ability of the driving transistor M1, and gate voltage Vg of the driving transistor M1 rises until the gate-source voltage of the driving transistor M1 reaches a threshold voltage (Vth). Note that the gate voltage Vg of the driving transistor M1 in this step is
Vg=Vdata−Vth.
Then, at a time t2, the control signal P2(1) shifts from the H level to the L level. As a result, the switch transistor M4 switches from the ON state to the OFF state, so that voltage dV1 between both terminals of the holding capacitor C1 is
dV1=(Vdata−Vth)−Vref.
Specifically, the threshold voltage (Vth) of the driving transistor M1 and the data voltage are written at the same time to one holding capacitor C1 (auto-zero data writing period).
Also, at the time t2 again, the control signal P3(1) shifts from the H level to the L level. As a result, the switch transistors M2 and M5 switch from the ON states to the OFF states, and the switch transistors M6 and M7 switch from the OFF states and stay in the ON states until immediately before a time t7 at which the pixel circuit 2 is selected next time.
Consequently, a current path is formed which extends from the common power supply line VOLED through the switch transistor M7, the driving transistor M1, the switch transistor M6, and the organic EL element EL to the common power supply line VOCOM, and the supply of current to the organic EL element EL starts.
Here, the switch transistor M7 has an ON resistance. The common power supply voltage VOLED after a voltage drop of a voltage 5V, which is caused at the switch transistor M7 by this ON resistance in proportion to the amount of current therethrough, is source voltage Vs of the driving transistor M1. Thus, the source voltage Vs of the driving transistor M1 is
Vs=VOLED−δV.
Meanwhile, since no current flows through the switch transistor M8, which is connected to the driving transistor M1, no voltage drop occurs due to the switch transistor M8. Thus, voltage Vc at the one terminal of the holding capacitor C1 is equal to the source voltage Vs of the driving transistor M1 (Vc=Vs).
Hence, the gate voltage Vg of the driving transistor M1 is
Vg=Vc−dV1=Vs−dV1.
Then, the gate-source voltage Vgs of the driving transistor M1 is
Vgs=Vg−Vs=dV1=(Vdata−Vth)−Vref (1)
Thus, a current proportional to the gate-source voltage Vgs of the driving transistor M1 is supplied to the organic EL element EL from the driving transistor M1, and the organic EL element EL emits an amount of light in accordance with the value of the supplied current (light emission period).
Next, the description will be given for the pixel block PB(2). Note that the following description will be given for one pixel in the pixel block PB(2), but the plurality of pixels in the pixel block PB(2) are driven simultaneously through similar steps.
Immediately before the time t2, a control signal P1(2), a control signal P2(2), and a control signal P3(2) are at L levels.
At the time t2, the control signal P3(2) shifts from the L level to an H level. As a result, the switch transistors M6 and M7 switch from ON states to OFF states, so that the supply of current to the organic EL element EL stops. Also, the switch transistors M2 and M5 switch from OFF states to ON states, so that the source of the driving transistor M1 is connected to the data signal line Vdata and the one terminal of the holding capacitor C1 is connected to the reference voltage line Vref.
Also, at the time t2 again, the control signal P1(2) shifts from the L level to an H level. As a result, the switch transistor M3 switches from an OFF state to an ON state, so that the gate of the driving transistor M1 is connected to the pre-charge voltage line Vini. Thus, the gate-source voltage Vgs of the driving transistor M1 is
Vgs=Vini−Vdata
and is set to a gate-source voltage that can drive a high current (pre-charge period).
After this, similarly to the pixel block PB(1), the operation goes sequentially through an auto-zero data writing period and a light emission period.
The pre-charge period, the auto-zero data writing period, and the light emission period are repeated as described above for each pixel block PB.
As mentioned in the above description of the operation, the control signal P1 is a signal for controlling the pre-charge period, the control signal P2 is a signal for controlling the auto-zero data writing period (a signal for controlling the duration of data writing), and the control signal P3 is a signal for controlling the light emission period. More specifically, the control signal P2 is for controlling the duration of correction of the threshold voltage of the driving transistor M1 and the control signal P3 is for controlling the duration of light emission, and they are particularly important for accurately controlling the amount of current to be flowed into the organic EL element EL.
According to the light-emitting device 10 of the present embodiment, as described above, the longest interconnection length between the pixel block select circuit 3 and the pixel circuit 2 can be shortened as compared to the case where signals are caused to travel sequentially from the pixel circuit 2 at an end of the pixel block PB. In this way, it is possible to reduce the deformation of the waveforms of the control signals due to the parasitic impedances of the control signal lines P1, P2, and P3.
Thus, the light-emitting device 10 of the present embodiment, which is capable of effectively reducing the deformation of the waveforms of the control signal P1, control signal P2, and control signal P3, is significantly advantageous in accurately controlling the amount of current to be flowed into the organic EL element EL.
Thus, according to the present embodiment, it is possible to reduce the deformation of the waveforms of the signals due to the parasitic impedances of the control signal lines, and thus to accurately control the amount of current to be flowed to the organic EL element of each pixel. Hence, a light-emitting device capable of accurately controlling the amount of light emission can be realized.
A light-emitting device according to a second embodiment of the present invention will be described with reference to
In the present embodiment, only the difference from the light-emitting device according to the first embodiment, which is illustrated in
In the light-emitting device according to the first embodiment, the plurality of pixel circuits 2 included in each pixel block PB are divided into two groups each including a half of the pixel circuits, and the space 4 is left between these groups for a contact portion of the control signal lines P1, P2, and P3. However, the arrangement of the contact portion (space 4) of the control signal lines P1, P2, and P3 is not necessarily limited to such an arrangement. In other words, when the plurality of pixel circuits 2 are divided into two groups, they do not necessarily have to be divided into groups each including a half of the pixel circuits 2.
In the light-emitting device illustrated in
As described above, according to the present embodiment, it is possible to reduce the deformation of the waveforms of the signals due to the parasitic impedances of the control signal lines, and thus to accurately control the amount of current to be flowed to the organic EL element of each pixel. Hence, a light-emitting device capable of accurately controlling the amount of light emission can be realized.
A light-emitting device according to a third embodiment of the present invention will be described with reference to
In the present embodiment, only the difference from the light-emitting devices according to the first and second embodiments, which are illustrated in
In the first and second embodiments, the plurality of pixel circuits 2 included in each pixel block PB are divided into two groups. However, the pixel circuits 2 do not necessarily have to be divided into two groups and may be divided into three or more groups.
In the light-emitting device illustrated in
In the case where the plurality of pixel circuits 2 included in each pixel block PB are divided into three or more groups and two or more contact portions are disposed, the control signal lines P1, P2, and P3 do not necessarily have to be common to all the pixel circuits 2. For example, in
Dividing the plurality of pixel circuits 2 included in each pixel block PB into three or more groups can further shorten the longest interconnection length between the pixel block select circuit 3 and the pixel circuit 2 as compared to the case where the pixel circuits 2 are divided into two groups. Hence, the light-emitting device according to the present embodiment can further reduce the deformation of the waveforms of the control signals due to the parasitic impedances of the control signal lines P1, P2, and P3.
Thus, according to the present embodiment, it is possible to reduce the deformation of the waveforms of the signals due to the parasitic impedances of the control signal lines, and thus to accurately control the amount of current to be flowed to the organic EL element of each pixel. Hence, a light-emitting device capable of accurately controlling the amount of light emission can be realized.
An image forming apparatus according to a fourth embodiment of the present invention will be described with reference to
In the present embodiment, an image forming apparatus which uses the light-emitting device according to any of the first to third embodiments as an exposure head will be described.
First, the configuration of the image forming apparatus according to the present embodiment will be described with reference to
As illustrated in
Next, the operation of the image forming apparatus according to the present embodiment will be described.
In the recording unit 104, the surface of the cylindrical photosensitive drum 105, which is a photosensitive member, is electrically charged uniformly with the charger 106, which is a charging unit.
Then, the exposure head 107, which is an exposure unit, is caused to emit light in accordance with data to expose the photosensitive drum 105 to the light, so that an electrostatic latent image corresponding to the data by the exposure is formed on the photosensitive drum 105. The formation of the electrostatic latent image can be controlled through the amount of light emission (illuminance and duration) by the exposure head 107.
Next, in the recording unit 104, the developing device 108, which is a developing unit, applies a toner, which is a developing agent, onto the photosensitive drum 105 so that the toner can adhere to the electrostatic latent image, and the transfer device 109 transfers the toner, which has adhered to the electrostatic latent image, onto a paper sheet 102.
The fixing device 110 fixes the toner to the paper sheet 102, onto which image data has been transferred through the recording unit 104, and the paper sheet 102 is then discharged. Note that the timing at which the paper sheet 102 is conveyed to the record system 104 by the conveyance rollers 103 can be set as appropriate.
The present embodiment has been described by taking, as an example, a monochrome image forming apparatus with one recording unit 104. However, the image forming apparatus 100 is not limited to such an apparatus and may be a color image forming apparatus including a plurality of the recording units 104.
As described above, according to the present embodiment, the image forming apparatus is formed using the light-emitting device according to any of the first to third embodiments. Hence, an image forming apparatus capable of fine image formation can be realized.
[Modifications]
The present invention is not limited to the above embodiments, and various modifications are possible.
For example, the pixel circuit illustrated in
Moreover, the arrangement of each circuit element in relation to the other circuit elements in
Also, while the contact portions of the control signal line P1, control signal line P2, and control signal line P3 are disposed in the same space 4 in the above first to third embodiments, they may be disposed in different spaces 4. For example, in
Also, while the plurality of pixels 1 and the plurality of pixel circuits 2 are divided into the plurality of pixel blocks PB in the above first to third embodiments, they do not necessarily have to be divided in a plurality of pixel blocks.
Also, the image forming apparatus in the above fourth embodiment is shown as one exemplary apparatus to which the light-emitting devices according the first to third embodiments are applicable, and apparatuses to which the light-emitting devices according the first to third embodiments are applicable are not limited to such an apparatus. The light-emitting devices according to the first to third embodiments are applicable to various apparatuses which use a light source with light-emitting elements aligned side by side.
The above embodiments are mere illustration of some possible modes of application of the present invention and are not intended to prevent the present invention from being corrected and/or modified as appropriate without departing from the spirit of the present invention.
According to the present invention, it is possible to reduce the deformation of the waveforms of the signals due to the parasitic impedances of the control signal lines, and thus to accurately control the amount of current to be flowed to the organic EL element of each pixel. Hence, a light-emitting device capable of accurately controlling the amount of light emission can be realized. Moreover, by using such a light-emitting device, an image forming apparatus capable of fine image formation can be realized.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2014-163369, filed on Aug. 11, 2014 which is hereby incorporated by reference herein in its entirety.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-163369 | Aug 2014 | JP | national |
