Patent Grant
11395384
The present invention relates to a light-emitting device driving apparatus, a light-emitting device driving system and a light-emitting system.
In a liquid-crystal display (LCD) panel, a light-emitting portion consisting of a light-emitting diode (LED) is often used as a backlight, and an LED driver is used as an apparatus for driving the light-emitting portion. In the recent years, in response to high dynamic range (HDR) imaging, an LED driver capable of local dimming is required.
[Patent document 1] Japan Patent Publication No. JP2013-222515
Due to an error in the forward voltage of each LED forming a light-emitting portion, various kinds of errors are present in the voltage drop in the light-emitting portion when a current flows. Considering such error, the output voltage (light emission driving voltage) of the power supply device 911 is determined or controlled. A required voltage is not applied to each light-emitting portion if the output voltage of the power supply device 911 is too low, and a large amount of heat is produced if the output voltage of the power supply device 911 is too high. Preferably, heat generation is suppressed as much as possible.
In aim of optimization of the output voltage of the power supply device 911, an approach of feeding back voltage information dependent on the voltage drop in each light-emitting portion to the power supply device 911 has also been studied. However, at this point, it is necessary to avoid situations where the output voltage of the power supply device fluctuates frequently (with associated details to be described shortly).
Further, an LED forming the light-emitting device of the light-emitting portion is given as an example, an LED driver serving as a light-emitting device driving apparatus is given as an example, and related situations of the light-emitting device driving apparatus are described. However, the same issue described above can also exist in a light-emitting device driving apparatus processing a light-emitting device other than the LED.
It is an object of the present invention to provide a light-emitting device driving apparatus, a light-emitting device driving system and a light-emitting system beneficial for the optimization of a light emission driving voltage.
A light-emitting device driving apparatus of the present invention is configured as below (first configuration), that is, the light-emitting device driving apparatus includes driver blocks of multiple channels, each driving block having a light-emitting portion connecting terminal to be connected to a light-emitting portion including one or more than one light-emitting device, the light-emitting portion caused to emit light by a current flowing through the light-emitting portion connecting terminal to the light-emitting portion; the light-emitting device driving apparatus further including: a lowest voltage detection circuit, detecting and outputting a lowest voltage among voltages of the light-emitting portion connecting terminals of each channel; a sample hold circuit, comparing an output voltage of the lowest voltage detection circuit with a hold voltage thereof, and updating the hold voltage to the output voltage if the output voltage is lower than the hold voltage; and a feedback control circuit, outputting a feedback signal according to the hold voltage and a predetermined reference voltage to a power supply device providing a light emission driving voltage to the light-emitting portions of the multiple channels, thereby controlling the light emission driving voltage.
The light-emitting device driving apparatus in the first configuration can also be configured as below (second configuration): each driver block further includes a constant current circuit providing a constant current flowing through the light-emitting portion connecting terminal to the light-emitting portion, and a switching element connected in series on a path along which the constant current flows, wherein the light-emitting portion is pulsed to emit light by controlling turning on and off of the switching element.
The light-emitting device driving apparatus in the first configuration or the second configuration can also be configured as below (third configuration): the feedback control circuit generates the feedback signal in a manner that, the light emission driving voltage decreases if the hold voltage is higher than the reference voltage, and the light emission driving voltage increases if the hold voltage is lower than the reference voltage.
The light-emitting device driving apparatus in any of the first to the third configurations can also be configured as below (fourth configuration): the sample hold circuit is configured to be capable of performing a reset process for setting the hold voltage to a predetermined initial voltage.
The light-emitting device driving apparatus in the fourth configuration can also be configured as below (fifth configuration): the sample hold circuit starts periodic execution of the reset process if a predetermined condition is true, and ends the periodic execution of the reset process according to a relationship between the hold voltage updated to the output voltage of the lowest voltage detection circuit and the reference voltage.
The light-emitting device driving apparatus in any of the first to fifth configurations can also be configured as below (sixth configuration): the multiple light-emitting portions of each channels are connected in parallel to the light-emitting portion connecting terminal, and the light emission driving voltage is selectively applied in a time division manner to the multiple light-emitting portions.
The light-emitting device driving apparatus in any of the first to sixth configurations can also be configured as below (seventh configuration): the light-emitting device driving apparatus includes a housing having a first side and a third side opposite to each other and a second side and a fourth side opposite to each other, the light-emitting portion connecting terminals of the multiple channels are arranged throughout the first side, the second side and the third side, and a feedback signal output terminal for outputting the feedback signal is arranged on the fourth side.
The light-emitting device driving apparatus in the seventh configuration can also be configured as below (eighth configuration): the light-emitting device driving apparatus is configured to be capable of communicating with an external apparatus, and a communication terminal for communicating with the external apparatus is arranged on the third side.
The light-emitting device driving apparatus in the eighth configuration can also be configured as below (ninth configuration): on the third side, the communication terminal is arranged closer to the fourth side than the light-emitting portion connecting terminal.
A light-emitting device driving system of the present invention is configured as below (tenth configuration), that is, the light-emitting device driving system includes: the light-emitting device driver apparatus of any of the first to ninth configurations; and a power supply device, generating and outputting the light emission driving voltage according to the feedback signal from the light-emitting device driving apparatus.
A light-emitting system of the present invention is configured as below (eleventh configuration), that is, the light-emitting system includes the light-emitting device driver apparatus of any of the first to ninth configurations; a power supply device, generating and outputting the light emission driving voltage according to the feedback signal from the light-emitting device driving apparatus; and the light-emitting portions of the multiple channels.
Alternatively, a light-emitting system of the present invention is configured as below (twelfth configuration), that is, the light-emitting system includes: the light-emitting device driving apparatus in the sixth configuration; a power supply device, generating the light emission driving voltage according to the feedback signal from the light-emitting device driving apparatus, and outputting the light emission driving voltage from an output terminal thereof; and light-emitting portions of the multiple channels. Wherein, the multiple channels include 1st to Nth channels (where N is an integer equal or more than 2), 1st to Mth light-emitting portions (where M is an integer equal or more than 2) are connected in parallel to the light-emitting portion connecting terminal of each channel, a 1st switching element connected in series between the output terminal of the power supply device and the 1st light-emitting portion of each channel, a 2nd switching element connected in series between the output terminal of the power supply device and the 2nd light-emitting portion of each channel, . . . and an Mth switching element connected in series between the output terminal of the power supply device and the Mth light-emitting portion of each channel; the light-emitting device driving apparatus further includes a switch control circuit, the switch control circuit selectively applying the light emission driving voltage in a time division manner to the 1st to Mth light-emitting portions of each channel by controlling turning on and off the 1st to Mth switching elements.
A light-emitting device driving apparatus, a light-emitting driving system and a light-emitting system beneficial for optimization of a light emission driving voltage are provided according to the present invention.
Details of the present invention are given in preferred embodiments with the accompanying drawings below. In the reference drawings, the same part is represented by the same denotation, and repeated description related to the same part is in principle omitted. Further, for brevity of the description, information, signals, physical quantities or names of components corresponding to signs or symbols representing information, signals, physical quantities or components of denotation references can be omitted or abbreviated. For example, as “40” is used to refer to a lowest voltage detection circuit (referring to
Some terms used in the description of the embodiments of the present invention are first explained. A ground wire refers to a conductive portion having a reference potential of 0 V or the reference potential itself. In the embodiments of the present invention, a voltage indicated without a specific reference is a potential observed from the ground wire. A level refers to the level of a potential, and for any signal or voltage, a high level has a level higher than that of a low level. Any switching element can be formed by one or more than one field-effect transistor (FET). When a switching element is in a turned-on state, two terminals of the switching element are connected. On the other, when a switching element is in a turned-off state, two terminals of the switching element are disconnected. The turned-on and turned-off state of any switching element can also be merely expressed as on and off.
A first embodiment of the present invention is described below
The LCD panel 14 includes multiple pixels arranged in a matrix. Multiple data lines and multiple scan lines are provided in the LCD panel 14, and the pixels are arranged at intersections of the data lines and the scan lines.
The liquid-crystal driver 15 receives image data representing an image (in other words, a picture) to be displayed on the LCD panel 14, and applies a voltage to the LCD panel 14 according to the image data so as to form on the LCD panel 14 an image based on the image data. The liquid-crystal driver 15 includes data drivers applying a driving voltage corresponding to the image data to the multiple data lines, and gate drivers sequentially selecting the multiple scan lines. The liquid-crystal driver 15 applies the voltage to the LCD panel 14 according to the image data at time points of a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync generated according to an oscillation circuit (not shown) in the display apparatus 1.
The DC/DC converter 11 performs power conversion (DC-DC conversion) of a DC input current Vi to generate a DC output current Vo. The input voltage Vi is a positive DC voltage (e.g., 12 V), and the output voltage Vo is also a positive DC voltage. However, the value of the output voltage Vo can be variably controlled (e.g., variably controlled within a range between 20 V and 40 V). The input voltage Vi can be provided from outside the display apparatus 1, or can be generated by other power supply circuits in the display apparatus 1. A power supply circuit (not shown) including a DC/DC converter 11 is provided in the display apparatus 1, and the constituting components provided in the display apparatus 1 are driven according to a voltage generated by the power supply circuit.
The backlight portion 12 functions as a light source for the LCD panel 14. The backlight portion 12 includes multiple light-emitting portions, and the LCD panel 14 visually displays the image by using light emitted from the light-emitting portions. Each light-emitting portion includes one or more than one LED, and emits light based on the output voltage Vo of the DC/DC converter 11.
The LED driver 10 drives the light-emitting portions forming the backlight portion 12. The CPU 13 is an example of an external apparatus with respect to the LED driver 10. The CPU 13 and the LED driver 10 can be connected to each other in a form capable of bidirectional communication. Under the control of the CPU 13, the LED driver 10 adjusts the light emission brightness of the light-emitting portions forming the backlight portion 12.
The DC/DC converter 11 generates the output voltage Vo by, for example, pulse-width modulating the input voltage Vi. The output voltage Vo has a positive DC voltage value. The DC/DC converter 11 has an output terminal 11a and a feedback input terminal 11b, and the output voltage Vo is outputted from the output terminal 11a. The output voltage Vo is divided by a series circuit of a resistor R1 and a resistor R2. More specifically, the output terminal 11a is connected to one terminal of the resistor R1, and the other terminal of the resistor R1 is connected to the ground wire via the resistor R2. Further, an output capacitor Co is disposed between the output terminal 11a and the ground wire. The voltage generated at a connecting node ND between the resistors R1 and R2 is referred to as a feedback voltage Vfb. The feedback voltage Vfb is dependent on the value of the output voltage Vo and a resistance ratio between the resistors R1 and R2. The node ND is connected to the feedback input terminal 11b. The DC/DC converter 11 controls the output voltage Vo by way of having the feedback voltage Vfb applied to the feedback input terminal 11b coincide with a predetermined DC/DC reference voltage. The DC/DC converter 11 adjusts the value of the output voltage Vo by increasing the output voltage Vo when the feedback voltage Vfb is lower than the DC/DC reference voltage, and adjust the value of the output voltage Vo by reducing the output voltage Vo when the feedback voltage Vfb is higher than the DC/DC reference voltage. As such, the DC/DC converter 11, the resistors R1 and R2 and the output capacitor Co form a power supply device providing a light emission driving voltage (the voltage Vo) to the light-emitting portions LL.
The power supply device including the DC/DC converter 11 and the LED driver 10A form a light-emitting device driving system, and the backlight portion 12A is added to the light-emitting driving system to form a light-emitting system.
The backlight portion 12A includes light-emitting portions LL of N channels, wherein the N channels are referred to as 1st to Nth channels. In the backlight portion 12A, the output voltage Vo of the DC/DC converter 11 is applied to the high-potential terminal of each light-emitting portion LL, as the light emission driving voltage. N is any integer equal or more than 2, for example, N is equal to 24. The light-emitting portions LL of the N channels have the same configuration. In the description below, a current flowing to the light-emitting portion LL is referred to as an LED current. In a situation where it is necessary to distinguish the light-emitting portions LL of the N channels from one another, the light-emitting portions LL of the N channels are referred to as light-emitting portions LL[1] to LL[N]. The light-emitting portion LL[i] is the light-emitting portion LL of the ith channel (where i is an integer).
The LED driver 10A includes driver blocks 20 of N channels, and further includes a light emission control circuit 30, a lowest voltage detection circuit 40, a sample hold circuit 50 and a feedback control circuit 60. Multiple external terminals exposing from a housing of the LED driver 10A are provided in the LED driver 10A. In
The driver blocks 20 of the N channels have the same configuration. Each driver block 20 includes the light-emitting portion connecting terminal CH, a constant current circuit 21 and a switching element 22. In each driver block 20, the switching element 22 is connected in series between the light-emitting connecting terminal CH and the constant current circuit 21. When the switching element 22 is in a turned-on state, the constant current circuit 21 operates such that a predetermined constant current flows through the light-emitting portion connecting terminal CH to the ground wire. The position for placing the switching element 22 can be any as desired (thus, for example, the switching element 22 can also be placed between the constant current circuit 21 and the ground wire), given that the switching element 22 is placed on the path along which the constant current of the constant current circuit 21 flows.
In a situation where it is necessary to distinguish the driver blocks 20 of the N channels from one another, the driver blocks 20 of the N channels are referred to as driver blocks 20[1] to 20[N]. The driver block 20[i] is the driver block 20 of the ith channel (where i is an integer). The light-emitting portion connecting terminal CH, the constant current circuit 21 and the switching element 22 in the driver block 20[i] are sometimes referenced as denotations “CH[i]”, “21[i]” and “22[i]”. The light-emitting portion connecting terminal CH[i], the constant current circuit 21[i] and the switching element 22[i] are respectively the light-emitting portion connecting terminal CH, the constant current circuit 21 and the switching element 22 of the ith channel (where i is an integer).
Each light-emitting portion connecting terminal CH is connected to the low-potential terminal of the corresponding light-emitting portion LL. Because the driver block 20 (i.e., 20[i]) of the ith channel corresponds to the light-emitting portion LL (i.e., LL[i]) of the ith channel, the light-emitting portion connecting terminal CH[i] is connected to the low-potential terminal of the light-emitting portion LL[i]. Thus, when the switching element 22[i] in in a turned-on state, the constant current of the constant current circuit 21[i] serves as an LED current that flows from the output terminal 11a and passes through the light-emitting portion LL[i], the light-emitting portion connecting terminal CH[i] and the switching element 22[i], and the light-emitting LL[i] emits light as a result. When the switching element 22[i] is in a turned-off state, the light-emitting portion LL[i] and the constant current circuit 21[i] are disconnected, and thus the current does not flow to the light-emitting portion LL[i] and the light-emitting portion LL[i] does not emit light.
The light emission control circuit 30 generates a PWM signal at each channel according to light emission setting information, and provides the PWM signal to the switching element 22 with respect to each channel. Accordingly, the duty cycle of the switching element 22 is controlled with respect to each channel. The light emission setting information is determined according to a signal from the CPU 13 (in other words, provided from the CPU 13). With respect to any ith channel, the switching element 22[i] is alternatingly turned on and turned off in predetermined unit intervals (referring to
In each driver block 20, the corresponding light-emitting portion LL is pulsed to emit light by turning on and turning off the switching element 22[i] according to the PWM signal. As the duty cycle of the switching element 22[i] increases or decreases, the average light emission brightness of the light-emitting portion LL[i] also increases or decreases.
Further, the value of the constant current in the constant current circuit 21 of each channel is variable, and the value of the constant current of each constant current circuit 21 is also controlled by the light emission control circuit 30 according to the light emission setting information. As the constant current of the constant current circuit 21[i] increases or decreases, the light emission brightness of the light-emitting portion LL[i] also increases or decreases. Although the value of the constant current of the constant current circuit 21 with respect to each channel can be set according to the light emission setting information, the value of the constant current circuit 21 is set as being common among the 1st to Nth channels herein.
A display region of the LCD panel 14 is divided in 1st to Nth areas, and the light-emitting portion LL[i] is allocated to the light source with respect to the ith area. Further, if the light emission brightness of the corresponding light-emitting portion LL is adjusted according to the brightness of an image displayed in the areas, local dimming in N segments can be achieved. Alternatively, multiple light-emitting systems in
The voltage in the light-emitting portion connecting terminal CH[i] is referred to as a terminal voltage, and is represented by the denotation “V[i]”. The terminal voltages in the channels, i.e., the terminal voltages V[1] to V[N], are provided to the lowest voltage detection circuit 40.
The lowest voltage detection circuit 40 detects a lowest voltage among the terminal voltages V[1] to V[N], and outputs the lowest voltage detected as a voltage VLS. The output voltage VLS of the circuit 40 changes each time the lowest voltage among the terminal voltages V[1] to V[N] changes. That is to say, for example, among the terminal voltages V[1] to V[N], if the terminal voltage V[1] is the lowest voltage at a 1st time point and the terminal voltage V[2] is the lowest voltage at a subsequent 2nd time point, the voltage VL, at the 1st time point coincides with the terminal voltage V[1] at the 1st time point, and the voltage VLS at the 2nd time point coincides with the terminal voltage V[2] at the 2nd time point.
However, if the voltage VLs exceeds a predetermined upper voltage limit (e.g., 5 V), such voltage exceeding the upper voltage limit is not outputted from the circuit 40. Thus, in a situation where the all the terminal voltages V[1] to V[N] are above the upper voltage limit, the voltage VLS becomes the upper voltage limit. Assuming that the switching element 22[1] is turned off and the LED current does not flow to the light-emitting portion LL[i], the terminal voltage V[i] becomes equal or more than the upper voltage limit. Hence, it can also be understood as that the lowest voltage detection circuit 40 is a circuit that detects the terminal voltage V[1] when the switching element 22[1] is set to the turned-on state, the terminal voltage V[2] when the switching element 22[2] is set to the turned-on state, . . . , and terminal voltage V[N] when the switching element 22[N] is set to the turned-on state, and outputs the lowest voltage detected as the voltage VLS (when all the switching elements 22[1] to 22[N] are in the turned-off state, the voltage VLS coincides with the upper voltage limit).
The sample hold circuit 50 appropriately updates the voltage held thereby (to be referred to as a hold voltage VLS_SH) according to the output voltage VLS of the lowest voltage detection circuit 40, and outputs the voltage VLS_SH to the feedback control circuit 60. The sample hold circuit 50 constantly compares the hold voltage VLS_SH with the output voltage VLS of the circuit 40, and keeps the hold voltage VLS_SH if the output voltage VLS is higher than the hold voltage VLS_SH, or updates the hold voltage VLS_SH to the current output voltage VLS if the output voltage VLS is lower than the hold voltage VLS_SH.
The feedback control circuit 60 generates a feedback signal Sfb according to the hold voltage VLS_SH provided from the sample hold circuit 50 and a predetermined reference voltage VREF, and outputs the feedback signal Sfb from a feedback signal output terminal FB. The feedback output terminal FB is connected to the node ND, and a feedback voltage Vfb changes according to the feedback signal Sfb. Thus, the feedback control circuit 60 can control the output voltage Vo (the light emission driving voltage) of the DC/DC converter 11 according to the feedback signal Sfb. The reference voltage VREF is a predetermined positive DC voltage (e.g., 1 V) lower than the upper voltage limit. The hold voltage VLS_SH at the startup of the LED driver 10 can be higher than the reference voltage VREF.
The switching element 51 is connected in series on a wire between the lowest voltage detection circuit 40 and the hold circuit 52. When the switching element 51 is in the turned-off state, the hold circuit 52 does not change and keeps the hold voltage VLS_SH held thereby. When the switching element 51 is in the turned-on state, the output voltage VLS of the circuit 40 is inputted to the hold circuit 52, and the hold circuit 52 updates the hold voltage VLS_SH to the inputted voltage VLS. The hold voltage VLS_SH is outputted from the hold circuit 52. Turning on and off of the switching element 51 is controlled by the control logic 53.
The voltage VLS from the circuit 40 and the hold voltage VLS_SH from the hold circuit 52 are inputted to the control logic 53. The control logic 53 compares the voltage VLS with the hold voltage VLS_SH, sets the switching element 51 to the turned-off state if the voltage VLS is higher than the hold voltage VLS_SH, and sets the switching element 51 to the turned-on state if the voltage VLS is lower than the hold voltage VLS_SH, and the voltage VLS is provided to the hold circuit 52 at this point. However, in a period in which the switching element 55 is in the turned-on state by performing a reset process below, the switching element 55 is not dependent on the high/low relationship between the voltages VLS and VLS_SH and is kept in the turned-off state.
The reset circuit 54 is a circuit capable of outputting a predetermined initial voltage. Only when the switching element 55 disposed between the reset circuit 54 and the hold circuit 52 is on the turned-on state, the initial voltage from the reset circuit 54 is inputted to the hold circuit 52. The hold circuit 52 sets the hold voltage VLS_SH to the initial voltage (that is to say, updates to the initial voltage) upon receiving the input of the initial voltage. The process of setting the hold voltage VLS_SH to the initial voltage is referred to as a reset process. The control logic 53 controls turning on and off of the switching element 55 by providing the reset signal RST to the switching element 55. Thus, the control logic 53 controls the execution of the reset process. The initial voltage can coincide with the reference voltage VREF, or can be higher than the reference voltage VREF.
The error amplifier 60a includes a non-inverting input terminal, an inverting input terminal and an output terminal. In the error amplifier 60a, the hold voltage VLS_SH from the hold circuit 52 is inputted to the non-inverting input terminal, the reference voltage VREF having a predetermined positive DC voltage value is inputted to the inverting input terminal, and the output terminal is connected to the feedback signal output terminal FB. The error amplifier 60a is a current output type transconductance amplifier, and hence an error current signal corresponding to a difference between the hold voltage VLS_SH and reference voltage VREF is outputted from an output terminal of the error amplifier 60a, as the feedback signal Sfb. That is to say, the error amplifier 60a converts a voltage signal of the differential voltage between the hold voltage VLS_SH and reference voltage VREF to the error current signal (the feedback signal Sfb).
Because the feedback signal output terminal FB is connected to the node ND, the current based on the error current signal is inputted and outputted with respect to the node ND. Further, a resistor can also be placed between the terminal FB and the node ND.
More specifically, when the hold voltage VLS_SH is higher than the reference voltage VREF, the error amplifier 60a outputs, by increasing the potential at the node ND, a current based on the error current signal (the feedback signal Sfb) from the output terminal thereof through the terminal FB toward the node ND. With the output of the current, control for reducing the output voltage Vo is performed in the DC/DC converter 11. That is to say, when the hold voltage VLS_SH is higher than the reference voltage VREF, the error current signal (the feedback signal Sfb) for reducing the output voltage Vo is generated.
Conversely, when the hold voltage VLS_SH is lower than the reference voltage VREF, the error amplifier 60a feeds in, by reducing the potential at the node ND, a current based on the error current signal (the feedback signal Sfb) from the node ND through the terminal FB toward the output terminal thereof. With the feed of the current, control for increasing the output voltage Vo is performed in the DC/DC converter 11. That is to say, when the hold voltage VLS_SH is lower than the reference voltage VREF, the error current signal (the feedback signal Sfb) for increasing the output voltage Vo is generated.
As the absolute value of the difference between the hold voltage VLS_SH and the reference voltage VREF increases, the value of the current based on the error current signal also increases.
Further, herein, as shown in
The unit intervals in all channels are common. As shown in
Further, for better illustrations below, a term “on terminal voltage” (referring to
Operation examples EX1_1 and EX1_2 are given below for the operation of the light-emitting system of the first embodiment. A first reference operation example for comparison with the operation example EX1_1 is first described. Further, a second reference operation example for comparison with the operation example EX1_2 is also be to described below.
Due to an error in the forward voltage of each LED forming the light-emitting portion LL, the voltage drops in the light-emitting portions LL[1] to LL[N] among the light-emitting portions LL when the LED current flows can be different from one another. In the situation α, the voltage drop in the light-emitting portion LL[1] among the light-emitting portions LL when the LED current flows is the largest, only the switching element 22[2] among the switching elements 22[1] to 22[N] is set to the turned-on state between the time points tA2 and tA3, and all of the switching elements 22[1] to 22[N] are set to the turned-off state between the time points tA3 and tA4. Therefore, in the situation α, the terminal voltage V[1] between the time points tA1 and tA2 is detected as the lowest voltage VLS, and the terminal voltage V[2] between the time points tA2 and tA3 is detected as the lowest voltage VLS. Between the time points tA3 and tA4, all of the terminal voltages V[1] to V[N] become higher than the upper voltage limit, and the voltage VLS coincides with the upper voltage limit.
Errors can exist in the on terminal voltage in multiple channels due to the error in the forward voltage among the light-emitting portions. With respect to a channel having terminal voltage that is too low, the LED current can be inadequate. To suppress such inadequacy of the LED current, a method of applying a sufficiently high output voltage Vo to each light-emitting portion LL in advance without performing feedback to the DC/DC converter 11 is also considered. However, in this method, there is a concern that excessive heat is generated while the on terminal voltage is increased in futile. Therefore, to avoid the inadequacy of the LED current and to suppress excessive heat generation, a feedback method of returning feedback to the DC/DC converter 11 by way of having the lowest reference voltage among the on terminal voltages of all channels become a predetermined reference voltage is developed.
In the first reference operation example, the feedback method above is adopted. However, the voltage VLS is persistently applied to the non-inverting terminal of the error amplifier 60a, and so the output voltage Vo of the DC/DC converter 11 changes frequently within one unit interval. Such change in the output voltage Vo can cause jittering of light emission brightness of the light-emitting portions LL perceivable to the eyes of a user, and is considered unsatisfactory.
Considering the situation above, in this embodiment, the sample hold circuit 50 is used in aim of stabilization of the voltage provided to the non-inverting input terminal of the error amplifier 60a. An operation example for realizing the stabilization, i.e., the operation example EX1_1, is given below.
The situation α is also taken into account in the operation example EX1_1 Further, herein, it is assumed that the hold voltage VLS_SH adjacently before the time point tA1 is higher than the terminal voltage V[1] at the time point tA1 and the terminal voltage V[1] adjacently after the time point tA1. As such, taking the time point tA1 as a boundary, the switching element 51 is switched from the turned-off state to the turned-on state by the control logic 53, and between the time points tA1 and tA2, the hold voltage VLS_SH is updated to the lowest voltage VLS (i.e., the terminal voltage V[1]) between the time points tA1 and tA2. Next, using the time point tA2 as a boundary, the voltage VLS from the lowest voltage detection circuit 40 increases, and thus the switching element 51 is switched from the turned-on state to the turned-off state by using the logic control 53. Then, as long as the voltage VLS lower than the hold voltage VLS_SH updated between the time points tA1 and tA2 is not outputted from the circuit 40, the turned off state of the switching element 51 is maintained and the voltage VLS_SH is kept unchanged.
In the example in
Accordingly, in the configuration provided with the sample hold circuit 50, by using the feedback method of returning feedback to the DC/DC converter 11, the effect of heat suppression can be enjoyed. Further, the change in the output voltage Vo such as that in the first reference operation example can be suppressed.
In a stable state of the display apparatus 1 after startup, no problem is caused when the operation example EX1_1 is used. However, if the transitional response of such as the startup of the DC/DC converter 11 is taken into account, a further design is preferably added. That is to say, for example, when the display apparatus 1 is first supplied with power and the display apparatus 1 is started, the DC/DC converter 11 is also started. However, during the process of the output voltage Vo increasing from 0 V to a predetermined voltage shortly after the startup of the DC/DC converter 11, the terminal voltage (on terminal voltage) of each light-emitting portion connecting terminal is predicted to be lower than the reference voltage VREF or may be lower than the reference voltage VREF during this process. Therefore, if the following configuration is adopted, that is, if the terminal voltage lower than the reference voltage VREF is sampled and is used and kept as the hold voltage VLS_SH, and the holding is not at all reset, there is a concern that the error amplifier 60a continues feeding the current such that the output voltage Vo of the DC/DC converter 11 increases to more than required. The overly high output voltage Vo is undesirable in terms of heat generation.
It can be considered the same situation when the value of the constant current of the constant current circuit 21 of each channel is changed by changing the light emission setting information. For example, the user of the display apparatus 1 can operate a remote controller attached to the display apparatus 1 so as to instruct the display apparatus 1 to increase or decrease the brightness of the display image in the display apparatus 1. According to the instruction, the CPU 13 sends a required command signal to the LED driver 10 (the LED driver 10A herein) in order to achieve the increase or decrease in the brightness as instructed. The light emission setting information is changed by the command signal received. The following situation β is assumed, that is, along with the change in the light emission setting information, the value of the constant current of the constant current circuit 21 of each channel changes from a current value I1 to a current value I2.
In
In the situation β, the command signal is received by the LED driver 10 (the LED driver 10A herein) before the time point tB2. Thus, by using the time point tB2 as a boundary, the value of the constant current of the constant current circuit 21 of each channel changes from the current value I1 (e.g., 20 mA) to the current value I2 (e.g., 40 mA) greater than the current value I1.
As such, compared to the unit interval 621, the voltage drop in each light-emitting portion LL when the LED current flows is increased in the unit interval 622. Thus, the lowest voltage VLS in the unit interval 622 is lower than the lowest voltage VLS in the unit interval 621. Accordingly, in the situation β, the lowest voltage VLS that is lower than the reference voltage VREF is sampled in the unit interval 622 so as to keep the voltage VLS_SH to be lower than the reference voltage VREF.
In the second reference operation example where the reset process is not performed, once the hold voltage VLS_SH is lower than the reference voltage VREF, the hold voltage VLS_SH stays lower than the reference voltage VREF. Hence, there is a concern that the feedback control for increasing the output voltage Vo is continuously performed such that the output voltage Vo increases to more than required. That is to say, the voltage Vo2_TG in
Considering the described situation, in this embodiment, the reset process that can reset the hold voltage VLS_SH to the initial voltage is formed. The operation example EX1_2 as an operation example with the reset process being performed is described below.
In the operation example EX1_2, the situation β is also assumed. In
As described above, in the situation β, the value of the constant current of the constant current circuit 21 of each channel is set to the current value I1 before the time point tB2, and in at least the unit interval 621, the voltage VLS_SH is kept coincident with the reference voltage VREF and the output voltage Vo of the DC/DC converter 11 is stabilized at the voltage Vo1_TG. Further, the command signal is received by the LED driver 10 (the LED driver 10A herein) before the time point tB2. Thus, by using the time point tB2 as a boundary, the value of the constant current of the constant current circuit 21 of each channel changes from the current value I1 (e.g., 20 mA) to the current value I2 (e.g., 40 mA) greater than the current value I1.
As such, compared to the unit interval 621, the voltage drop in each light-emitting portion LL when the LED current flows is increased in the unit interval 622. Thus, the lowest voltage VLS in the unit interval 622 is lower than the lowest voltage VLS in the unit interval 621. Accordingly, in the situation β, the lowest voltage VLS that is lower than the reference voltage VREF is sampled in the unit interval 622 so as to keep the voltage VLS to be lower than the reference voltage VREF.
If the hold voltage VLS_SH is lower than the reference voltage VREF, the output voltage Vo of the DC/DC converter 11 increases through the effect of the error amplifier 60a. During the interval in which the hold voltage VLS_SH is lower than the reference voltage VREF, the output voltage Vo of the DC/DC converter 11 gradually increases (further, an actual situation can be different, and in
The reset signal RST is kept at a low level before the time point tB3. At the time point tB3, the logic control 53 restores the level of the reset signal RST to a low level after setting the reset signal RST to a high level for infinitesimal time. Thus, the reset process is performed at the time point tB3, and the hold voltage VLS_SH coincides with the initial voltage only in the high-level interval of the reset signal RST. Herein, the initial voltage is set to be higher than the reference voltage VREF. After the level of the reset signal RST has become low level, the hold voltage VLS_SH can be updated according to a comparison result of the hold voltage VLS_SH and the lowest voltage VLs from the lowest voltage detection circuit 40. In the example in
Then, in the example in
At the time point tB4, the control logic 53 again restores the level of the reset signal RST to a low level shortly after setting the level of the reset signal RST to a high level for infinitesimal time. Thus, the reset process is again performed at the time point tB4, and the hold voltage VLS_SH coincides with the initial voltage only in the high-level interval of the reset signal RST. After the level of the reset signal RST has become low level, the hold voltage VLS_SH can be updated according to a comparison result of the hold voltage VLS_SH and the lowest voltage VLS from the lowest voltage detection circuit 40. In the example in
After performing the reset process, when it is made sure that the hold voltage VLS_SH has reached the reference voltage VREF, the control logic 53 determines that the output voltage Vo has reached near the voltage Vo2_TG and sets the reset process not to be performed thereafter.
As described above, in the operation example EX1_2, maintaining of the overly low hold voltage VLS_SH as that in the second reference operation example (referring to
It can be said that, the operation below is performed in the sample hold circuit 50 with respect to the reset process. That is to say, the sample hold circuit 50 starts periodic execution of the reset process if a predetermined reset start condition is true, and then ends the periodic execution of the reset process according to the relationship between the hold voltage VLS_SH updated to the output voltage (i.e., the lowest voltage VLS) of the lowest voltage detection circuit 40 and the reference voltage VREF.
For example, the reset start condition is true if the value of the constant current of the constant current circuit 21 changes from one current value to another current value (e.g., changing from the current value I1 to the current value I2).
Further, for example, when the LED driver 10 (the LED driver 10A herein) is started, the reset start condition is also true. When power is supplied to the display apparatus 1 and the display apparatus 1 is started, the LED driver (the LED driver 10A herein) is also started along with the DC/DC converter 11, and shortly after the two have started, the output voltage Vo is in a progress of increasing from 0V to the predetermined voltage. Thus, the LED driver 10 (the LED driver 10A herein) including the sample hold circuit 50 is started according to the voltage Vi provided to the power voltage input terminal VCC, and it is accordingly understood as that the reset start condition is true.
In any situations of transitional changes in output voltage Vo of the DC/DC converter 11, the reset start condition can also be true.
After the periodic execution of the reset process has started, the control logic 53 can determine that a reset end condition is true upon observing that the hold voltage VLS_SH updated to the output voltage (i.e., the lowest voltage VLS) of the lowest voltage detection circuit 40 coincides with the reference voltage VREF, and end the periodic execution of the reset process. More specifically, for example, in each unit interval after the periodic execution of the reset process has started, the hold voltage VLS_SH is updated to the output voltage (i.e., the lowest voltage VL) of the circuit 40 by turning on the sample switching element 51, and the control logic 53 refers and uses the hold voltage VLS_SH immediately before the unit interval ends as a determination voltage. Moreover, the control logic 53 compares the determination voltage with the reference voltage VREF, determines that the reset end condition is true if a difference between the determination voltage and the reference voltage VREF is less than a predetermined infinitesimal voltage, and ends the periodic execution of the reset process. Alternatively, the reset end condition can be determined as true if a state in which the difference between the determination voltage and the reference voltage VREF is less than the predetermined infinitesimal voltage lasts for multiple unit intervals, and the periodic execution of the reset process is ended. The infinitesimal voltage can be understood as substantially zero.
The second embodiment of the present invention is to be described below. The second embodiment as well as third and fourth embodiments below are embodiments on the basis of the first embodiment. For items not particularly described in the second to fourth embodiment, given that there is not contradiction, the details of the first embodiment are also applicable to the second to fourth embodiment. In the explanation regarding the second embodiment, for any contradictory items between the first and second embodiments, the details of the second embodiment prevail (the same applies to the third and fourth embodiment). Given that there is no contradiction, any multiple embodiments among the first to fourth embodiments can be combined as desired.
A light-emitting device driving system is formed by a power supply device including the DC/DC converter 11 and the LED driver 10B, and the backlight portion 12B is added to the light-emitting device driving system to form a light-emitting system. Alternatively, the switching elements SW[1] to SW[M] can be considered as being included in the constituting components of the light-emitting device driving system and the light-emitting system.
The switching element SW[i] has a first terminal, a second terminal and a control terminal. A switch control signal G[j] is provided to the control terminal of the switching element SW[i], and turning on and off of the switching element SW[i] is controlled according to the switch control signal G[j] (where j is an integer). The switching elements SW[1] to SW[4] can be configured in advance as P-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) In this case, the first terminal, the second terminal and the control terminal of the switching element SW[j] are equivalent to the source, drain and gate. The switching element SW[j] becomes the turned-on state by setting the switch control signal G[j] to a low level (that is to say, the first terminal and the second terminal of the switching element SW[j] are connected), and the switching element SW[j] becomes a turned-off state by setting the switch control signal G[j] to a high level (that is to say, the first terminal and the second terminal of the switching element SW[j] are disconnected). At this point, the high level of the switch control signal G[j] coincides with the level of the voltage Vo, and the low level of the switch control signal G[j] is lower than the level of the voltage Vo.
The backlight portion 12B includes (N×M) light-emitting portions LL. The configuration and operation details of the DC/DC converter 11 are identical to those given in the description associated with the first embodiment. However, in the second embodiment, the output terminal Vo of the DC/DC converter 11 is not directly connected to each light-emitting portion LL forming the backlight portion 12B, but is connected to the first terminal of each of the switching elements SW[1] to SW[M]. The second terminals of the switching elements SW[1] to SW[M] are respectively connected to high-potential terminals of N light-emitting portions LL.
Again referring to
It can be understood according to the description that, as shown in
The LED driver 10B in
Multiple external terminals exposed from a housing of the LED driver 10B are provided in the LED driver 10B, wherein the multiple external terminals include the switch control terminals GC[1] to GC[4] and the voltage input terminal VINSW. The output voltage Vo of the DC/DC converter 11 is provided to the voltage input terminal VINSW. The switch control circuit 70 generates switch control signals G[1] to G[4] by using the voltage Vo provided to the voltage input terminal VINSW. The switch control terminals GC[1] to GC[4] are respectively connected to control terminals of the switching elements SW[1] to SW[4]. The switch control circuit 70 provides the switch control signals G[1] to G[4] through the switch control terminals GC[1] to GC[4] to the control terminals of the switching elements SW[1] to SW[4], and accordingly controls turning on and off of the switching elements SW[1] to SW[4].
Using the configuration above, in the second embodiment, when the switching elements SW[j] and 22[i] are both in the turned-on state, the constant current of the constant current circuit 21[i] flows from the output terminal 11a, and passes through the switching element SW[j], the light-emitting portion LL[i, j], the light-emitting portion connecting terminal CH[i] and the switching element 22[i] to serve as the LED current, and the light-emitting portion LL[i, j] emits light as a result. When at least one switching element between the switching elements SW[j] and 22[i] is in the turned-off state, the current does not flow to the light-emitting portion LL[i, j] and the light-emitting portion LL[i, j] accordingly does not emit light.
As shown in
In each of the unit intervals, only any one of the switching elements SW[1] to SW[4] is selectively set to the turned-on state. That is to say, in the jth PWM interval of each unit interval, the switch control circuit 70 in
The light emission control circuit 30 generates a PWM signal with respect to the 1st to 4th PWM intervals and each channel according to the light emission setting information, and provides the PWM signal with respect to each PWM interval and each channel to the switching element 22, accordingly controlling the duty cycle of the switching element 22 with respect to each PWM interval and each channel.
That is to say, in the 1st PWM interval, the duty cycles of the switching elements 22[1] to 22[N] are controlled according to the PWM signal generated in the 1st PWM interval with respect to each channel, and light emission control of the light-emitting portions LL[1, 1] to LL[N, 1] belonged the first group (referring to
Similarly, in the 2nd PWM interval, the duty cycles of the switching elements 22[1] to 22[N] are controlled according to the PWM signal generated in the 2nd PWM interval with respect to each channel, and light emission control of the light-emitting portions LL[1, 1] to LL[N, 1] belonged the second group (referring to
The same applies to the 3rd and 4th PWM intervals.
As such, the in the second embodiment, the (N×M) light-emitting portions LL are divided into M groups and light emission control is performed in a time division manner. The switch control circuit 70 functions by selectively applying, in cooperation with the switching elements SW [1] to SW [M], the output voltage Vo (light emission driving voltage) of the DC/DC converter 1 to the (N×M) light-emitting portions LL in a time division manner.
The configuration and operation details of the lowest voltage detection circuit 40, the sample hold circuit 50 and the feedback control circuit 60 are identical to the configuration and operation details given in the description associated with the first embodiment. In the 1st PWM interval, the lowest voltage among the terminal voltages V[1] to V[n] dependent on the LED forward voltage of the light-emitting portions LL belonged to the first group is outputted as the voltage VLS from the circuit 40; in the 2nd PWM interval, the lowest voltage among the terminal voltages V[1] to V[n] dependent on the LED forward voltage of the light-emitting portions LL belonged to the second group is outputted as the voltage VLS from the circuit 40. The same applies to the 3rd and 4th PWM intervals.
As given in the description associated with the first embodiment, the output voltage VLS of the circuit 40 changes each time the lowest voltage among the terminal voltages V[1] to V[N] changes (referring to
In the second embodiment, since the LED current is provided to the light-emitting portions LL in a time division manner with respect to each group, the voltage having taken into account the LED forward voltage of the (N×M) light-emitting portions LL can be obtained as the hold voltage VLS_SH. Thus, the DC/DC converter 11 is controlled in a way that the output voltage Vo appropriate for the backlight portion 12B in overall is outputted from the DC/DC converter 11.
Thus, regarding the voltage drop in the light-emitting portions LL while the LED current flows, assuming that the voltage drop in the light-emitting portion LL[2, 3] among all of the light-emitting portions LL forming the backlight portion 12B is the largest, the terminal voltage V[2] when the LED current flows to the light-emitting portion LL[2, 3] in the 3rd PWM interval is sampled as the hold voltage VSL_SH and provided to the error amplifier 60a.
Regarding the second embodiment, in a situation where situation α described in
Regarding the second embodiment, in a situation where situation β described in
In the second embodiment, the display region of the LCD panel 14 can be divided into areas AR[1, 1] to AR[N, M], and the light-emitting portion LL[i, j] is allocated to the light source corresponding to the area AR[i, j]. Further, if the light emission brightness of the corresponding light-emitting portions LL can be adjusted according to the brightness of an image displayed in the areas, local dimming in (N×M) segments can be achieved. That is to say, in order to use the configuration of the first embodiment to achieve local dimming in (N×M) segments, M LED drivers 10A are needed. However, if the configuration of the second embodiment is used, the number of the LED driver 10B needed is one, which brings better benefits for reducing overall costs of the display apparatus.
The number of the light-emitting portions LL connected to one LED driver is increased compared to the configuration of the first embodiment, and correspondingly, in the second embodiment, appropriate feedback control for the output voltage Vo becomes more critical. By using the feedback control of the circuits 40, 50 and 60, heat generation and the change in the output voltage Vo can be appropriately suppressed.
Further, multiple light-emitting systems in
The third embodiment of the present invention is to be described below. The LED driver 10 is formed by using a semiconductor integrated circuit, and an electronic component accommodated with the semiconductor integrated circuit is referred to as a driver integrated circuit 200. The driver integrated circuit 200 is an electronic component formed by encapsulating a semiconductor integrated circuit forming the LED driver 10 into a housing (a package) made of resin. Multiple external terminals exposed on the outside of the driver integrated circuit 200 are provided at the housing (in other words, the housing of the LED driver 10) of the driver integrated circuit 200.
The back surface of the housing of the driver integrated circuit 200 appears as a rectangular (including a square) in shape, and four vertices of the rectangle are respectively vertices VT1 to VT4. A side connecting the vertices VT1 and VT2, a side connecting the vertices VT2 and VT3, a side connecting the vertices VT3 and VT4, and a side connecting the vertices VT4 and VT1 are respectively referred to as sides SD1, SD2, SD3 and SD4. The sides SD1 and SD3 are parallel and opposite to each other. The sides SD2 and SD4 are parallel and opposite to each other.
The arrangement of the external terminals of the driver integrated circuit 200 shown in
A total of 14 external terminals are disposed on the side SD1 On the side SD1, terminals VINSW, GC[4], GC[3], GC[2], GC[1], CH[24], CH[23], CH[22], CH[21], LGND, CH[20]. CH[19], CH[18] and CH[17] serving as external terminals are sequentially arranged from the vertex VT1 toward the vertex VT2.
A total of 9 external terminals are disposed on the side SD2. On the side SD2, terminals CH[16], CH[15], CH[14], CH[13], LGND, CH[12], CH[11], CH[10] and CH[9] serving as external terminals are sequentially arranged from the vertex VT2 toward the vertex VT3.
A total of 14 external terminals are disposed on the side SD3. On the side SD3, terminals CH[8], CH[7], CH[6], CH[5]. LGND. CH[4], CH[3], CH[2], CH[1], FAILB, SDO, SCLK, SI and SCSB serving as external terminals are sequentially arranged on from the vertex VT3 toward the vertex VT4.
A total of 9 external terminals are disposed on the side SD4. On the side SD4, terminals VIO, VSYNC, HSYNC, ISET, VREG15, GND, VREG50, FB and VCC serving as external terminals are sequentially arranged from the vertex VT4 toward the vertex VT1.
Functions of the terminals VINSW, GC[1] to GC[4], CH[1] to CH[24], FB and VCC are as given in the description associated with the first or second embodiment. Functions of the other terminals are described below.
The terminal LGND disposed on each of the sides SD1 to SD3 is a ground terminal to be connected to a ground wire of an analog circuit. The analog circuit includes the DC/DC converter 11 and the backlight portion 12. The LED current flows from the output terminal 11a of the DC/DC converter 11 through the light-emitting portion LL and the light-emitting portion connecting terminal CH to the ground terminal LGND. On the other hand, the terminal GND provided on the side SD4 is a ground terminal to be connected to a ground wire of a digital circuit. The digital circuit includes the CPU 13. The ground wire of the analog circuit and the ground wire of the digital circuit have a mutually common ground potential, and patterns are separated in a way that the input and output of currents between these circuits is as small as possible.
Communication between the CPU 13 and the driver integrated circuit 200 is implemented by a serial peripheral interface (SPI). At this point, the CPU 13 functions as a host device, and the driver integrated circuit 200 functions as a peripheral device. Communication based on SPI is realized by receiving and transmitting chip selection signals, clock signals, data input signals and data output signals. The terminals SCSB, SCLK, SDI and SDO function as communication terminals for communication based on SPI. However, in a situation where the configuration of the CPU 13 serving as a host device includes only one peripheral device, the terminal SCSB can be omitted. The terminal SCSB is a chip select terminal for receiving a chip selection signal from the CPU 13. The terminal SCLK is a clock input terminal for receiving a clock signal from the CPU 13. The terminal SDI is a data input terminal for receiving a data signal from the CPU 13. The terminal SDO is a data output terminal for receiving an output data signal from the CPU 13.
An abnormality detection circuit (not shown) for detecting whether an abnormality (a temperature-related abnormality or a voltage-related abnormality) has occurred in the driver integrated circuit 200 is provided in the driver integrated circuit 200. The terminal FAILB is a fail terminal for outputting a detection result indicative of an abnormality to the outside (e.g., the CPU 13).
The terminal VIO is a voltage input terminal for receiving a voltage the same as the power voltage. In the driver integrated circuit 200, a communication interface (not shown) in charge of communicating with the CPU 13 operates by using the voltage inputted to the terminal VIO.
The terminals VSYNC and HSYNC are terminals for receiving the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync. In the driver integrated circuit 200, the unit interval can be specified by the vertical synchronization signal Vsync inputted to terminal VSYNC. The horizontal synchronization signal Hsync is equivalent to a pulse synchronization signal including the number of horizontal lines of the LCD panel 14 within one cycle of the vertical synchronization signal Vsync. In the driver integrated circuit 200, the PWM signal can also be generated by using the horizontal synchronization signal Hsync. Sometimes the terminal HSYNC is omitted from the driver integrated circuit 200.
The terminal ISET is a current setting terminal for specifying the maximum value of the constant current of the constant current circuit 21 in each channel. On the outside of the driver integrated circuit 200, a setting resistor (not shown) is provided between the terminal ISET and the ground wire, and the maximum value of the constant current is determined according to the resistant value of a setting resistor.
A regulator circuit (not shown) is provided in the driver integrated circuit 200. The regulator circuit (not shown) generates a predetermined first DC voltage (e.g., 5.0 V) and a predetermined second DC voltage (e.g., 1.5 V) according to the input voltage Vi of the power voltage input terminal VCC, and applies the first and second DC voltages to the terminals VREG50 and VREG15, respectively. On the outside of the driver integrated circuit 200, a capacitor is placed between the terminal VREG50 and the ground line and between the terminal VREG15 and the ground line.
The configuration of the external terminals is determined by separating external terminals requiring a larger withstand voltage from external terminals without such requirement as far as possible. Thus, it is then not easy to result in circuit damage caused by short circuit between adjacent terminals.
More specifically, the withstand voltages of the terminals GC[1] to GC[4], CH[1] to CH[24] and VINSW are set to a predetermined first withstand voltage, and the withstand voltages of the terminals FAILB, SDO, SCLK, SDI, SCSB, VIO, VSYNC, HSYNC, ISET and VREG15 are set to a predetermined second withstand voltage. The first withstand voltage has a value (e.g., 40 V) equal or more than the maximum of the output voltage Vo that can be outputted from the DC/DC converter 11. The second withstand voltage is lower than the first withstand voltage, and can be in a same level (e.g., 10 V) as the withstand voltage of the terminal of the CPU 13.
The withstand voltages of the terminals FB and VCC are set to a predetermined third withstand voltage. The third withstand voltage is lower than the first withstand voltage but higher than the second withstand voltage. However, the withstand voltage of the terminals VB and VCC can also be set to the first withstand voltage or the second withstand voltage. The withstand voltages of the terminals VREG50 and GND can be set to the second withstand voltage or the third withstand voltage. The withstand voltage of the terminal LGND can be set to the first withstand voltage, or can be set to the second or third withstand voltage.
The fourth embodiment of the present invention is described below. In the fourth embodiment, the application techniques, variation techniques or supplementary items suitable for the first to third embodiments are described.
In the third embodiment (
The DC/DC converter 11 can also be formed by a semiconductor integrated circuit. In this case, a power supply integrated circuit (not shown) of a semiconductor integrated circuit forming the DC/DC converter 11 and accommodated in a housing, and the driver integrated circuit 200 of a semiconductor integrated circuit forming the LED driver 10 and accommodated in a housing are separately assembled in the display apparatus 1. However, the semiconductor integrated circuit forming the DC/DC converter 11 and the semiconductor integrated circuit forming the LED driver 10 can also be accommodated in a common housing so as to form one single driver integrated circuit.
As described above, each light-emitting portion LL includes one or more than one light-emitting device that emits light by a current provided. The LED serving as the light-emitting device can be an LED of any type, or can be an organic LED achieving organic electroluminescence (EL). Further, the light-emitting device can also be a device that is not classified as an LED, for example, a laser diode.
In this embodiment, the light-emitting device driver apparatus implemented as an LED driver is not limited to serving for backlight applications of an LCD panel, but can be used in various applications such as laser imaging detection and ranging (LIDAR) systems using laser diodes or head-up displays.
Various modifications within the range of the technical concept defined by the claims can be appropriately made to the embodiments of the present invention. The embodiments described above are merely examples of the embodiments of the present invention, and meanings of the present invention or the terms of the constituting components are not limited to the meanings described in the embodiments above. The specific values given in the description are merely examples, and can be modified to various other values.
| Number | Date | Country | Kind |
|---|---|---|---|
| JP2019032821 | Feb 2019 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 4242730 | Golias | Dec 1980 | A |
| 5347201 | Liang | Sep 1994 | A |
| 6912139 | Kernahan | Jun 2005 | B2 |
| 7132804 | Lys | Nov 2006 | B2 |
| 8274248 | Hirata | Sep 2012 | B2 |
| 8373358 | Hsu | Feb 2013 | B2 |
| 9232579 | Sasaki | Jan 2016 | B2 |
| 9282606 | Kuang | Mar 2016 | B1 |
| 9374083 | Sawada | Jun 2016 | B2 |
| 9648676 | Angeles | May 2017 | B2 |
| 9877367 | Wang | Jan 2018 | B2 |
| 10676017 | Murakami | Jun 2020 | B2 |
| 10887957 | Chen | Jan 2021 | B2 |
| 11089663 | Nishigami | Aug 2021 | B2 |
| 20020161511 | Fujikawa | Oct 2002 | A1 |
| 20040095020 | Kernahan | May 2004 | A1 |
| 20040095108 | Kernahan | May 2004 | A1 |
| 20040095109 | Kernahan | May 2004 | A1 |
| 20070239003 | Shertukde | Oct 2007 | A1 |
| 20070262966 | Nishimura | Nov 2007 | A1 |
| 20090009486 | Sato | Jan 2009 | A1 |
| 20090230891 | Zhao | Sep 2009 | A1 |
| 20100134040 | Elder | Jun 2010 | A1 |
| 20110121744 | Salvestrini | May 2011 | A1 |
| 20110227497 | Hu | Sep 2011 | A1 |
| 20130320880 | Walker | Dec 2013 | A1 |
| 20140042924 | Lee | Feb 2014 | A1 |
| 20150054418 | King | Feb 2015 | A1 |
| 20150366018 | Kuang | Dec 2015 | A1 |
| 20170272093 | Kim | Sep 2017 | A1 |
| 20180174507 | Ohara | Jun 2018 | A1 |
| 20180373094 | Ryoo | Dec 2018 | A1 |
| 20190229630 | Halberstadt | Jul 2019 | A1 |
| 20190254130 | Chen | Aug 2019 | A1 |
| 20200275537 | Takahashi | Aug 2020 | A1 |
| 20200314368 | Tsukuda | Oct 2020 | A1 |
| Number | Date | Country |
|---|---|---|
| 101883458 | Nov 2010 | CN |
| 101990715 | Mar 2011 | CN |
| 102045921 | May 2011 | CN |
| 102136252 | Jul 2011 | CN |
| 202258258 | May 2012 | CN |
| 203722871 | Jul 2014 | CN |
| 2448013 | May 2012 | EP |
| 2013-222515 | Oct 2013 | JP |
| Entry |
|---|
| Partial English Translation of Office Action for corresponding Chinese Appln. No. 202010122197.1, dated Mar. 3, 2022, 11 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20200275537 A1 | Aug 2020 | US |
