Micro-LEDs (μLEDs) that can be monolithically integrated with CMOS electronics and have dimensions as small as one micrometer are in demand for various applications (e.g., the emerging revolution in virtual reality (VR)/augmented reality (AR), etc.). Achieving such μLEDs, however, has remained a daunting challenge. The past two decades have witnessed the solid-state lighting revolution powered by GaN-based broad area light emitting diodes (LEDs), which generally have lateral dimensions on the order of millimeter. For the emerging revolution in virtual reality (VR)/augmented reality (AR), however, LEDs with dimensions as small as one micrometer (e.g., LEDs with surface area approximately one million times smaller than conventional broad area devices, etc.) are in demand. It is desired that the micro, or submicron scale LEDs (μLEDs) can exhibit high efficiency, high brightness, highly stable operation, ultralow power consumption, and full-color emission, and can be monolithically grown on Si for integration with CMOS electronics. To date, however, it has remained a daunting challenge to achieve high efficiency μLEDs. For example, the external quantum efficiency often drops to well below 1% when the lateral dimensions of conventional high efficiency InGaN quantum well LEDs are shrunk to micrometer, or submicron scale. The efficiency cliff of μLEDs is primarily due to surface damage and the resulting nonradiative surface recombination induced by top-down etching of conventional quantum well structures. The efficiency cliff typically becomes even more severe for long wavelength (e.g., green LEDs, red LEDs, greater than 500 nm, 500-650 nm, etc.) due to the enhanced defect formation related to the large misfit between InN and GaN. Performance of such long wavelength devices also often suffer severely from quantum-confined Stark effect (QCSE).
Systems and methods presented herein include efficient and effective Light Emitting Devices (LED) devices. In one embodiment, a light emitting device comprises: a substrate comprising silicon; a first portion comprising a group III-V compound component with a first type of doping; a second portion comprising an active region, a shell comprising a gradient configuration with piezoelectric field compensation characteristics; and a third portion comprising a group Ill-V compound component with a second type of doping, The silicon substrate is coupled to the first portion. The first portion and shell are coupled to the second portion with is in turn coupled to the third portion. The active region comprises a quantum core structure with strain compensation barriers and polarization doping. The strain compensated barriers form multiple quantum wells. In one embodiment, the strain compensation barriers include AlGaN in a configuration that compensates tensile strain within the active region. The AlGaN can also be configured to induce polarization charges and enhance indium incorporation. In one embodiment, the shell comprises AlGaN with a negative Al composition gradient.
In one embodiment, the first portion, second portion, and third portion comprise nanostructure components (e.g., forming a nanowire, etc.). In one exemplary implementation, a nanowire is one of a plurality of nanowires included in the light emitting device. The first portion, second portion, third portion and shell form a nanowire core with polarization doping configured to enable stable operation and light emission. The light emission can be a long wavelength range. The light emitting device can be configured to operate with negligible quantum-confined Stark effect. In one exemplary implementation, the light emitting device is configured to create stable wavelength emissions.
In one embodiment, the substrate includes electronics (e.g., CMOS electronics, etc.). In one exemplary implementation, the light emitting device is a micro-light emitting device and the substrate includes electronics monolithically integrated in the micro-light emitting device (e.g., a micro-light emitting diode (PLED), etc.).
In one embodiment, a method comprises: forming a substrate comprising silicon; forming a first portion comprising a group III-V compound component with a first type of doping; forming a second portion comprising an active region, wherein the active region comprises a quantum core structure with strain compensated barriers, wherein the second portion is coupled to the first portion; forming a shell coupled to the second portion, wherein the shell comprises polarization doping, and forming a third portion comprising a group III-V compound component with a second type of doping, wherein the third portion is coupled to the second portion. Forming the substrate includes forming electronic components in the silicon. The substrate, the first portion, the second portion, shell and third portion are monolithically formed. In one exemplary implementation, the first portion, the second portion, shell, and third portion are grown on substrate in a configuration that reduces thermal accumulation within the device area.
The accompanying drawings, which are incorporated in and form a part of this specification, are included for exemplary illustration of the principles of the present invention and are not intended to limit the present invention to the particular implementations illustrated therein. The drawings are not to scale unless otherwise specifically indicated.
Reference will now be made in detail to the various embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While described in conjunction with these embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the disclosure. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.
The figures are not necessarily drawn to scale, and only portions of the devices and structures depicted, as well as the various layers that form those structures, are shown. For simplicity of discussion and illustration, only one or two devices or structures may be described, although in actuality more than one or two devices or structures may be present or formed. Also, while certain elements, components, and layers are discussed, embodiments according to the invention are not limited to those elements, components, and layers. For example, there may be other elements, components, layers, and the like in addition to those discussed.
Systems and methods presented herein include efficient and effective light emitting devices (e.g., Light Emitting Diode (LED), etc.). In one embodiment, an=light emitting device includes an introduced core-shell structure and polarization doping. The introduced core-shell structure and polarization doping enable stable operation and light emission (e.g., with negligible quantum-confined Stark effect, etc.). In one embodiment, a light emitting device includes a barrier (e.g., an AlGaN barrier, etc.) that effectively compensates the tensile strain within the active region, which significantly reduces the strain distribution and results in higher indium incorporation (e.g., in comparison to a conventional GaN barrier, etc.). In one embodiment, a light emitting device configuration can be considered a Micro-LED (LED). In one embodiment, an light emitting device is grown on a substrate in a configuration that reduces thermal accumulation within the device area. It is appreciated that various methods and aspects of growing a light emitting device (e.g., μLED, etc.) can be implemented (e.g., grown on a silicon (Si) substrate, monolithically grown, grown directly on the substrate, grown with lateral dimensions as small as 0.9 μm, etc.). The presented novel embodiments provide new insights and a viable path for the design, fabrication, and integration of high-performance LEDs for various applications (e.g., on-chip optical communication, emerging virtual reality/augmented reality (VR/AR) devices and systems, etc.).
Recent advances of III-nitride nanostructures (e.g., nanowires, etc.) have provided a promising path to overcome the efficiency cliff of μLEDs. Typically, μLEDs made of bottom-up nanostructures are free from etch-induced damage on the surface and misfit dislocations in the device active region. However, traditionally there have been few studies of μLEDs monolithically grown on Si substrate, due to the large lattice mismatch between GaN and Si. A significant traditional challenge for nanowire μLEDs, particularly for those operating at long wavelengths, however, in the presence of point defects, in both the device active region and on the lateral surfaces, largely due to the relatively low growth temperature required to enhance indium incorporation. In one embodiment, such a challenge is addressed by a strain-compensated active region design, In one exemplary implementation, a strain-compensated active region design includes replacing a GaN barrier in the quantum well active region with an AlGaN barrier for a smaller mismatch strain energy, and therefore a higher growth temperature to reduce defect formation. Moreover, with a wider bandgap, AlGaN can provide stronger carrier confinement within the InGaN active region and reduces the carrier leakage related to non-radiative recombination. However, in one exemplary implementation higher Al composition may cause an enhanced piezoelectric field for quantum wells (QWs) grown on the c-plane, which reduces the oscillator strength of the QW fundamental transition and causes a carrier-density sensitive emission.
Approaches presented herein can address the traditional conundrums associated with achieving stable μLED operations. In one embodiment, an light emitting device includes a shell configured to mitigate/overcome piezoelectric field issues. In one exemplary implementation, an AlGaN/GaN shell around the active region with a negative Al composition gradient is included along the c-axis of InGaN nanowire μLEDs. In one embodiment, a μLED is fabricated based on a N-polar nanowire array synthesized through a bottom-up selective area epitaxy (SAE) process. In one exemplary implementation, the devices exhibits strong green emission with a lateral dimension below 1 pam. Detailed power-dependent photoluminescence (PL) measurements and current-dependent electroluminescence (EL) measurements show negligible shifts in the peak energy, contrasting the blue-shifts commonly measured from InGaN/GaN QWs because of quantum-confined Stark effect (QCSE). In one embodiment, the composition gradient GaN/AlGaN shell around the InGaN QWs can effectively induce bound positive charges and free electrons, which screen the internal electrostatic field within the InGaN QW. In one exemplary implementation, an AlGaN barrier can effectively compensate the tensile strain caused by InGaN QWs and lead to an enhanced indium incorporation as well as longer emission wavelengths. Moreover, light emitting devices are achieved on a silicon (Si) substrate instead of commonly used sapphire substrate, which reduces thermal accumulation within the device area and enables seamless integration with CMOS electronics. In one embodiment, the presented novel light emitting device systems and methods provide new insights and a viable approach for achieving high performance light emitting devices (e.g., μLEDs, etc.) with highly ultra stable operation on Si for their emerging applications in VR/AR and ultrahigh resolution mobile displays.
First portion 121 includes a group III-V compound component with a first type of doping. Second portion 130 includes an active region, wherein the active region comprises a quantum core structure with strain compensation barriers (e.g., 131, 132, and 133, etc.) and polarization doping. The shell comprises a gradient configuration with piezoelectric field compensation characteristics. The third portion 140 includes a group III-V compound component with a second type of doping.
In one embodiment, EDS elemental analyses (e.g.,
In one embodiment, power-dependent PL properties of samples with AlGaN barrier (Sample A) and GaN barrier (Sample B) are investigated under resonant excitation with a 405 nm continuous wave (CW) laser at room temperature. The excitation power density is varied from ˜0.5 W/cm2 to ˜400 W/cm2.
The effect of Al incorporation on the carrier radiative recombination process can be related with the Al distribution in the active region. III-nitrides are polar materials and the grading of (Al,Ga)N composition along the c-axis induces polarization charges in the bulk nanowire, which further results in accumulated free charge carriers with opposite sign. In one embodiment, the Al content features a negative gradient along the [000
In one embodiment, the strain distribution in InGaN/(Al)GaN MQWs is examined using low angle angular dark field (LAADF) STEM. Sample D with single InGaN QW in GaN nanowire is grown for this implementation.
In one embodiment, μLED fabrication is performed by standard passivation, lithography, reactive ion etching and metallization processes. Additional description of exemplary various fabrication process aspects is set forth in the Methods section below. Devices with sizes of ˜900 nm×900 nm are fabricated.
In conclusion, the QCSE effect can be significantly suppressed through adopting AlGaN barriers in InGaN/AlGaN MQWs. In one embodiment, this is achieved through a formation of AlGaN/GaN shell around the active region and with Al composition gradient from bottom to the top of the active region. The free electrons induced by the polarization positive bond charges can effectively screen the internal electric field within the InGaN QWs. Moreover, AlGaN as a quantum barrier can effectively compensate the tensile strain caused by InGaN QW in GaN nanowire. The strain distribution within the active region is directly imaged and analyzed by LAADF-STEM. The strain compensation effect results in an enhanced indium incorporation and thus a longer emission wavelength, and this is achieved without sacrificing the oscillation strength within the QW. In addition, green-emitting nanowire μLEDs on Si substrate with a sub-micrometer size have been demonstrated for the first time. The active region of the μLEDs includes InGaN/AlGaN MQWs and detailed current dependent EL measurements show that negligible QCSE is observed. This work provides a new approach for designing the active region of high-performance multi-color μLEDs. Moreover, the monolithic integration of μLED on Si substrate is of great importance for next generation display, optical communication, and other optoelectronic devices.
In one embodiment, the nanowire μLED heterostructures are grown on a relatively thin N-polar GaN/AlN buffer layer on Si wafer. The SEM image of an exemplary as-grown substrate is shown in Figure Sla, wherein the pit density is ˜8×108 cm−2. Before performing SAE on the N-polar GaN on Si substrate, a Ti patterning process is adopted. Before performing SAE on the N-polar GaN on Si substrate, a Ti patterning process is adopted. Additional explanation can be found in:
In block 610, a substrate comprising silicon is formed.
In block 620, a first portion is formed comprising a group III-V compound component with a first type of doping.
In block 630, a second portion is formed comprising an active region. In one embodiment, the active region comprises a quantum core structure with strain compensated barriers. The second portion is coupled to the first portion.
In block 640, a shell is formed. The shell is coupled to the second portion. The shell comprises an Al gradient configuration. In one embodiment, the gradient forms a negative Al gradient.
In block 650, a third portion is formed comprising a group III-V compound component with a second type of doping. The third portion is coupled to the second portion.
Epitaxy: In one embodiment, the growth of N-polar GaN epilayer on 2 inch Si(111) wafers is performed in a Veeco GENxplor system. The growth started with an unintentionally doped (UID) AlN buffer layer of ˜100 nm and followed by a Si-doped GaN layer of ˜500 nm at a substrate temperature of 770° C., nitrogen flow of 0.3 sccm and plasma power of 350 W. After patterning and standard solvent cleaning, wafer is loaded into a Veeco GEN II system for subsequent nanowire device structure growth. The Ti masked wafer is first nitridized at 400° C. for 10 mins under a nitrogen plasma flow rate of 1 sccm. The n-GaN segment is grown at 690° C., Ga beam equivalent pressure of 3.5×10−7 Torr and nitrogen flow of 0.5 sccm. The estimated growth rate is ˜3 nm/s. The active region is grown at a substrate temperature of 560° C., Ga beam equivalent pressure (BEP) of 6×10−8, In BEP of 1×10−7 Torr and Al BEP of 8×10−9 Torr. The nitrogen flow rate is increased to 0.7 sccm to enhance indium incorporation during active region growth. The p-GaN is grown at 690° C. for 30 mins. Mg BEP of 8×10−9 Torr is used.
Fabrication: In one embodiment, the fabrication starts with atomic layer deposition (ALD) of Al2O3 to fill the air gap and planarize the nanowire array. The top p-GaN of each individual nanowire is revealed by a fluoride-based reactive ion etching (RIE) process. Plasma-enhanced chemical vapor deposition of 320 nm SiO2 is performed as an insulation layer followed by lithography and RIE etching to open the current injection window for each sub-micrometer LED devices. Metal stacks including 2.5 nm Ni/2.5 nm Au/180 nm ITO are used as p-metal contact. ITO deposition is performed using sputtering process to ensure an excellent coverage on the sidewall of the SiO2 insulation layer. Chlorine-based RIE process is used to etch down into the n-GaN. 20 nm Ti/8 nm Au is deposited for n-metal contact. The device is annealed in N2 ambient at 550° C. for 1 min.
Characterizations: In one embodiment, structural properties of the samples are analyzed using a JEOL JEM-3100R05 analytical electron microscope with double Cs-correctors operated at 300 keV. EDS mapping are performed using Thermo Fisher Talos F200X analytical electron microscope. The I-V characteristics are measured using a Keithley 2400 voltage source meter. The PL and EL emission are collected by an optical fiber and spectrally resolved by high-resolution spectrometers, and then detected by liquid nitrogen/thermal electrically cooled CCD cameras.
Thus, efficient and effective light emitting devices are presented. In one embodiment, high-performance tunnel junction deep ultraviolet (UV) light-emitting diodes (LEDs) are created using plasma-assisted molecular beam epitaxy. The device heterostructure is grown under slightly Ga-rich conditions to promote the formation of nanoscale clusters in the active region. The nanoscale clusters can act as charge containment configurations. In one embodiment, an active region comprises Ga(Al)N quantum well heterostructures with barrier layer thicknesses varying (e.g., decreasing, etc.) from a n-AlGaN side to a p-AlGaN side to enhance hole injection and transport. In one exemplary implementation the barrier layer thicknesses nanometers.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in this disclosure is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing this disclosure.
Some portions of the detailed descriptions are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means generally used by those skilled in data processing arts to effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical, magnetic, optical, or quantum signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as “processing”, “computing”, “calculating”, “determining”, “displaying” or the like, refer to the action and processes of a computer system, or similar processing device (e.g., an electrical, optical, or quantum, computing device), that manipulates and transforms data represented as physical (e.g., electronic) quantities. The terms refer to actions and processes of the processing devices that manipulate or transform physical quantities within a computer system's component (e.g., registers, memories, other such information storage, transmission or display devices, etc.) into other data similarly represented as physical quantities within other components.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents. The listing of steps within method claims do not imply any particular order to performing the steps, unless explicitly stated in the claim.
The present invention claims the benefit of and priority to USPTO Provisional application Number: 63/344,491 entitled “LIGHT EMITTING DIODE” (Attorney Docket Number TRTM-0020-00.00) filed on May 20, 2022, and is a continuation of and claims priority to USPTO application Number: Ser. No. 16/044,337 entitled Core-Shell InGaN/AlGaN Quantum Nanowire Photonic Structures (Attorney Docket Number TRTM-P0005) filed on Jul. 24, 2018, which claims priority to and benefit of USPTO Provisional Application No. 62/536,449 Core-Shell InGaN/AlGaN Quantum Nanowire Photonic Structures (Attorney Docket Number 30275/52065) filed on Jul. 24, 2017; and is also a continuation of and claims priority to USPTO application Number: Ser. No. 17/956,571 entitled Methods and Devices for Solid State Nanowire Devices (Attorney Docket Number TRTM-P0007-04C03US) filed on Sep. 29, 2022, which is a continuation of USPTO application Ser. No. 14/776,120 filed on Sep. 14, 2015, which is a 371 of international application PCT/CA2014/000234 filed Mar. 14, 2014 which claims the benefit of provisional applications 61/781,806 filed Mar. 14, 2013 and 61/904,493 filed on Nov. 15, 2013; and is also a continuation of and claims priority to USPTO application Number: Ser. No. 17/800,878 entitled Micrometer Scale Light-emitting Diodes (Attorney Docket Number TRTM-P0010-02N02US) filed on Aug. 18, 2022, which is a 371 of international application PCT/US2021/018559 filed Feb. 18, 2021, which claims the benefit of provisional applications 62/978,168 filed Feb. 18, 2020; and is also a continuation of and claims priority to USPTO application Number: Ser. No. 17/745,753 entitled High Efficiency InGaN Light Emitting Diodes (Attorney Docket Number TRTM-P0014) filed on May 16, 2022, and of international application PCT/US2022/29397 filed May 16, 2022, both of which claim priority to and benefit of USPTO Provisional Application No. 63/188,971 entitle High Efficiency INGaN Nanocrystal tunnel Junction Micro LEDs (Attorney Docket Number TRTM-0014.00.00) filed on May 14, 2021; all of which are incorporated herein by reference.
Number | Date | Country | |
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63344491 | May 2022 | US | |
62536449 | Jul 2017 | US | |
61781806 | Mar 2013 | US | |
61904493 | Nov 2013 | US | |
62978168 | Feb 2020 | US | |
63188971 | May 2021 | US | |
63188971 | May 2021 | US |
Number | Date | Country | |
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Parent | 16044337 | Jul 2018 | US |
Child | 18200375 | US | |
Parent | 17956571 | Sep 2022 | US |
Child | 16044337 | US | |
Parent | 14776120 | Sep 2015 | US |
Child | 17956571 | US | |
Parent | 17800878 | Aug 2022 | US |
Child | 14776120 | US | |
Parent | 17745753 | May 2022 | US |
Child | 17800878 | US | |
Parent | PCT/US22/29397 | May 2022 | US |
Child | 17745753 | US |