The present disclosure claims the priority benefit of Taiwan Patent Application No. 104123703, filed on Jul. 22, 2015, 2015, and Taiwan Patent Application No. 104127620, filed on Aug. 25, 2015, which are incorporated by reference in their entirety.
The present disclosure relates to a light emitting device.
With the evolution of lighting technology, light emitting diode chips (LED chips) have rapid been the dominative light sources used in modern light emitting devices. LED chips have many advantages such as lower power consumption, long service life, environmental friendliness, fast start, and compactness. In addition, the power capability of LED chips has been increasingly improved as the technology becomes more and more mature. Currently, LED chips have replaced traditional light sources in various light emitting devices and make light emitting devices more favorable to conservation of energy.
In practical applications, for color mixing or color changing, there are light emitting devices containing therein a plurality of LED chips. These LED chips emit light rays of different wavelengths, thereby providing color mixing or color changing as their buyers require. In particular, the light emitting devices of this kind usually at least include a first work circuit having a first LED chip and a second work circuit having a second LED chip. Since the first and second LED chips are made using different epitaxy methods or materials and therefore the first and second LED chips have different characteristics, when the same operation current is supplied to both of the first and second working circuits, different voltage drops happen in the first and second working circuits, making the entire light emitting device underperform. For addressing this issue, a resistance element has to be added and electrically connected to one of the working circuits. However, this additional resistance element means increased costs and waste heat.
For solving the foregoing problems, the present disclosure the first provides a scheme for modulating voltage drops in working circuits. Particularly, in this scheme, a light emitting device comprises a first work circuit and a second work circuit. The first work circuit comprises a first LED chip and a first bonding adhesive. The first LED chip is electrically connected in series with the first bonding adhesive. The second work circuit comprises a second LED chip. When an operation current I is used to operate the first work circuit and the second work circuit, the first work circuit has a first voltage drop VW1 and the second work circuit has a second voltage drop VW2, wherein VW1≈VW2.
With the foregoing configuration, the disclosed light emitting device uses the first bonding adhesive that is connected in series with the first LED chip to make the first work circuit that comprises the first LED chip and the first bonding adhesive have a voltage drop similar or identical to that of the second work circuit that comprises the second LED chip. Thereby, the need of the additional resistance element as required in prior-art light emitting devices can be eliminated, and this in turn eliminates the problems about increased costs and waste heat.
The present disclosure as well as a preferred mode of use, further objectives and advantages thereof will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings.
Reference is now made to the accompanying drawings for illustrating the scheme provided by the present disclosure for modulating voltage drops.
In the present aspect, a light emitting device includes a first work circuit and a second work circuit. The first work circuit comprises a first LED chip and a first bonding adhesive. The first LED chip and the first bonding adhesive are electrically connected in series. The second work circuit comprises a second LED chip. When an operation current I is used to operate both of the first and second work circuits, the first work circuit has first voltage drop VW1, and a second work circuit has a second voltage drop VW2, wherein VW1≈VW2. The specific implement is detailed below.
Referring to
Referring to
Referring to
Referring to
It is to be noted that, as shown in
Referring to
Taking specific quantitative values for example, in the present disclosure, the ratio between VW1 and VW2 (or VW3) may be about 0.785 to about 0.95. For example, when the operation current I for the first work circuit CT1, the second work circuit CT2 and the third work circuit CT3 is 10 mA, the first LED chip 120a has the first forward voltage V1, the second LED chip 120b has the second forward voltage V2, and the third LED chip 120c has the third forward voltage V3, wherein the first forward voltage V1 is about 1.9 to about 2.0 Volt, the second forward voltage V2 is about 3.0 to about 3.5 Volt, and the third forward voltage V3 is about 3.0 to about 3.5 Volt. By applying the quantitative values of the operation current I, the first forward voltage V1, the second forward voltage V2, the third forward voltage V3 to Equation (1), the required resistance R1 of the first bonding adhesive 130a can be determined.
In the present disclosure, the first bonding adhesive 130a is a resin composition, which contains conductive ceramic particles. In particular, the resin may be epoxy resin or silicone resin. In the embodiments provided herein for illustrating the present disclosure, epoxy resin is taken for example. The conductive ceramic particles may be any materials that have electric conductivity under given working voltage and current, such as indium-tin oxide particles, carbon particles and any combination thereof. As compared to metal particles, conductive ceramic particles provide higher electric impedance, and are more suitable for modulating the resistance R1 of the first bonding adhesive 130a. Preferably, in the present disclosure, electrically conductive ceramic particles provide electric conductivity. However, without going against the spirit of the present disclosure, a trace amount of metal particles may be added into the first bonding adhesive, thereby obtaining appropriate resistance R1. In the present embodiment, carbon particles having impedance of 3.5×10−5 and indium-tin oxide having impedance of 3.5×10−5 are used for example, without any metal particles. Blending concentration may vary with desired electric conductivity and adhesion or other properties of the resin composition. Based on weight percentage of the resin composition, the electrically conductive ceramic particles have a concentration preferably about 20% to about 80%. A concentration lower than 20% is too low to generate even electric conductivity, while a concentration higher than 80% may adversely affect adhesion or other properties of the bonding adhesive, in turn significantly reducing its operational stability and reliability of end products. However, the present disclosure is not limited to the aforementioned resin composition and material and blending concentration of the electrically conductive ceramic particles. With the disclosure of the present disclosure, people skilled in the art may adjust the material used and concentration to achieve the objectives of the present disclosure readily.
In the present disclosure, the resistance R1 of the first bonding adhesive 130a may be controlled by designing the thickness l and area A of the first bonding adhesive on the surface 110a of the circuit substrate 110. With consideration to the chip area and to the thickness of the final device, the first bonding adhesive preferably has its thickness l ranging from about 2 μm to about 15 μm, and the area A preferably ranges from about 0.015 mm2 to about 0.15 mm2. However, the present disclosure is not limited to the recited thickness and area. With the disclosure of the present disclosure, people skilled in the art may adjust the dimensions and achieve the objectives of the present disclosure readily.
In Table I given below, bonding adhesive materials having various compositions are provided. In some experiments, the various bonding adhesive materials listed in Table I were used to make bonding adhesive having the area A and thickness l as described previously (area: 0.04 mm2; thickness: 8 μm). Table I also reflects the variations of the first voltage drop VW1 of the first work circuit CT1 when the first bonding adhesive 130a of
The data provided in Table I may be used by a designer to determine the suitable material of the first bonding adhesive 130a. For example, in the present embodiment, when the operation current I operates the first work circuit CT1, the second work circuit CT2 and the third work circuit CT3 is 10 mA, the second voltage drop VW2 is about 3.0 to about 3.5V and the third voltage drop VW3 is about 3.0 to about 3.5V. A designer may want to use the first bonding adhesive 130a having appropriate resistance to make the first voltage drop VW1 close to the second voltage drop VW2 and the third voltage drop VW3 (about 3.0 to about 3.5V). As shown in Table I, when the resin composition used to make the first bonding adhesive 130a of
Referring back to
As described previously, after die bonding and wiring, packaging may be performed to protect chips and wire solder. In detail, packaging is performed by using the encapsulation compound 140 to cover chips, leads and the circuit substrate. The encapsulation compound may contain fluorescent powder to further change the color of the emitted light. Preferably, one or more kinds of fluorescent powder selected from below are used: Sr5(PO4)3Cl:Eu2+, (Sr,Ba)MgAl10O17:Eu2+, (Sr,Ba)3MgSi2O8:Eu2+, SrAl2O4:Eu2+, SrBaSiO4:Eu2+, CdS:In, CaS:Ce3+, Y3(Al,Gd)5O12:Ce2+, Ca3Sc2Si3O12:Ce3+, SrSiON:Eu2+, ZnS:Al3+,Cu+, CaS:Sn2+, CaS:Sn2+,F, CaSO4:Ce3+,Mn2+, LiAlO2:Mn2+, BaMgAl10O17:Eu2+,Mn2+, ZnS:Cu+,Cl−, Ca3WO6:U, Ca3SiO4C12:Eu2+, SrxBayClzAl2O4-z/2:Ce3+,Mn2+ (X:0.2, Y:0.7, Z:1.1), Ba2MgSi2O7:Eu2+, Ba2SiO4:Eu2+, Ba2Li2Si2O7:Eu2+, ZnO:S, ZnO:Zn, Ca2Ba3(PO4)3Cl:Eu2+, BaAl2O4:Eu2+, SrGa2S4:Eu2+, ZnS:Eu2+, Ba5(PO4)3Cl:U, Sr3WO6:U, CaGa2S4:Eu2+, SrSO4:Eu2+,Mn2+, ZnS:P, ZnS:P3−,Cl−, ZnS:Mn2+, CaS:Yb2+,Cl, Gd3Ga4O12:Cr3+, CaGa2S4:Mn2+, Na(Mg,Mn)2LiSi4O10F2:Mn, ZnS:Sn2+, Y3Al5O12:Cr3+, SrB8O13:Sm2+, MgSr3Si2O8:Eu2+,Mn2+, α-SrO.3B2O3:Sm2+, ZnS—CdS, ZnSe:Cu+,Cl, ZnGa2S4:Mn2+, ZnO:Bi3+, BaS:Au,K, ZnS:Pb2+, ZnS:Sn2+,Li+, ZnS:Pb,Cu, CaTiO3:Pr3+, CaTiO3:Eu3+, Y2O3:Eu3+, (Y,Gd)2O3:Eu3+, CaS:Pb2+,Mn2+, YPO4:Eu3+, Ca2MgSi2O7:Eu2+,Mn2+, Y(P,V)O4:Eu3+, Y2O2S:Eu3+, SrAl4O7:Eu3+, CaYAlO4:Eu3+, LaO2S:Eu3+, LiW2O8:Eu3+,Sm3+, (Sr,Ca,Ba,Mg)10(PO4)6Cl2:Eu2+,Mn2+, Ba3MgSi2O8: Eu2+,Mn2+, ZnS:Mn2+,Te2+, Mg2TiO4:Mn4+, K2SiF6:Mn4+, SrS:Eu2+, Na1.23K0.42Eu0.12TiSi4O11, Na1.23K0.42Eu0.12TiSi5O13:Eu3+, CdS:In,Te, CaAlSiN3:Eu2+, CaSiN3:Eu2+, (Ca,Sr)2Si5N8:Eu2+ and Eu2W2O7.
The above description explains the spirit and principle of the scheme for modulating voltage drops by referring to the first aspect of the present disclosure, and more aspects will be further provided below.
Referring to
Comparing
Similarly, referring to
In the present embodiment, the resistance of the first bonding adhesive 130a is much greater than the resistance of the second bonding adhesive 130b′, and the resistance of the first bonding adhesive 130a is much greater than the resistance of the third bonding adhesive 130c′. In other words, the first bonding adhesive 130a is of a material different that/those of the second bonding adhesive 130b′ and the third bonding adhesive 130c′. The second bonding adhesive 130b′ and the third bonding adhesive 130c′ may be made of identical or different materials. The layers of bonding adhesive made of different materials may be applied on the circuit substrate 110 one after another. For example, when the second bonding adhesive 130b′ and the third bonding adhesive 130c′ are made of an identical material, and the material of the first bonding adhesive 130a is different from the material of the second bonding adhesive 130b′, the second bonding adhesive 130b′ and the third bonding adhesive 130c′ may be formed in one process, and the first bonding adhesive 130a may be formed in another process. The process may be a dispensing process, a screen printing process, a B-stage prepreg laminating process or other appropriate processes.
Referring to
To sum up, the disclosed light emitting device uses the first bonding adhesive connected in series with the first LED chip to make the first work circuit that comprises the first LED chip and the first bonding adhesive have a voltage drop close or identical to that of the second work circuit that comprises the second LED chip. As such, when used, the light emitting device does not need any additional resistance element as required by the conventional devices, thereby eliminating the problems about increased costs and waste heat.
While the above description teaches using a single vertical chip and the disclosed bonding adhesive to modulate the voltage drop of the work circuit, in practical applications where a plurality of chips are connected in series/parallel, the disclosed scheme is also useful to modulate individual vertical chips and the total voltage drop of the bonding adhesives, so as to make the voltage drops of all the horizontal chips identical, thereby achieving a work circuit having identical voltage drops easily. More details will be given below for explaining the disclosed light emitting device of serial connection and its circuit configuration.
Stated broadly, in the following aspect, the substrate of the light emitting device has a serial-connection design. In addition, the light emitting device has a specially designed circuit substrate, and is suitable to provide plural sets of electric loops with integrated configuration of polarity, so as to simplify circuit configuration of a circuit mainboard at the users' side. This eliminates the needs of jumper wires and multilayer circuit structure, which mean significantly increased costs and reduced reliability of the resulting lamp. In detail, in the present embodiment, the light emitting device comprises a circuit substrate and one or more LED chips, wherein the circuit substrate comprises an insulating base and a first pattern. The insulating base has back to back a first surface and a second surface. The first pattern is configured on the first surface. The first pattern comprises a first pad pair, a second pad pair, a third pad pair, a fourth pad pair, and a communicating pad. The first pad pair comprises a first die-bonding pad and a first matching pad. The second pad pair comprises a second die-bonding pad and a second matching pad. The third pad pair comprises a third die-bonding pad and a third matching pad. The fourth pad pair comprises a fourth die-bonding pad and a fourth matching pad. The communicating pad is electrically connected to the first matching pad and the third die-bonding pad. The LED chips are each configured on one of the first die-bonding pad, the second die-bonding pad, the third die-bonding pad and the fourth die-bonding pad. Thereby, the first pad pair, the third pad pair and the communicating pad constitute a set of electric loop, while the second pad pair and the fourth pad pair each constitute a set of electric loop. A third, a fourth and a fifth aspects will be described below to illustrate the design schemes of the substrate and light emitting devices made therefrom.
In the present embodiment, the insulating base has a first region, a second region, a third region and a fourth region that are arranged into an array. Particularly, referring to
Furthermore, in the present embodiment, the first pattern 220 comprises a first pad pair 221, a second pad pair 223, a third pad pair 225, a fourth pad pair 227 and a communicating pad 228. The first pad pair 221, the second pad pair 223, the third pad pair 225 and the fourth pad pair 227 are configured on the first region R1, the second region R2, the third region R3 and the fourth region R4, respectively. Therein, each of the pad pairs comprises a die-bonding pad and a matching pad. That is, the first pad pair 221 comprises a first die-bonding pad 221a and a first matching pad 221b, the second pad pair 223 comprises a second die-bonding pad 223a and a second matching pad 223b, the third pad pair 225 comprises a third die-bonding pad 225a and a third matching pad 225b, while the fourth pad pair 227 comprises a fourth die-bonding pad 227a and a fourth matching pad 227b. Thereby, the four sets of die-bonding pads and matching pads are paired, and successively configured in the four regions from the first quadrant to the fourth quadrant.
In the present embodiment, the first die-bonding pad 221a is adjacent to the second die-bonding pad 223a, and the third die-bonding pad 225a is adjacent to the fourth die-bonding pad 227a. That is, the first die-bonding pad 221a located in the first region R1/first quadrant and the second die-bonding pad 223a located in the second region R2/second quadrant may be deemed as arranged at two opposite sides of the Y axis of the planar coordinate system and adjacent to each other, while the first matching pad 221b and the second matching pad 223b are configured outside the first die-bonding pad 221a and the second die-bonding pad 223a, respectively and located near the opposite edges of the first surface 212. Similarly, the third die-bonding pad 225a located in the third region R3/third quadrant and the fourth die-bonding pad 227a located in the fourth region R4/fourth quadrant may be deemed as arranged at two opposite sides of the Y axis of the planar coordinate system and adjacent to each other, while the third matching pad 225b and the fourth matching pad 227b are configured outside the third die-bonding pad 225a and the fourth die-bonding pad 227a, respectively and located near the opposite edges of the first surface 212.
In addition, in the present embodiment, the first die-bonding pad 221a has an area greater than the area of the first matching pad 221b. The second die-bonding pad 223a has an area greater than the area of the second matching pad 223b. The third die-bonding pad 225a has an area greater than the area of the third matching pad 225b. The fourth die-bonding pad 227a has an area greater than the area of the fourth matching pad 227b. The term “area” refers to the planar scope the pad covers the first surface 212. In each of the pad pairs, the area of the die-bonding pad is greater than the area of the matching pad, so that when the circuit substrate 200 is latter applied to the light emitting device for working with the LED chips, the LED chips may be set in the die-bonding pads that are relatively large in terms of area in the pad pairs and connected to the corresponding matching pads by means of connecting components (e.g. wiring). However, the present disclosure is not limited to the foregoing modes, and may be modified according to practical needs.
Moreover, in the present embodiment, the communicating pad 228 is electrically connected to the first matching pad 221b and the third die-bonding pad 225a. Furthermore, the communicating pad 228 passes through a division located between the first die-bonding pad 221a and the fourth die-bonding pad 227a. Thereby, the communicating pad 228 electrically connects the third die-bonding pad 225a located in the third region R3 and the first matching pad 221b located in the first region R1, and the first die-bonding pad 221a and the fourth die-bonding pad 227a be deemed as arranged at two opposite sides of the X axis of the planar coordinate system, and separated by the communicating pad 228 to be located at two sides of the communicating pad 228. With the communicating pad 228, the LED chips set on the first pad pair 221 and electrically connected thereto are electrically connected to the LED chips set on the third pad pair 225 and electrically connected thereto, thereby forming a connected circuit.
On the other hand, referring to
It is thus learned that the bottom view of
Moreover, in the present embodiment, the first primary electrode 232a at the back of the first region R1, the second primary electrode 234a at the back of the second region R2, and the third secondary electrode 236b at the back of the fourth region R4 are adjacent to each other. That is, the second primary electrode 234a at the back of the second region R2 and the third secondary electrode 236b at the back of the fourth region R4 are at their places that correspond to the second region R2 and the fourth region R4 and are adjacent to the first primary electrode 232a. Similarly, the first secondary electrode 232b at the back of the third region R3, the second secondary electrode 234b at the back of the second region R2, and the third primary electrode 236a at the back of the fourth region R4 are adjacent to each other. That is, the second secondary electrode 234b at the back of the second region R2 and the third primary electrode 236a at the back of the fourth region R4 are at their places that correspond to the second region R2 and the fourth region R4 and are adjacent to the first secondary electrode 232b.
It is thus learned that in the present embodiment, the primary electrodes and the secondary electrodes may be deemed as being separated by a diagonal extending from the upper right to the lower left corners of the second surface 214 and passing through the second region R2 and the fourth region R4. Therein, the first primary electrode 232a, the second primary electrode 234a and the third secondary electrode 236b are roughly at the upper left side of the diagonal and adjacent to each other, while the first secondary electrode 232b, the second secondary electrode 234b and the third primary electrode 236a are roughly at the lower right side of the diagonal and adjacent to each other. The description related to the diagonal is merely for illustrating the relative locations of the primary electrodes and the secondary electrodes and is not intended to limit the exact locations and orientations of the primary electrodes and the secondary electrodes with respect to the diagonal. The present disclosure is not limited to the foregoing modes, and may be modified according to practical needs.
In addition, in the present embodiment, the first primary electrode 232a has its area approximately equal to the area of the first secondary electrode 232b, and the second primary electrode 234a has its area greater than the area of the second secondary electrode 234b, while the third primary electrode 236a has its area greater than the area of the third secondary electrode 236b. The term “area” refers to the planar scope the electrode covers the second surface 214. Therein, since the second primary electrode 234a and the second secondary electrode 234b correspond to the second die-bonding pad 223a located in the second region R2 (larger in area) and the second matching pad 223b (smaller in area), respectively, the second primary electrode 234a preferably has its area greater than the area of the second secondary electrode 234b. Similarly, since the third primary electrode 236a and the third secondary electrode 236b correspond to the fourth die-bonding pad 227a located in the fourth region R4 (larger in area) and the fourth matching pad 227b (smaller in area), respectively, the third primary electrode 236a preferably has its area greater than the area of the third secondary electrode 236b. In addition, since first primary electrode 232a and the first secondary electrode 232b are configured at the back of the first region R1 and the back of the third region R3, respectively, they may be equal in terms of area. However, the first primary electrode 232a and the first secondary electrode 232b may be different in terms of area. The present disclosure is not limited to the foregoing modes, and may be modified according to practical needs.
Moreover, referring to
Particularly, in the present embodiment, since first primary electrode 232a located at the back of the first region R1, the first primary electrode 232a is electrically connected to the first die-bonding pad 221a located in the first region R1 by the conductive post 240a. Similarly, since first secondary electrode 232b is located in the back of the third region R3, the first secondary electrode 232b is electrically connected to the third matching pad 225b located in the third region R3 by the conductive post 240b. In addition, since the second primary electrode 234a and the second secondary electrode 234b are located at the back of the second region R2, and correspond to the second die-bonding pad 223a and the second matching pad 223b, respectively, the second primary electrode 234a is electrically connected to the second die-bonding pad 223a located in the second region R2 by the conductive post 240c, and the second secondary electrode 234b is electrically connected to the second matching pad 223b located in the second region R2 by the conductive post 240d. Similarly, since the third primary electrode 236a and the third secondary electrode 236b are located at the back of the fourth region R4 and correspond to the fourth die-bonding pad 227a and the fourth matching pad 227b, respectively, the third primary electrode 236a is electrically connected to the fourth die-bonding pad 227a located in the fourth region R4 by the conductive post 240e, and the third secondary electrode 236b is electrically connected to the fourth matching pad 227b located in the fourth region R4 by the conductive post 240f.
With the configuration stated above, in the present embodiment, the first die-bonding pad 221a and the first primary electrode 232a are electrically connected, and the second die-bonding pad 223a and the second matching pad 223b are electrically connected to the second primary electrode 234a and the second secondary electrode 234b, respectively, while the third matching pad 225b and the first secondary electrode 232b are electrically connected, and the fourth die-bonding pad 227a and the fourth matching pad 227b are electrically connected to the third primary electrode 236a and the third secondary electrode 236b, respectively. The first matching pad 221b, the third die-bonding pad 225a and the communicating pad 228 connecting the first matching pad 221b and the third die-bonding pad 225a are not electrically connected to the second pattern 230 by means of the conductive posts. Thereby, when the circuit substrate 200 is used in a light emitting device, the six conductive posts 240a through 240f have each two thereof connected to positive electricity and negative electricity so as to constitute an electric loop, so the circuit substrate 200 provides three sets of electric loops.
Referring to
Particularly, as shown in
In addition, in the present embodiment, since the first matching pad 221b and the third die-bonding pad 225a are electrically connected through the communicating pad 228, and the first die-bonding pad 221a and the third matching pad 225b are electrically connected to the first primary electrode 232a and the first secondary electrode 232b of the second surface 214, respectively, the first LED chip 202a, the first pad pair 221, the third LED chip 202c, the third pad pair 135 and the first electrode pair 232 are electrically connected to each other and constitute a first set of electric loop L1 (as shown in
Moreover, as shown in
Similarly, as shown in
With the configuration stated above, in the present embodiment, as described previously, based on the diagonal extending from the upper right to the lower left parts of the second surface 214 and passing through the second region R2 and the fourth region R4, the first primary electrode 232a, the second primary electrode 234a and the third secondary electrode 236b are roughly at the upper left side of the diagonal and adjacent to each other, while the first secondary electrode 232b, the second secondary electrode 234b and the third primary electrode 236a are roughly at the lower right side of the diagonal and adjacent to each other. Therein, as shown in
At this time, since the first primary electrode 232a, the second primary electrode 234a and the third secondary electrode 236b acting as the positive ends are located at the upper left side of the diagonal and adjacent to each other, they are grouped at the upper left side of the circuit substrate/the insulating base 210. Thus, connecting leads (as the connecting leads L11, L21, L31, L41, L51, L61, L71, L81, L91 shown in
Additionally, where vertical chips are used, since this type of chips has its die-bonding surface an electrically conductive surface, in the process of die bonding, the polarity of the die-bonding surface and the die-bonding pads to be used has to be considered in order to achieve integrated configuration of polarity. In the present embodiment, the first LED chip 202a and the third LED chip 202c are red-light chips, and the second LED chip 202b and the fourth LED chip 202d are blue-light chips. Therein, the red-light chip exemplificatively has its positive electrode at the bottom, and has its negative electrode at the top. When the light emitting device 300 uses such a red-light chip, the red-light chip is preferably configured on the electrically positive die-bonding pad, so that the positive electrode at its bottom is directly connected to the electrically positive die-bonding pad, and then the negative electrode is connected to the electrically negative matching pad through wiring. Comparatively, the blue-light chip is a horizontal chip with its positive and negative electrodes both at its top, so it may be configured on a die-bonding pad of any polarity, and have its positive and negative electrodes connected to the die-bonding pad and the matching pad, respectively, through wiring.
Thereby, the red-light chip as shown in the present embodiment having its positive electrode at the bottom is suitable to be configured on the first die-bonding pad 221a, the second die-bonding pad 223a or the third die-bonding pad 225a. In the present embodiment, the red-light chips are configured on the first die-bonding pad 221a and the third die-bonding pad 225a. Comparatively, the blue-light chip is suitable to be configured on any of the four die-bonding pads. In the present embodiment, the blue-light chips are configured on the second die-bonding pad 223a and the fourth die-bonding pad 227a. However, the present disclosure puts no limitation to the type and amount of the LED chips, and these variables may be determined according to practical needs. Therein, since fourth die-bonding pad 227a is electrically connected to the third primary electrode 236a to make it electrically negative, the fourth die-bonding pad 227a is not suitable for connecting a red-light chip having its positive electrode at the bottom as exemplificatively described above. It is thus learned that when the circuit substrate 200 of the present embodiment is used in the light emitting device 300, it may have four blue-light chips as the LED chips so that the light emitting device provides monochromatic light. Alternatively, it may have plural red-light chips and at least one blue-light chip (configured on the fourth die-bonding pad 227a) for providing mixed color light.
In addition, when the light emitting device 300 uses the blue chip, it may be adjusted to provide white light as needed. Particularly, in the present embodiment, one of the second LED chip 202b and the fourth LED chip 202d, taking the fourth LED chip 202d for example herein, is covered by a layer of fluorescent powder. Therein, the fluorescent powder layer may be made of yellow fluorescent powder or other suitable colors of fluorescent powder. The preferable fluorescent powder is as described in the first aspect. The fluorescent powder layer is laid on the fourth LED chip 202d, so that the blue light emitted by the fourth LED chip 202d is mixed in the fluorescent powder layer before emitted, so as to provide white light. Moreover, the light emitting device 300 comprises circular sub retaining wall 306, which circles the LED chip covered by the fluorescent powder layer, namely the fourth LED chip 202d. The circular sub retaining wall 306 comprises a reflective material. The purpose of the circular sub retaining wall 306 is to prevent laying of the fluorescent powder layer from affecting the other LED chips. That is, the circular sub retaining wall 306 prevents the fluorescent powder layer from overflowing to any LED chips other than the fourth LED chip 202d. In addition, the reflective material it contains helps to collecting the light emitted by the fourth LED chip 202d. However, the present disclosure puts no limitation to whether the fluorescent powder layer and the circular sub retaining wall 306 are included, and use of these components may be decided according to practical needs.
Moreover, based on the light emitting device 300, the scheme for modulating voltage drops as described in the first or second aspect may be further adopted. In particular, bonding adhesive is provided between the LED chips and the corresponding die-bonding pads to change the voltage drops of the LED chips. Specifically, in the embodiment of
The above description merely reflects one possible aspect of the present disclosure, and the present disclosure is not limited to using the modulating scheme in the foregoing light emitting device 300. To state clearly, use of the design of the circuit substrate described in the present aspect shall be also within the scope of the present disclosure.
With the configuration stated above, the circuit substrate 200 and the light emitting device 300 of the present embodiment are suitable for providing plural sets of electric loops L1 through L3 having integrated configuration of polarity, so as to simplify circuit configuration of a circuit mainboard at the users' side. This eliminates the needs of jumper wires and multilayer circuit structure. One or more LED chips may be connected thereto, and the chips may be red-light chips or blue-light chips according to practical needs, so that the light emitting device 300 emits monochromatic light or mixed color light as a combination of rays of various bands. Thereby, work circuits having the same voltage drop can be achieved using a simple combination, and this in turn allows use of a single external power source to perform control.
The above description explains the spirit and principle of the scheme for modulating voltage drops by referring to the third aspect of the present disclosure, and more aspects will be further provided below.
Particularly, in the present embodiment, the first pattern 220a further comprises an extended pad 229 configured on the first surface 212. The extended pad 229 is adjacent to one lateral of the first die-bonding pad 221a and electrically connected to the third matching pad 225b. Furthermore, the extended pad 229 passes through a division located between the second die-bonding pad 223a and the third die-bonding pad 225a. Thereby, the extended pad 229 is connected to the third matching pad 225b located in the third region R3 and extends from the third region R3 to the first region R1 so as to be adjacent to the first die-bonding pad 221a located in the first region R1. The second die-bonding pad 223a and the third die-bonding pad 225a may be deemed as arranged at two opposite sides of the X axis of the planar coordinate system, and separated by the extended pad 229 so as to be located at two opposite sides of the extended pad 229. The extended pad 229 may electrically connect protective elements, such as Zener diodes. However, the present disclosure puts no limitation on whether the extended pad 229 and the protective elements are included, and the use of such components may be decided according to practical needs. Particularly, the protective element may be deposited on the extended pad or the first die-bonding pad and electrically connected to the extended pad and the first die-bonding pad, thereby protecting the electric loop L1.
The pads on which the Zener diodes Z1 through Z3 are configured and the pads on which the wiring is made may be individually interchanged, as long as the equivalent electric loop is formed. In other words, the Zener diode Z1 may be configured on the first die-bonding pad 221a and wired to the extended pad 229 and electrically connected to third matching pad 225b. Alternatively, the Zener diode Z2 may be configured on the second die-bonding pad 223a, and electrically connected to the second matching pad 223b through wiring. Alternatively, the Zener diode Z3 may be configured on the fourth die-bonding pad 227a and electrically connected to fourth matching pad 227b through wiring. All these variations are within the scope of the present disclosure. Additionally, in one embodiment without the extended pad 229 (such as the embodiment depicted in
Particularly, in the present embodiment, the first pattern 220b comprises a first pad pair 221, a second pad pair 223, a third pad pair 225, a fourth pad pair 227, a communicating pad 228 and an extended pad 229. The first pad pair 221, the second pad pair 223, the third pad pair 225, and the fourth pad pair 227 are configured on the first region R1, the second region R2, the third region R3 and the fourth region R4, respectively, and each of the pad pairs comprises a die-bonding pad and a matching pad. The relative location between the die-bonding pad and the matching pad can be seen in the description of the previous embodiment. Moreover, the communicating pad 228 passes through a division located between the first die-bonding pad 221a and the fourth die-bonding pad 227a and connects the third die-bonding pad 225a located in third region R3 and the first matching pad 221b located in the first region R1. The extended pad 229 passes through a division located between the second die-bonding pad 223a and the third die-bonding pad 225a and connects the third matching pad 225b located in the third region R3 and extends to be adjacent to the first die-bonding pad 221a located in the first region R1. It is thus learned that the first pattern 220b of the present embodiment are similar to the foregoing first patterns 220 and 120a, so its structure and design may be seen in the foregoing, and no repetition is made herein.
Similarly, the second pattern 230 comprises a first electrode pair 232, a second electrode pair 234 and a third electrode pair 236. Each of the electrode pairs comprises a primary electrode and a secondary electrode. The first primary electrode 232a configured at the back of first region R1, the second primary electrode 234a configured at the back of the second region R2, and the third secondary electrode 236b configured at the back of the fourth region R4 are adjacent to each other. The first secondary electrode 232b configured at the back of the third region R3, the second secondary electrode 234b configured at the back of the second region R2, and the third primary electrode 236a configured at the back of the fourth region R4 are adjacent to each other. It is thus learned that the second pattern 230 of the present embodiment is similar to its counterparts described previously, so its structure and design may be seen in the foregoing, and no repetition is made herein.
With the configuration stated above, in the present embodiment, the circuit substrate 200b is similar to the foregoing circuit substrates 200 and 200a in terms of structure and design, with the only difference laid on how the fourth pad pair 227 located in the fourth region R4 and the third electrode pair 236 located at the back of the fourth region R4 are connected.
In detail, in the present embodiment, the first primary electrode 232a is electrically connected to the first die-bonding pad 221a located in the first region R1 through the conductive post 240a, while the first secondary electrode 232b is electrically connected to the third matching pad 225b located in the third region R3 through the conductive post 240b. Similarly, the second primary electrode 234a is electrically connected to the second die-bonding pad 223a located in the first region R1 through the conductive post 240c, while the second secondary electrode 234b is electrically connected to the second matching pad 223b located in the first region R1 through the conductive post 240d. However, while the third primary electrode 236a and the third secondary electrode 236b are located at the back of the fourth region R4 and correspond to the fourth die-bonding pad 227a and the fourth matching pad 227b, respectively, in the present embodiment, the third primary electrode 236a is not connected to the fourth die-bonding pad 227a, and the third secondary electrode 236b is not connected to the fourth matching pad 227b. Instead, in the present embodiment, the third primary electrode 236a and the fourth matching pad 227b are electrically connected through the conductive post 240e, and the third secondary electrode 236b and the fourth die-bonding pad 227a are electrically connected through the conductive post 240f. The connection may be realized by designing the fourth die-bonding pad 227a and the fourth matching pad 227b into specific geometry so that their local parts correspond to the third secondary electrode 236b and the third primary electrode 236a, respectively.
With the configuration stated above, in the present embodiment, the first die-bonding pad 221a and the first primary electrode 232a are electrically connected. The second die-bonding pad 223a and the second matching pad 223b are electrically connected and the second primary electrode 234a and the second secondary electrode 234b, respectively. The third matching pad 225b and the first secondary electrode 232b are electrically connected. The fourth die-bonding pad 227a and the fourth matching pad 227b are electrically connected to the third secondary electrode 236b and the third primary electrode 236a, respectively. The first matching pad 221b, the third die-bonding pad 225a and the communicating pad 228 connecting the first matching pad 221b and the third die-bonding pad 225a are not electrically connected to the second pattern 230 through the conductive post. Thereby, when the circuit substrate 200a is used in a light emitting device, the six conductive posts 240a through 240f have each two thereof connected to positive electricity and negative electricity so as to constitute an electric loop, so the circuit substrate 200a provides three sets of electric loops.
In detail, as shown in
Moreover, as shown in
In addition, as shown in
With the configuration stated above, in the present embodiment, as described previously, based on the diagonal extending from the upper right to the lower left parts of the second surface 214 and passing through the second region R2 and the fourth region R4, the first primary electrode 232a, the second primary electrode 234a and the third secondary electrode 236b are roughly at the upper left side of the diagonal and adjacent to each other, while the first secondary electrode 232b, the second secondary electrode 234b and the third primary electrode 236a are roughly at the lower right side of the diagonal and adjacent to each other. Therein, as shown in
Thereby, since the first primary electrode 232a, the second primary electrode 234a and the third secondary electrode 236b acting as the positive ends are located in the upper left side of the diagonal and adjacent to each other (grouped at the upper left side of the circuit substrate/the insulating base 210), and the first secondary electrode 232b, the second secondary electrode 234b and the third primary electrode 236a acting as the negative ends are located in the lower right side of the diagonal and adjacent to each other (grouped at the lower right side of the circuit substrate/the insulating base 210). Thus, connecting lead (as the connecting leads L11, L21, L31 as shown in
It is thus learned that in the present embodiment, the circuit substrate 200b is similar to the foregoing circuit substrates 200 and 200a in terms design of the second pattern 230, and when it is used in the light emitting device 300b, the second pattern 230 is electrically connected to the connecting leads in the manner as that described in the previous embodiment the. However, in the present embodiment, the fourth pad pair 227 and the third electrode pair 236 of the circuit substrate 200b are connected differently from that seen in the previous embodiment. Particularly, the fourth die-bonding pad 227a is electrically connected to the third primary electrode 236a acting as the positive end, and the fourth matching pad 227b is electrically connected to the third secondary electrode 236b acting as the negative end. Thereby, in the present embodiment, the fourth die-bonding pad 227a is electrically positive, and the fourth matching pad 227b is electrically negative. With this design, the four die-bonding pads of the circuit substrate 200b of the present embodiment are all electrically positive, while the four matching pads are all electrically negative. Thus, the four die-bonding pads of the present embodiment may freely use red-light chips and blue-light chips according to practical needs.
In detail, as described previously, the red-light chip has its positive electrode provided on the bottom, and has its negative electrode provided on the top. When the light emitting device 300b uses such a red-light chip, the red-light chip is preferably configured on the electrically positive die-bonding pad, so that the positive electrode at the bottom is directly connected to the die-bonding pad, and then the negative electrode is connected to the matching pad through wiring. Comparatively, the blue-light chip has its positive and negative electrodes both on the top, so it may be configured on a die-bonding pad of any of the polarity, and have the positive and negative electrodes connected to the die-bonding pad and the matching pad through wiring. Thereby, in the present embodiment, the light emitting device 300b may use two red-light chips and two blue-light chips as those seen in the foregoing light emitting device 300. For example, the first LED chip 202a and the third LED chip 202c are red-light chips, while the second LED chip 202b and the fourth LED chip 202d are blue-light chips. However, in other embodiments not shown herein, the circuit substrate 200b may alternatively carry four blue-light chips or four red-light chips, and the present disclosure is not limited thereto.
It is thus learned that when the circuit substrate 200b of the present embodiment is used in the light emitting device 300b, the LED chips may be four blue-light chips or four red-light chips so as to allow the light emitting device to provide monochromatic light. Alternatively, the LED chips may be a combination of red-light chips and blue-light chips to as to provide mixed color light. The amounts of the red-light chips and of the blue-light chips may vary according to practical needs, and the blue-light chip may use the fluorescent powder layer to provide white light. With the configuration stated above, the circuit substrate 200b and the light emitting device 300b of the present embodiment can provide plural electric loops L1 through L3. One or more LED chips may be connected thereto, and the chips may be red-light chips or blue-light chips according to practical needs, so that the light emitting device 300 emits monochromatic light or mixed color light as a combination of rays of various bands. Thereby, work circuits having the same voltage drop can be achieved using a simple combination, and this in turn allows use of a single external power source to perform control.
The present disclosure has been described with reference to the preferred embodiments and it is understood that the embodiments are not intended to limit the scope of the present disclosure. Moreover, as the contents disclosed herein should be readily understood and can be implemented by a person skilled in the art, all equivalent changes or modifications which do not depart from the concept of the present disclosure should be encompassed by the appended claims.
Number | Date | Country | Kind |
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104123703 | Jul 2015 | TW | national |
104127620 | Aug 2015 | TW | national |