Patent Application
20130328010
This application claims priority to Taiwan Application Serial Number 101120486, filed Jun. 7, 2012, which is herein incorporated by reference.
1. Technical Field
The present disclosure relates to a light-emitting diode (LED) and a method for manufacturing the same, and more particularly, to a high brightness LED and a method for manufacturing the same.
2. Description of Related Art
Å light-emitting diode (LED) is a photoelectric conversion device, with an n-type semiconductor connected to a p-type semiconductor, which emits light by recombination of electrons and holes. Recently, the LED has been widely applied in backlight modules and the field of lighting due to having long life and a small size.
The gallium nitride (GaN) based LED is the most representative LED. The GaN-based LED includes a light-emitting cell composed of an n-type GaN layer, a multi-quantum well (MQW) layer (i.e., an active layer) and a p-type GaN layer. However, each of the aforementioned layers would absorb light emitted from the active layer, resulting in the reduction of light extraction.
Therefore, there is still a need for an improved LED and a method for manufacturing the same to increase the light extraction.
One aspect of the present disclosure provides a high brightness LED free of p-type gallium nitride (GaN) layer, which includes an n-type semiconductor layer, a multi-quantum well (MQW) layer, a p-type indium gallium nitride (InGaN) layer and an indium tin oxide (ITO) layer. The grain size of the ITO layer is ranging from 5 to 1,000 angstroms (Å). The n-type semiconductor layer is disposed on a substrate. The MQW layer is disposed on the n-type semiconductor layer. The p-type InGaN layer is disposed on the MQW layer. The ITO layer is disposed on the p-type InGaN layer.
Another aspect of the present disclosure provides a method for manufacturing the high brightness LED, which includes the steps below. A substrate is provided. An n-type semiconductor layer is formed on the substrate. The MQW layer is formed on the n-type semiconductor layer. The p-type InGaN layer is formed on the MQW layer. The ITO layer is formed on the p-type InGaN layer. The grain size of the ITO layer is ranging from 5 to 1,000 Å.
The disclosure may be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
The present disclosure is described by the following specific embodiments. Those with ordinary skill in the arts can readily understand the other advantages and functions of the present invention after reading the disclosure of this specification. The present disclosure can also be implemented with different embodiments. Various details described in this specification can be modified based on different viewpoints and applications without departing from the scope of the present disclosure.
As used herein, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Therefore, reference to, for example, a data sequence includes aspects having two or more such sequences, unless the context clearly indicates otherwise.
Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The n-type semiconductor layer 130 is disposed on a substrate 110. In one embodiment, the n-type semiconductor layer includes n-type gallium nitride (n-type GaN). The substrate 110 is made of glass, quartz, sapphire, silicon carbide, gallium nitride, aluminum nitride or other suitable materials. The n-type semiconductor layer 130 can be formed by performing a chemical vapor deposition (CVD) process and a doped process in sequence. The n-type semiconductor layer 130 may be III-V group semiconductor compounds, such as silicon-doped GaN compounds, but not limited thereto.
In one embodiment, the LED 100 further includes an undoped GaN (U-GaN) layer 120 interposed between the n-type semiconductor layer 130 and the substrate 110. The U-GaN layer 120 is acted as a buffer layer, and it can be formed by a CVD process.
The MQW layer 140 is disposed on the n-type semiconductor layer 130. In one embodiment, the MQW layer 140 is a structure composed of InxGa1-xN (0<x<1) layers and GaN layers interstacked with each other, and those layers can be formed by CVD processes. The MQW layer 140 is used to confine carriers in the quantum wells to enhance luminous intensity.
The p-type InGaN layer 150 is disposed on the MQW layer 140. The p-type InGaN layer 150 has a p-type dopant which is a material selected from the group consisting of beryllium (Be), magnesium (Mg) and a combination thereof. The p-type InGaN layer 150 includes a material having a general formula of p-InxGa1-xN, in which 0<x<1.In one embodiment, the p-type InGaN layer 150 has a thickness ranging from 5 to 1,000 Å, preferably ranging from 5 to 20 Å, to reduce light absorption thereof. That is, the thin p-type InGaN layer 150 helps to significantly decrease light absorption and thus increase light extraction of the LED 100.
The ITO layer 170 is disposed on the p-type InGaN layer 150, which is used to uniformly spread a current. In order to decrease light absorption of the p-type InGaN layer 150, the thickness thereof is reduced. However, the reduction of the thickness of the p-type InGaN layer 150 deteriorates its ability of uniformly spreading a current. As such, in one embodiment, the ITO layer 170 is formed by a sputtering process. The sputtering process can be carried out to form a denser ITO layer 170 having higher quality to greatly enhance the ability of uniformly spreading a current compared to an e-gun evaporation process. In one embodiment, the grain size of the ITO layer 170 is in a range of 5 to 1,000 Å. Also, in the condition of forming the ITO layer at the same thickness, the ITO layer 170 formed by the sputtering process has lower surface resistance than that formed by the e-gun process. Therefore, in one embodiment, the ITO layer 170 has a surface resistance ranging from 5 to 100 ohms/sq. In one embodiment, the ITO layer 170 has a thickness ranging from 5 to 1,000 angstroms. In other words, the thin ITO layer can reduce light absorption and exhibit enough low surface resistance and good current spreading effect. Further, a good ohmic contact between the ITO layer 170 and the p-type InGaN layer 150 is formed.
In one embodiment, the LED 100 further includes an alkaline earth metal alloy layer 160 interposed between the p-type InGaN layer 150 and the ITO layer 170, as shown in
Å p-type contacting pad 182 and an n-type contacting pad 184 are respectively disposed on the ITO layer 170 and the exposed portion of the n-type semiconductor layer 130, as shown in
In step 310, a substrate 110 is provided. In one embodiment, the method 300 further includes a step of forming a U-InGaN layer 120 on the substrate 110. The embodiments of the substrate 110 and the U-InGaN layer 120 may be the same as the embodiments of the substrate 110 and the U-InGaN layer 120 described above in connection with
In step 320, an n-type semiconductor layer 130 is formed on the substrate 110. The embodiments of the n-type semiconductor layer 130 may be the same as the embodiments of the n-type semiconductor layer 130 described above in connection with
In step 330, an MQW layer 140 is formed on the n-type semiconductor layer 130. The embodiments of the MQW layer 140 may be the same as the embodiments of the MQW layer 140 described above in connection with
In step 340, a p-type InGaN layer 150 is formed on the MQW layer 140. The p-type InGaN layer 150 may be formed by an organometallic chemical vapor deposition (OM-CVD) process, an ion implantation process or a thermal diffusion process, which are described in detail hereinafter.
In one embodiment, step 330 includes forming InGaN middle layers 142 and GaN middle layers 144 which are interstacked with each other, and then forming a top layer 146, as shown in
In another embodiment, as shown in
In further embodiment, as shown in
In step 350, the ITO layer 170 is formed on the p-type InGaN layer 150, as shown in
Sequentially, an etching process is performed to expose a portion of the n-type semiconductor layer 130, as shown in
Finally, a p-type contacting pad 182 and an n-type contacting pad 184 are respectively formed on the ITO layer 170 and the exposed portion of the n-type semiconductor layer 130, as shown in
As mentioned above, the LEDs do not include p-type GaN layers. Also, the embodiments of the present disclosure uses an ultra thin p-type InGaN layer combined the high quality ITO layer with small grain size to reduce light absorption and help spread current. Further, the high quality ITO layer can be thinned to reduce light absorption and exhibit enough low surface resistance and good current spreading effect. As such, the LEDs with high light extraction and the method for manufacturing the same can effectively solve those problems above.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those ordinarily skilled in the art that various modifications and variations may be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations thereof provided they fall within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 101120486 | Jun 2012 | TW | national |
