Patent Application
20210083145
The disclosure relates to a light emitting diode device, and more particularly to a light emitting diode device having patterned structures on a peripheral face thereof.
Group III-V compounds are the main semiconductor materials used for manufacturing light emitting diode (LED) devices, and among such compounds, gallium nitride (GaN) and aluminum gallium indium phosphide (AlGaInP) are the most common ones.
A conventional GaN-based LED device is made by the following techniques: mesa etching (forming an n-type platform), and formation of a current block (CB) layer, a transparent conductive layer (TCL, serving as a current spreading layer), pads and a passivation layer (PV). During formation of the TCL, to ensure that the wet etching of the current spreading layer (such as an indium tin oxide (ITO) layer) is conducted precisely to avoid current leakage, the ITO layer would be unavoidably overetched. Because wet etching is an isotropic etching, the edge of the ITO layer, even if pre-formed with a pattern, would still show a plain structure after wet etching (see
Therefore, an object of the disclosure is to provide an LED device that can alleviate at least one of the drawbacks of the prior art.
According to the disclosure, the LED device includes a light emitting epitaxial layered structure and a current spreading layer formed on the light emitting epitaxial layered structure. The current spreading layer has a top surface and a bottom surface that are respectively distal from and proximal to the light emitting epitaxial layered structure, and a peripheral surface that interconnects the top surface and the bottom surface and that is formed with a first patterned structure. The peripheral surface and the bottom surface cooperatively define an interior angle included therebetween which is greater than 90° and smaller than 180°.
Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiment with reference to the accompanying drawings, of which:
Before the disclosure is described in greater detail, it should be noted that where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.
Referring to
The substrate 100 may be made of a material selected from sapphire, aluminum nitride, silicon, and silicon carbide. In this embodiment, the substrate 100 is made of sapphire. The substrate 100 has a substrate surface 100a that is connected to the light emitting epitaxial layered structure 200 opposite to the current spreading layer 300, and a side surface 100b that extends peripherally from the substrate surface 100a. The substrate surface 100a may be a plain surface or a roughed surface.
The light emitting epitaxial layered structure 200 includes a first-type semiconductor layer 201 disposed on the substrate surface 100a of the substrate 100, a second-type semiconductor layer 203 spaced apart from the first-type semiconductor layer 201, and a light emitting layer 202 that is sandwiched between the first-type semiconductor layer 201 and the second-type semiconductor layer 203.
The light emitting epitaxial layered structure 200 is made of a material selected from the group consisting of a GaN-based material, a gallium phosphide-based material, a gallium nitride phosphide-based material, and a zinc oxide-based material. In this embodiment, the light emitting epitaxial layered structure 200 is made of a GaN-based material. For example, the first-type semiconductor layer 201 is an N-type semiconductor layer made of N-GaN and the second-type semiconductor layer 203 is a P-type semiconductor layer made of P-GaN. The light emitting layer 202 is an active layer including a multi-quantum well (MQW) structure made of a material selected from the group consisting of AlGaN, InAlGaN, GaN and InGaN.
The current spreading layer 300 may be made of a material selected from the group consisting of indium tin oxide (ITO), zinc oxide (ZnO), cadmium tin oxide (CTO), indium oxide (InO), zinc oxide (ZnO) doped with indium (In), zinc oxide (ZnO) doped with aluminum (Al), and zinc oxide (ZnO) doped with gallium (Ga). In this embodiment, the current spreading layer 300 is made of ITO.
The current spreading layer 300 has a top surface 301 and a bottom surface 303 that are respectively distal from and proximal to the light emitting epitaxial layered structure 200, and a peripheral surface 302 that interconnects the top surface 301 and the bottom surface 303. The peripheral surface 302 and the bottom surface 303 cooperatively define an interior angle θ included therebetween which is greater than 90° and smaller than 180°. The peripheral surface 302 is formed with a first patterned structure 500.
The N-type electrode 401 is formed on an exposed portion of the first-type semiconductor layer 201 that is not covered by the light emitting layer 202 and the second-type semiconductor layer 203. The P-type electrode 402 is formed on the top surface 301 of the current spreading layer 300.
In certain embodiments, the interior angle θ included between the peripheral surface 302 and the bottom surface 303 of the current spreading layer 300 ranges from 120° to 150°, such as 135°.
The peripheral surface 302 of the current spreading layer 300 has an inclined region 302a that is connected to the bottom surface 303 and an upper edge region 302b that is connected to the top surface 301 and the inclined region 302a. The first patterned structure 500 may be formed on one of the inclined region 302a, the upper edge region 302b, and a combination thereof. The first patterned structure 500 may have one of a wave pattern, a triangular pattern, and a step pattern.
In this embodiment, the first patterned structure 500 has a wave pattern (see
First, a silicon oxide layer is disposed on the current spreading layer 300 opposite to the light emitting epitaxial layered structure 200, and then a photoresist layer having a wave pattern on a periphery thereof partially covers the silicon oxide layer to expose a portion of the silicon oxide layer. Then, the silicon oxide layer, the current spreading layer 300 and the light emitting epitaxial layered structure 200 are subjected to a dry etching process (such as inductively coupled plasma (ICP) etching), so as to remove the exposed portion of the silicon oxide layer, as well as portions of the current spreading layer 300, the second-type semiconductor layer 203, the light emitting layer 202 and the first-type semiconductor layer 201 that are disposed below the silicon oxide layer, and to obtain the wave pattern on the upper edge region 302b of the current spreading layer 300. Then, the peripheral surface 302 of the current spreading layer 300 is subjected to a selective wet etching process using an etching solution. Since an upper portion of the current spreading layer 300 proximal to the silicon oxide layer may be etched by the etching solution at an etching rate lower than the etching rate of a bottom portion of the current spreading layer 300 distal from the silicon oxide layer, the inclined region 302a of the current spreading layer 300 is thus formed, and cooperates with the bottom surface 303 to define an obtuse angle. After the wet etching process performed on the current spreading layer 300, the silicon oxide layer and the photoresist are removed.
In certain embodiments, the light emitting epitaxial layered structure 200 has a lateral surface 200a that is formed with a second patterned structure 501, which may be formed by, for example, disposing a template having a ball pattern (such as arrays of polystyrene (PS) balls or SiO2 balls) on the lateral surface 200a and then conducting an anisotropic wet etching process thereon. The lateral surface 200a of the light emitting epitaxial layered structure 200 is defined by at least one selected from the group consisting of a lateral face of the first-type semiconductor layer 201, a lateral face of the second-type semiconductor layer 203, and a lateral face of the light emitting layer 202. That is to say, the lateral face of the first-type semiconductor layer 201, the lateral face of the second-type semiconductor layer 203 and/or the lateral face of the light emitting layer 202 may be formed with the second patterned structure 501. In this embodiment, the lateral face of the second-type semiconductor layer 203 is formed with the second patterned structure 501. The second patterned structure 501 may have one of a wave pattern, a triangular pattern, and a step pattern. In this embodiment, the first patterned structure 500 and the second patterned structure 501 has a same pattern, i.e., a wave pattern.
Referring to
Referring to
In this way, a total area of the first patterned structure 500 on the peripheral surface 302 may be increased so that more light can be extracted from the peripheral surface 302 of the current spreading layer 300.
Referring to
Referring to
In conclusion, the LED device of this disclosure has the following advantages.
First, by controlling the interior angle θ defined between the peripheral surface 302 and the bottom surface 303 of the current spreading layer 300 to be greater than 90° and smaller than 180°, an light-exit angle may be varied and an area of the peripheral surface for light exiting therefrom is increased. Therefore, the light emitted from the light emitting layer 202 may easily exit from the LED device (rather than being confined within the LED device which causes an optical loss), so as to increase a light extraction efficiency of the LED device.
Second, by forming the first patterned structure 500 on the peripheral surface 302 of the current spreading layer 300, or further forming the second and the third patterned structures 501, 502 respectively on the lateral surface 200a of the light emitting epitaxial layered structure 200 and the side surface 100b of the substrate 100, the total internal reflection of light within the LED device may be reduced or even eliminated, and thus more light may exit from the peripheral face of the LED device in an efficient manner, thereby improving the light extraction efficiency of the LED device.
In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent, however, to one skilled in the art, that one or more other embodiment may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects, and that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure.
While the disclosure has been described in connection with what are considered the exemplary embodiments, it is understood that this disclosure is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201821012260.0 | Jun 2018 | CN | national |
This application is a continuation-in-part (CIP) of International Application No. PCT/CN2019/072025, filed on Jan. 16, 2019, which claims priority of Chinese Utility Model Patent Application No. 201821012260.0, filed on Jun. 28, 2018. The entire content of each of the international and Chinese patent applications is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2019/072025 | Jan 2019 | US |
| Child | 17105294 | US |
