LIGHT-EMITTING DIODE WITH CURRENT-SPREADING REGION

Abstract

A light-emitting diode (LED) device is provided. The LED device has a lower LED layer and an upper LED layer with a light-emitting layer interposed therebetween. A current blocking layer is formed in the upper LED layer such that current passing between an electrode contacting the upper LED layer flows around the current blocking layer. When the current blocking layer is positioned between the electrode and the light-emitting layer, the light emitted by the light-emitting layer is not blocked by the electrode and the light efficiency is increased. The current blocking layer may be formed by converting a portion of the upper LED layer into a resistive region. In an embodiment, ions such as magnesium, carbon, or silicon are implanted into the upper LED layer to form the current blocking layer.

Description

TECHNICAL FIELD

This invention relates generally to semiconductor devices and, more particularly, to crystalline group light-emitting diodes.

BACKGROUND

Light-emitting diodes (LEDs) are manufactured by forming active regions on a substrate and by depositing various conductive and semiconductive layers on the substrate. The radiative recombination of electron-hole pairs can be used for the generation of electromagnetic radiation (e.g., light) by the electric current in a p-n junction. In a forward-biased p-n junction fabricated from a direct band gap material, such as GaAs or GaN, the recombination of the electron-hole pairs injected into the depletion region causes the emission of electromagnetic radiation. The electromagnetic radiation may be in the visible range or may be in a non-visible range. Different color LEDs may be created by using materials with different band gaps. Further, an LED emitting electromagnetic radiation at a particular wavelength range may direct the radiation towards a phosphor that absorbs the radiation and emits radiation of one or more different wavelengths. So, for example, an LED emitting non-visible light may direct that light toward a phosphor that transforms the non-visible light into visible light.

Generally, LED structures have a light-emitting layer interposed between a lower layer and an upper layer, wherein the upper layer and the lower layer have opposite types of conductivity. Electrodes are formed to contact the lower and the upper layers. Current flowing from between the electrodes and the light-emitting layer takes the least electrically resistive path. In many configurations in which the upper electrode is positioned directly above the light-emitting layer, much of the light emitted by the light-emitting layer is blocked by the upper electrode, thereby significantly decreasing the light efficiency of the LED structure.

One attempt to limit the light-blocking effect of the upper electrode to increase the light efficiency of the LED structure involves forming a dielectric layer on a portion of the light-emitting layer prior to the forming of the upper layer. The upper electrode is positioned over the dielectric layer such that current flowing between the upper electrode and the lower layer of the LED structure are forced around the dielectric layer. As a result, the current flows between the upper layer and the lower layer at locations not directly under the upper electrode, thereby limiting the amount of light blocked by the upper electrode and increasing the light efficiency of the LED structure.

The dielectric layer is typically formed by depositing and patterning a layer of silicon dioxide on the light-emitting layer. The deposition and patterning steps add additional cost and complexity to the standard LED fabrication process. Furthermore the patterning steps typically comprise an etch process that may damage the surface of the light-emitting layer and reduce its crystal quality. This damage may adversely affect the quality of the LED devices and reduce the yield.

Accordingly, there is a need for an LED device having an increased light efficiency and methods for producing such a device.

SUMMARY OF THE INVENTION

These and other problems are generally reduced, solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention, which provides light-emitting diodes (LEDs) having a planar surface.

In accordance with one aspect of the present invention, an LED device is provided. The LED device includes a substrate having an LED structure formed thereon. The LED structure includes a lower layer, a light-emitting layer, and an upper layer. A current blocking layer is formed in the upper layer such that the upper layer maintains a planar surface. The current blocking layer may be formed by, for example, implanting ions, such as magnesium, carbon, silicon, or other ions, into the upper layer to create a resistive region. Another upper layer may be formed over the upper layer after the ion implant.

In accordance with another aspect of the present invention, a method of forming an LED device is provided. The method includes providing a substrate and forming an LED structure on the substrate, wherein the LED structure includes a first layer, an active layer, and a second layer. Thereafter, a current blocking layer is formed in the second layer by, for example, forming a resistive region. The resistive region may be formed by, for example, implantation. After implanting, another layer may be formed over the second layer.

In accordance with yet another aspect of the present invention, another method of forming an LED device is provided. The method includes providing a substrate and forming an LED structure on the substrate. The LED structure may include one or more lower layers, one or more light-emitting layers, and one or more first upper layers. Ions are implanted into at least one of the one or more first upper layers to form a resistive layer. One or more second upper layers may be formed over the one or more first upper layers.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1, 2 and 3A-3B illustrate various process steps of manufacturing a light-emitting diode device in accordance with an embodiment of the present invention; and

FIGS. 4 and 5 illustrate various process steps of manufacturing a light-emitting diode device in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

Novel methods for forming light-emitting diodes (LEDs) are provided. It should be understood that steps necessary to illustrate the inventive aspects of the invention are shown, but other processes already known in the art may also be performed. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.

FIGS. 1-3 illustrate various intermediate process steps of forming a light-emitting diode (LED) device 100 with a current-blocking layer in accordance with an embodiment of the present invention. Referring first to FIG. 1, the LED device 100 is shown as including a substrate 102 with an LED structure 104 formed thereon. The substrate 102 is preferably a bulk sapphire or silicon substrate, doped or undoped. It should be noted that while embodiments of the present invention are described in the context of using a sapphire substrate, other substrates may be used. For example, other substrates commonly employed in the fabrication of LEDs, such as SiC substrates, may also be used in certain embodiments. Furthermore, substrates with various surface orientations, such as (111), (100), or (110) may be used.

The LED structure 104 may comprise any LED structure suitable for a particular application. Generally, the LED structure 104 includes a lower LED layer 110 formed over the surface of the substrate 102. Preferably, the lower LED layer 110 is formed of a group III-V compound doped with a dopant of a first conductivity type. For example, a group Ill-N compound such as n-GaN having an n-type conductivity may be used. The lower LED layer 110 of n-GaN may be formed by, for example, a selective epitaxial growth process such as a molecular-beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), or the like. Other group III-N materials that may be used include, for example, GaN, InN, AlN, In_xGa_(1−x)N, Al_xIn_yGa_(1−x−y)N, or the like. Other group III-V materials may also be used.

A light-emitting layer 112 (also sometimes referred to as an active layer) is formed on the lower LED layer 110. The light-emitting layer 112 may include a homojunction, heterojunction, single-quantum well (SQW), multiple-quantum well (MQW), or the like, structure. In an exemplary embodiment, light-emitting layer 112 comprises undoped n-type gallium indium nitride (Ga_xIn_yN_(1−x−y)). In alternative embodiments, light-emitting layer 112 includes other commonly used materials such as (Al_xIn_yGa_(1−x−y)N). In yet other embodiments, light-emitting layer 112 may be a multiple quantum well including multiple well layers (such as InGaN) and barrier layers (such as GaN) allocated in an alternating pattern. Again, the formation methods include MOCVD, MBE, HVPE, LPE, or other applicable CVD methods.

An upper LED layer 114 is disposed on the light-emitting layer 112. The upper LED layer 114 is preferably formed of a group III-N compound doped with a dopant of a second conductivity type, opposite of the first conductivity type, such as p-GaN, and may be formed by a process similar to the lower LED layer 110.

It should be noted that the above description provides a general overview of the construction of an LED structure for illustrative purposes. Other layers, such as a distributed Bragg reflector, omni-directional reflectors, buffer/nucleation layers, cladding/contact layers, or the like, may also be present as required and/or desired for a particular application. Furthermore, it should be noted that where a layer was described as a single layer, a plurality of layers may be used comprising of the same or different materials. For example, the lower and upper LED layers may each comprise one or more contact layers and one or more cladding layers, which may both be formed of the same or different materials. The structure of the LED structure may also vary depending on the type of materials used and the intended application. It is expected that many types of LED structures may be used with embodiments of the present invention.

FIG. 2 illustrates the formation of a current-blocking layer (CBL) 202 in the upper LED layer 114 in accordance with an embodiment of the present invention. The CBL 202 comprises a region formed in the upper LED layer 114, or other conductive layer/substrate formed over the LED structure 104, of a resistive material. It should be noted that the CBL 202 is positioned along the bottom of the upper LED layer 114 for illustrative purposes only. The CBL 202 may be positioned at any vertical position within the upper LED layer 114. For example, the CBL 202 may be positioned along the top surface or in the middle of the upper LED layer 114.

The region of resistive material within the CBL 202 is formed by implanting impurities into the upper LED layer 114. In an illustrative embodiment, the region of resistive material is formed by implanting magnesium ions into the upper LED layer 114. In this embodiment, a photoresist layer 204 is formed by spin-coating and patterned using photolithography techniques. The photoresist layer 204 is used to perform a selective implant into the upper LED layer 114 to form the CBL 202. In the illustrative embodiment, the CBL 202 is formed by implanting magnesium ions at a dose of about 1.times.10.sup.14 to about 1.times.10.sup.15 atoms/cm.sup.2 and at an energy of about 10 to about 100 KeV, as indicated by the arrows 208. The vertical position of the profile peak of the CBL 202, which is the point of maximum concentration of the implanted impurities within the upper LED layer 114, may be adjusted by controlling the implant energy. Other process conditions may be used. Also, other impurities, such as Si, C, or the like, that create a relatively more resistive region in the upper LED layer 114, may also be used. The CBL 202 preferably has a width of about 50 Å to about 500 μm.

FIG. 3 illustrates a top electrode 302 and a bottom electrode 304 in accordance with an embodiment of the present invention. The top electrode 302 may be formed, for example, by a self-aligned “lift-off” process wherein the top electrode 302 is deposited on the patterned photoresist layer 204 and the unwanted layer material of the photoresist layer 204 and the electrode material are then removed. The top electrode 302 provides an electrical connection to the upper LED layer 114, and the bottom electrode 304 provides an electrical connection to the lower LED layer 110. In an embodiment in which the lower LED layer 110 is n-type, then the bottom electrode 304 is preferably an ohmic contact formed of one or more layers of a metal or metal alloy, such as an alloy containing Ti/Al, Ti/Au, or the like. In this embodiment, the top electrode 302 makes ohmic contact with the p-type upper LED layer 114 and may be formed of one or more layers of a metal or metal alloy, such as an alloy containing Ni/Au or the like.

One of ordinary skill in the art will appreciate that the top electrode 302 is positioned above the CBL 202. Without the CBL 202, the current flowing from the top electrode 302 through the light-emitting layer 112 to the lower LED layer 110 is a substantially direct route. As a result, much of the light emitted by the light-emitting layer 112 is blocked by the top electrode 302, greatly reducing the light-emitting efficiency of the LED device. By placing the top electrode 302 above the CBL 202, the current that would normally flow along the most direct route between the top electrode 302 and the lower LED layer 110 is forced around the CBL 202 as indicated by the dotted lines of FIG. 3. As the current flows between the upper LED layer 114 and the lower LED layer 110, the light emitted by the light-emitting layer 112 is not substantially blocked by the top electrode 302.

FIGS. 4 and 5 illustrate a method of forming an LED device 400 in accordance with another embodiment of the present invention. FIG. 4 comprises substantially the same layers and may be formed using similar processes and materials as the LED device 100 discussed above with reference to FIGS. 1 and 2, except that the upper LED layer (114 in FIGS. 1-3) is replaced by a first upper LED layer 402. The first upper LED layer 402 of FIG. 4 is formed having a thickness less than the desired final thickness of the upper LED layer 114 of FIGS. 1-3.

For the previously described embodiments exemplified in FIGS. 1-3, it has been found that the implant process used to form the CBL 202 may damage the surface of the upper LED layer 114. It has also been found that the formation and removal of the photoresist layer 204 may also damage the surface of the upper LED layer 114. In some cases the damage to the surface of the upper LED layer 114 may adversely affect the formation of and the electrical contact with overlying layers, such as the top electrode 302, and possibly adversely affect the performance and reliability of the LED device. In embodiments in which the damage to the surface of the upper LED layer 114 is greater than desired for a particular application, it is preferred that the upper LED layer 114 is formed to have a thickness less than a desired thickness, as illustrated by the first upper LED layer 402 of FIG. 4. The CBL 202 is formed in the first upper LED layer 402 by implanting magnesium ions as illustrated by arrows 208. The CBL 202 may be formed in a similar manner as discussed above with reference to FIG. 2. An activation anneal may be performed before or after formation of the CBL 202.

FIG. 5 illustrates the LED device 400 after a second upper LED layer 502 is formed over the first upper LED layer 402 in accordance with an embodiment of the present invention. The second upper LED layer 502 may be formed of the same materials using similar processes as those used for the first upper LED layer 402. The second upper LED layer 502 is formed to a thickness such that the combined thickness of the first upper LED layer 402 and the second upper LED layer 502 is about 1000 .ANG. to about 3000 .ANG., but the second upper LED layer 502 preferably has a thickness of about 300 .ANG. to about 2700 .ANG..

One of ordinary skill in the art will realize that by forming the second upper LED layer 502 over the first upper LED layer 402, surface damage to the first upper LED layer 402 is repaired, thereby providing a better surface for forming overlying layers and making electrical contacts.

Thereafter, processes may be performed to complete the LED device 400. Including, for example, forming the top electrode 302 and the bottom electrode 304 as illustrated in FIG. 3. The operation to the LED device 400 is similar to the operation of the LED device 100 discussed above with reference to FIG. 3.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A lighting apparatus, comprising: a substrate;a first semiconductor layer located over the substrate;a light-emitting layer located over the first semiconductor layer;a second semiconductor layer located over the light-emitting layer;a resistive element embedded within the second semiconductor layer; anda conductive element located over the second semiconductor layer, wherein the conductive element vertically blocks the resistive element.

2. The lighting apparatus of claim 1, wherein the resistive element contains impurities.

3. The lighting apparatus of claim 2, wherein the impurities include silicon, carbon, or magnesium.

4. The lighting apparatus of claim 1, wherein a lateral dimension of the resistive element is in a range from about 50 angstroms to about 500 microns.

5. The lighting apparatus of claim 1, wherein the resistive element is embedded near a bottom surface of the second semiconductor layer.

6. The lighting apparatus of claim 1, wherein: the first semiconductor layer contains a first group III-V compound;the second semiconductor layer contains a second group III-V compound; andthe first group III-V compound and the second group III-V compound have different types of conductivity.

7. The lighting apparatus of claim 1, wherein the conductive element is a first conductive element and is electrically connected to the second semiconductor layer, and wherein the lighting apparatus further comprises a second conductive element that is located over, and electrically connected to, the first semiconductor layer.

8. The lighting apparatus of claim 1, wherein the first and second conductive elements each contain titanium, aluminum, gold, or nickel, or alloys thereof.

9. The lighting apparatus of claim 1, wherein the substrate is a silicon substrate, a sapphire substrate, or a silicon carbide substrate.

10. A lighting apparatus, comprising: a substrate, wherein the substrate contains silicon, silicon carbide, or sapphire;a first doped group III-V compound layer formed over the substrate;a multiple quantum well (MQW) layer formed over the first doped group III-V compound layer;a second doped group III-V compound layer formed over the MQW layer, wherein the first and second doped group III-V compound layers have different types of conductivity;a first electrode formed over, and electrically coupled to, the first doped group III-V compound layer;a second electrode formed over, and electrically coupled to, the second doped group III-V compound layer; anda current-blocking layer formed within the second doped group III-V compound layer, wherein the current-blocking layer is located below, and vertically aligned with, the first electrode.

11. The lighting apparatus of claim 10, wherein the current-blocking layer contains implanted impurities and has a width ranging from about 50 angstroms to about 500 microns.

12. The lighting apparatus of claim 10, wherein the implanted impurities include silicon, carbon, or magnesium.

13. A method of fabricating a lighting apparatus, comprising: growing a first semiconductor layer over a substrate;growing a light-emitting layer over the first semiconductor layer;growing a second semiconductor layer over the light-emitting layer;implanting impurities in the second semiconductor layer, thereby forming a resistive element embedded within the second semiconductor layer; andforming a conductive element over the second semiconductor layer, wherein the conductive element is formed to vertically block the resistive element.

14. The method of claim 13, wherein the implanting comprises implanting one of the following impurities: silicon, carbon, or magnesium.

15. The method of claim 13, wherein the implanting is performed such that a lateral dimension of the resistive element is in a range from about 50 angstroms to about 500 microns.

16. The method of claim 13, further comprising, before the implanting: forming a photoresist mask over the second semiconductor layer, the photoresist mask including an opening, wherein the implanting comprises implanting the impurities through the opening.

17. The method of claim 13, wherein the forming of the conductive element comprises a self-aligned lift-off process.

18. The method of claim 13, wherein: the first semiconductor layer contains a first group III-V compound;the second semiconductor layer contains a second group III-V compound; andthe first group III-V compound and the second group III-V compound have different types of conductivity.

19. The method of claim 13, wherein the substrate is a silicon substrate, a sapphire substrate, or a silicon carbide substrate.

20. The method of claim 13, further comprising: forming a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer and the second semiconductor layer have the same material composition.