Patent Grant
11842693
This application claims the priority of Korean Patent Application No. 10-2021-0105687, filed on Aug. 10, 2021, which is hereby incorporated by reference in its entirety.
The present disclosure relates to a light-emitting display device(apparatus) and a driving method thereof.
With the development of information technology, the market for display devices, which are connection media between users and information, has been growing. Accordingly, there has been an increase in use of display devices such as a light-emitting display device (LED), a quantum dot display device (QDD), and a liquid crystal display device (LCD).
The display devices described above each include a display panel including subpixels, a driving circuit configured to output a driving signal for driving the display panel, a power supply circuit configured to generate power to be supplied to the display panel or the driving circuit, etc.
In each of the display devices, when a driving signal, for example, a scan signal, a data signal, etc. is supplied to the subpixels formed in the display panel, an image may be displayed by a selected subpixel transmitting light or directly emitting light.
Accordingly, the present disclosure is directed to a light-emitting display device (apparatus) and a driving method thereof that substantially obviate one or more problems due to limitations and disadvantages of the conventional art.
More specifically, the present disclosure is to minimize an influence of coupling by a mux signal to prevent data voltage fluctuation or luminance fluctuation, relieve a black floating defect that may occur during driving in a low gradation area, and minimize luminance deviation between a linear portion and a deformed portion when applied to a deformed display panel.
Additional advantages, objects, and features of the disclosure will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the disclosure. The objectives and other advantages of the disclosure may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a light-emitting display device includes a display panel configured to display an image, a data driving circuit configured to apply a data voltage to the display panel, and a signal applying circuit configured to apply a data voltage output from a first channel of the data driving circuit to one of at least two data lines disposed on the display panel, in which the signal applying circuit includes a compensation circuit configured to prevent a data voltage increase due to signal coupling when the data voltage output from the first channel is applied to one of the at least two data lines.
The compensation circuit may include a transistor having a first electrode and a second electrode connected to a data line for transmitting the data voltage and a gate electrode connected to a compensation signal line to which a compensation signal is applied.
The compensation circuit may include a capacitor having a first electrode connected to a data line for transmitting the data voltage and a second electrode connected to a compensation signal line to which a compensation signal is applied.
The compensation circuit may be disposed close to the signal applying circuit.
The compensation circuit may be disposed between the signal applying circuit and a display area of the display panel.
The transistor may operate opposite to a mux switch included to apply the data voltage in the signal applying circuit.
When the mux switch is turned on in response to a logic-high mux signal to apply the data voltage, the transistor may be turned off in response to a logic-low compensation signal, and when the mux switch is turned off in response to a logic-low mux signal not to apply the data voltage, the transistor may be turned on in response to a logic-high compensation signal.
The compensation signal may be configured in a form opposite to a form of the mux signal, and may be applied in a form that a rising edge, a falling edge, or the rising edge and the falling edge are delayed or advanced.
A compensation signal in a pulse form or a DC form may be applied to the compensation signal line.
In another aspect of the present disclosure, a driving method of a light-emitting display device includes a display panel configured to display an image, a data driving circuit configured to apply a data voltage to the display panel, a signal applying circuit configured to apply a data voltage output from a first channel of the data driving circuit to one of at least two data lines disposed on the display panel, and a compensation circuit configured to prevent a data voltage increase due to signal coupling when the data voltage output from the first channel is applied to one of the at least two data lines. The driving method of the light-emitting display device includes applying a mux signal to the signal applying circuit to apply the data voltage, and applying a compensation signal to the compensation circuit to prevent data voltage increase due to signal coupling when the data voltage output from the first channel is applied to one of the at least two data lines.
The compensation signal may be configured in a form opposite to a form of the mux signal and may be applied.
The compensation signal may be configured in a form opposite to a form of the mux signal, and may be applied in a form that a rising edge, a falling edge, or the rising edge and the falling edge are delayed or advanced.
It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate aspect(s) of the disclosure and together with the description serve to explain the principle of the disclosure.
In the drawings:
Reference will now be made in detail to the aspects of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
A display device (or a display apparatus) according to the present disclosure may be implemented as a television, a video player, a personal computer (PC), a home theater, an automobile electric device, a smartphone, etc., but is not limited thereto. The display device according to the present disclosure may be implemented as an LED, a QDD, an LCD, etc. However, hereinafter, for convenience of description, a light-emitting display device that directly emits light based on an inorganic light-emitting diode or an organic light-emitting diode will be given as an example.
As illustrated in
The image supply part (set or host system) 110 may output various driving signals along with a data signal supplied from the outside or a data signal stored in an internal memory. The image supply part 110 may supply a data signal and various driving signals to the timing controller 120.
The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the scan driving part 130, a data timing control signal DDC for controlling the operation timing of the data driving part 140, various synchronization signals (Vsync, which is a vertical synchronization signal, and Hsync, which is a horizontal synchronization signal), etc. The timing controller 120 may supply a data signal DATA supplied from the image supply part 110 together with the data timing control signal DDC to the data driving part 140. The timing controller 120 may be formed as an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.
The scan driving part 130 may output a scan signal (or a scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driving part 130 may supply a scan signal to subpixels included in the display panel 150 through gate lines GL1 to GLm. The scan driving part 130 may be formed as an IC or may be formed directly on the display panel 150 in a gate-in-panel method, but is not limited thereto.
The data driving part 140 may sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert a digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driving part 140 may supply a data voltage to the subpixels included in the display panel 150 through data lines DL1 to DLn. The data driving part 140 may be formed as an IC and mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.
The power supply part 180 may generate first power having a high potential and second power having a low potential based on an external input voltage supplied from the outside, and output the first power and the second power through a first power line EVDD and a second power line EVSS. The power supply part 180 may generate a voltage necessary to drive the scan driving part 130 (for example, a gate voltage including a gate high voltage and a gate low voltage) or a voltage necessary to drive the data driving part 140 (a drain voltage including a drain voltage and a half-drain voltage) in addition to the first power and the second power.
The display panel 150 may display an image in response to a driving signal including a scan signal and a data voltage, first power, second power, etc. The subpixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, polyimide, etc. In addition, the subpixels that emit light may include pixels including red, green, and blue or pixels including red, green, blue, and white.
For example, one subpixel SP may be connected to the first data line DL1, the first gate line GL1, the first power line EVDD, and the second power line EVSS, and may include a pixel circuit having a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode (OLED), etc. Since the subpixel SP used in the light-emitting display device directly emits light, a circuit configuration is complicated. In addition, there are various compensation circuits for compensating for deterioration of the OLED that emits light as well as the driving transistor that supplies a driving current to the OLED. Accordingly, note that the subpixel SP is simply illustrated in the form of a block.
Meanwhile, in the above description, the timing controller 120, the scan driving part 130, the data driving part 140, etc. have been described as individual elements. However, depending on the implementation method of the light-emitting display device, one or more of the timing controller 120, the scan driving part 130, and the data driving part 140 may be integrated into one IC.
As illustrated in
The scan driving parts 130a and 130b are illustrated and described as being disposed in the non-display area NA located on the left and right sides or upper and lower sides of a display area AA. However, the scan driving parts 130a and 130b may be disposed on one side of the left side, right side, upper side, or lower side.
As illustrated in
The shift register 131 may operate based on the signals Clks and Vst output from the level shifter 135, and output scan signals Scan[1] to Scan[m] capable of turning on or off a transistor formed on the display panel. The shift register 131 may be formed as a thin film on the display panel using a gate-in-panel method. Accordingly, the parts 130a and 130b formed on the non-display area NA of the display panel 150 illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
The first switching transistor T1 may transfer a data voltage applied through the first data line DL1 to one end of the storage capacitor Cst in response to a first scan signal applied through a first scan line SCAN1.
The second switching transistor T2 may electrically connect a gate electrode and a second electrode of the driving transistor DT to each other (putting DT into a diode connection state for threshold voltage compensation) in response to a second scan signal applied through a second scan line SCAN2.
The third switching transistor T3 may transfer a reference voltage (an initialization voltage or a compensation voltage) applied through a reference line VREF to one end of the storage capacitor Cst in response to an emission control signal (or a third scan signal) applied through an emission control line (or a third scan line) EM.
The fourth switching transistor T4 may transfer a driving current generated from the driving transistor DT to an anode electrode of the light-emitting diode OLED in response to an emission control signal applied through the emission control line EM.
The storage capacitor Cst may store a data voltage and drive the driving transistor DT based on the stored data voltage. The light-emitting diode OLED may emit light based on a driving current generated from the driving transistor DT.
The subpixel illustrated in
Meanwhile, in
As illustrated in
The first mux switch M1 to the fourth mux switch M4 may be turned on or off in response to a first mux signal and a second mux signal applied through a first mux signal line MUX1 and a second mux signal line MUX2. The first mux switch M1 and the third mux switch M3 may be simultaneously turned on or off in response to the first mux signal, and the second mux switch M2 and the fourth mux switch M4 may be simultaneously turned on or off in response to the second mux signal.
In the demultiplexer 145 according to the experimental example, when a logic-high first mux signal is applied, data voltages output from a first channel CH1 and a second channel CH2 of the data driving part 140 may be applied to a first subpixel SP1 and a second subpixel SP2 through the first data line DL1 and the third data line DL3. As can be seen with reference to
Incidentally, the first mux signal line MUX1 transmitting the first mux signal and the second mux signal line MUX2 transmitting the second mux signal are disposed to intersect the data lines DL1 to DL4. For this reason, it has been found that the data voltage is affected by signal coupling with the mux signal whenever the first mux signal or the second mux signal is generated as logic high.
In addition, when the demultiplexer 145 according to the experimental example illustrated in
The deformed display panel 150 may include an A-th data line DLA having a first length across the display area AA and a B-th data line DLB having a second length shorter than the first length. The A-th data line DLA having the first length is disposed in a linear shape, and thus may be referred to as a linear portion INA, and the B-th data line DLB having the second length is disposed in a deformed (or non-linear) shape, and thus may be referred to as a deformed portion (or non-linear portion) INB.
As such, the deformed display panel 150 may include data lines having different lengths in the display area AA. In order to solve a problem caused by the difference in length between the data lines, deviation compensation that matches both conditions may be performed based on a line capacitor or a line resistor.
However, even the deviation compensation is performed, if the data voltage Vdata is affected by signal coupling with the mux signal MUX1, as illustrated in
In addition, as illustrated in
As illustrated in
The first transistor S1 to the fourth transistor S4 may be disposed adjacent to the first mux switch M1 to the fourth mux switch M4 for coupling compensation. As an example, the transistors S1 to S4 may be disposed between the data driving part 130 and the mux switches M1 to M4. As another example, the transistors S1 to S4 may be disposed between the mux switches M1 to M4 and subpixels SP1 to SP4. The transistors S1 to S4 may be disposed between the MUX switches M1 to M4 and the display area AA for efficient coupling compensation. However, the present disclosure is not limited thereto.
The first mux switch M1 to the fourth mux switch M4 may be turned on or off in response to a first mux signal and a second mux signal applied through a first mux signal line MUX1 and a second mux signal line MUX2. The first mux switch M1 and the third mux switch M3 may be simultaneously turned on or off in response to the first mux signal, and the second mux switch M2 and the fourth mux switch M4 may be simultaneously turned on or off in response to the second mux signal. The first transistor S1 to the fourth transistor S4 may be turned on or off in response to a compensation signal applied through a compensation signal line MUXP. The first transistor S1 to the fourth transistor S4 may be simultaneously turned on or off in response to the compensation signal.
The first mux switch M1 may have a first electrode connected to the first channel CH1 of the data driving part 140, a second electrode connected to the first data line DL1, and a gate electrode connected to the first mux signal line MUX1. The second mux switch M2 may have a first electrode connected to the first channel CH1 of the data driving part 140, a second electrode connected to the second data line DL2, and a gate electrode connected to the second mux signal line MUX2. The third mux switch M3 may have a first electrode connected to the second channel CH2 of the data driving part 140, a second electrode connected to the third data line DL3, and a gate electrode connected to the first mux signal line MUX1. The fourth mux switch M4 may have a first electrode connected to the second channel CH2 of the data driving part 140, a second electrode connected to the fourth data line DL4, and a gate electrode connected to the second mux signal line MUX2.
The first transistor S1 may have a first electrode and a second electrode connected to the first data line DL1 and a gate electrode connected to the compensation signal line MUXP. The second transistor S2 may have a first electrode and a second electrode connected to the second data line DL2 and a gate electrode connected to the compensation signal line MUXP. The third transistor S3 may have a first electrode and a second electrode connected to the third data line DL3 and a gate electrode connected to the compensation signal line MUXP. The fourth transistor S4 may have a first electrode and a second electrode connected to the fourth data line DL4 and a gate electrode connected to the compensation signal line MUXP.
The first mux signal line MUX1 transmitting the first mux signal and the second mux signal line MUX2 transmitting the second mux signal are disposed to intersect the data lines DL1 to DL4. In addition, the compensation signal line MUXP that transmits the compensation signal is disposed to intersect the data lines DL1 to DL4.
As illustrated in
The first transistor S1 to the fourth transistor S4 are formed as thin film transistors on the display panel, and thus have parasitic capacitors. The parasitic capacitors included in the first transistor S1 to the fourth transistor S4 may be charged with the compensation signal MUXP before the first and third mux switches M1 and M3 or the second and fourth mux switches M2 and M4 are turned on. Thereafter, the parasitic capacitors included in the first transistor S1 to the fourth transistor S4 may maintain charged states when the first and third mux switches M1 and M3 or the second and fourth mux switches M2 and M4 are turned on, and such an operation may be repeated.
As such, when the first transistor S1 to the fourth transistor S4 are connected to the data lines DL1 to DL4, and the parasitic capacitors included therein are charged, the data lines are relatively stabilized, and thus a coupling phenomenon caused by the MUX signal may be minimized. For this reason, even when the logic-high first mux signal MUX1 is applied, the data voltage Vdata applied to the linear portion INA and the deformed portion INB does not increase, and is maintained close to the input data voltage Vdata (see INA′ & INB′). This phenomenon may be confirmed from a simulation result of
In addition, since an increase in the data voltage Vdata applied to the linear portion INA and the deformed portion INB is prevented (an increase in the luminance of the light-emitting diode is prevented), it is possible to relieve the black floating (a phenomenon in which it becomes brighter than desired black color) defect in the low gradation area. This may be confirmed from a simulation result of
As illustrated in
In addition, the compensation signal MUXP may be implemented by using the first mux signal MUX1 and in the form of inverting the signal using an inverter and varying at least one part of the signal using an inverter and a delayer.
As illustrated in
The first capacitor C1 to the fourth capacitor C4 may be disposed close to the first mux switch M1 to the fourth mux switch M4 for signal coupling compensation. As an example, the capacitors C1 to C4 may be disposed between the data driving part 130 and the mux switches M1 to M4. As another example, the capacitors C1 to C4 may be disposed between the mux switches M1 to M4 and the subpixels SP1 to SP4. The capacitors C1 to C4 may be disposed between the mux switches M1 to M4 and the display area AA for efficient coupling compensation. However, the present disclosure is not limited thereto.
The first mux switch M1 to the fourth mux switch M4 may be turned on or off in response to the first mux signal and the second mux signal applied through the first mux signal line MUX1 and the second mux signal line MUX2. The first mux switch M1 and the third mux switch M3 may be simultaneously turned on or off in response to the first mux signal, and the second mux switch M2 and the fourth mux switch M4 may be simultaneously turned on or off in response to the second mux signal.
The first capacitor C1 may have a first electrode connected to the first data line DL1 and a second electrode connected to the compensation signal line MUXP. The second capacitor C2 may have a first electrode connected to the second data line DL2 and a second electrode connected to the compensation signal line MUXP. The third capacitor C3 may have a first electrode connected to the third data line DL3 and a second electrode connected to the compensation signal line MUXP. The fourth capacitor C4 may have a first electrode connected to the fourth data line DL4 and a second electrode connected to the compensation signal line MUXP.
The first capacitor C1 to the fourth capacitor C4 may maintain a charged state at a specific voltage or may be charged or discharged in response to a compensation signal applied through the compensation signal line MUXP. To this end, the compensation signal may be applied in the same pulse form (pulse voltage) as in the first aspect or may be applied in a DC form (direct voltage).
The first mux signal line MUX1 transmitting the first mux signal and the second mux signal line MUX2 transmitting the second mux signal are disposed to intersect the data lines DL1 to DL4. In addition, the compensation signal line MUXP that transmits the compensation signal is disposed to intersect the data lines DL1 to DL4.
The first capacitor C1 to the fourth capacitor C4 may maintain a charged state or may be charged or discharged in response to a compensation signal applied through the compensation signal line MUXP. In addition, since the data lines have relatively stable states due to the capacitors C1 to C4, a coupling phenomenon caused by the MUX signal may be minimized.
Meanwhile, in the description of the present disclosure, a 1:2 demultiplexer for time-division inputting a data voltage output from the first channel to the data driving part to two data lines has been described as an example, which is merely an example, and the present disclosure may be applied to a 1:N (N being an integer greater than or equal to 2) demultiplexer.
As described above, the present disclosure has an effect of preventing a data voltage fluctuation or a luminance fluctuation by minimizing the coupling effect due to the MUX signal that may be caused when the data voltage is transmitted. In addition, the present disclosure has an effect of minimizing the increase in the data voltage due to the coupling effect, thereby relieving a black floating defect that may occur during driving in the low gradation area. In addition, when the present disclosure is applied to the deformed display panel, there is an effect of minimizing the luminance deviation between the linear portion and the deformed portion.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0105687 | Aug 2021 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20110050741 | Jeong | Mar 2011 | A1 |
| 20150156829 | Lin | Jun 2015 | A1 |
| 20160209808 | Byun | Jul 2016 | A1 |
| 20200159053 | Fujikawa | May 2020 | A1 |
| 20200193914 | Shin | Jun 2020 | A1 |
| 20210241709 | Takeuchi | Aug 2021 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20230048129 A1 | Feb 2023 | US |
