Patent Grant
7586506
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for LIGHT EMITTING DISPLAY DEVICE AND METHOD OF DRIVING THE SAME earlier filed in the Korean Intellectual Property Office on Sep. 22, 2004 and thereby duly assigned Serial No. 2004-75820.
1. Field of the Invention
The present invention pertains to a video signal processing method and a display device using the same and, more specifically, to a video signal processing method and a delta-structured display device that can be used in a small display where input video signals are rearranged for use in a delta pixel structure in a programmable logic circuit.
2. Discussion of Related Art
In general, a display device uses video signals to display predetermined images. The video signals indicate information about an image for display on a screen. Such video signals are typically input to a controller of the display device from the external device, and then transmitted to each pixel through a driving portion according to the control of the controller.
A display device generally has a stripe pixel structure or a delta pixel structure. The stripe pixel structure is a structure where pixels, each having a red pixel, a green pixel and a blue pixel are arranged in a straight line. The delta pixel structure (hereinafter, referred to as a ‘delta-structure’) is a structure where pixels, each having a red pixel, a green pixel and a blue pixel, are arranged approximately in a triangle across two lines. A delta-structure display device will be described below.
Generally, curves and moving images are more effectively and efficiently displayed on a display that uses a delta structure instead of the stripe structure. However, in order to process video signals for a delta structure display effectively, a large memory and a high-end central processing unit (CPU) are needed. This is problematical for small displays as small displays do not and can not always contain large memories or CPUs. Therefore, what is needed is a method and an apparatus for displaying video signals having a delta structure that can easily be implemented in small-sized displays.
It is therefore an object of the present invention to provide an improved method for displaying delta structure video data on a display.
It is also an object of the present invention to provide an improved display device that displays images using the delta structure.
It is further an object of the present invention to provide a method of displaying video data that can be applied to a small display that uses a delta-type structure.
It is yet another object of the present invention to provide a design for a small display that inverts and displays video signals according to a delta-type structure.
It is still an object of the present invention to provide a video signal processing method that can be applied to a small delta-structured display device absent a driver integrated circuit (IC).
It is also an object of the present invention to provide a video signal processing method capable of optimizing a driving portion in a driver IC in a delta-structure display device.
It is yet an object of the present invention to provide a delta-structure display device employing the novel video signal processing method.
These and other objects can be achieved by a method of processing a video signal for a light emitting display device that includes receiving sequentially first line video signals and second line video signals, each having a plurality of sub video signals such as a red sub video signal, a green sub video signal, and a blue sub video signal, extracting alternately one of the red sub video signals, the green sub video signals, and the blue sub video signals from at least two successive video signals of the first line video signals and storing the extracted signal into a memory as the first line delta video signals, and extracting alternately one of the red sub video signals, the green sub video signals, and the blue sub video signals from at least two successive video signals of the second line video signals and storing the extracted signal into the memory as the second line delta video signals.
The storing of the extracted second line delta video signals into the memory can include reading the extracted first line delta video signals from the memory followed by storing the extracted first line delta video signals into the memory. In addition, storing the extracted second line delta video signals into the memory can include reading the extracted first line delta video signals from a first region of the memory while recording the extracted first line delta video signals into a second region of the memory. In addition, the memory can include a line memory having a storage capacity of at least one horizontal line.
The method can further include sequentially providing the first line delta video signals and the second line delta video signals to a data driving portion. Here, the first line delta video signals and the second line delta video signals can be provided to the data drive circuit by delaying by a predetermined clock cycle the second line delta video signals preceded by the predetermined clock cycle to the first line delta video signals such that a start position of the second line delta video signals is aligned to a start position of the first line delta video signals.
The method can further include providing the first line delta video signals to data lines in an image display portion during a first horizontal period where first scanning signals are applied to first scanning lines, and providing the second line delta video signals to the data lines during a second horizontal period following the first horizontal period where second scanning signals are applied to second scanning lines.
The sequentially receiving the first and second line video signals can include sequentially receiving odd signals and even signals of the first line video signals and odd signals and even signals of the second line video signals, respectively, in parallel.
The extracting the first and second line delta video signals can include extracting the first and second line delta video signals from even signals of the first line video signals and odd signals of the second line video signals, respectively.
The extracting the first and second line delta video signals can include extracting the first and second line delta video signals by inverting an order of extracting the odd signals and the even signals, based on a direction of shifting signals by a shift register in a scan driver.
The extracting the first and second line delta video signals can include extracting the first and second line delta video signals by inverting an order of extracting the red sub video signal, the green sub video signal, and the blue sub video signals from the odd signals of the first line video signals and the even signals of the second line video signals, based on a data signal applying direction between a first direction extending in a scanning direction and a second direction opposite to the first direction.
Another aspect of the present invention is to provide a display device that includes a scan driver adapted to supply scanning signals to a plurality of scanning lines a data driver adapted to supply data signals to a plurality of data lines a plurality of pixels arranged in a delta, each pixel comprises a light emitting diode electrically connected to one of the scanning lines and one of the data lines and a controller adapted to control the scanning signals and the data signals supplied to the plurality of pixels, wherein the controller also being adapted to sequentially receive first line video signals and second line video signals, each having a plurality of video signals having red sub video signals, green sub video signals, and blue sub video signals, alternately extract one of the red sub video signals, the green sub video signals, and the blue sub video signals for at least two video signals of the first line video signals and stores the extracted signals into a memory as the first line delta video signals, alternately extract one of the red sub video signals, the green sub video signals, and the blue sub video signals for at least two video signals of the second line video signals and stores the extracted signals into a memory as the first line delta video signals, and sequentially supply the first line delta video signals and the second line delta video signals to the data driver. The controller can include a low voltage differential signal (LVDS) interface adapted to receive odd signals and even signals of the first line video signals and odd signals and even signals of the second line video signals, respectively, in parallel.
A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which like reference symbols indicate the same or similar components, wherein:
Turning now to the figures,
The image display portion 10 includes a plurality of scanning lines S1, S2, S3, S4, . . . , Sn-1, and Sn for transferring scanning signals, a plurality of data lines D1, D2, D3, . . . , and Dm-1, Dm for transferring data signals, and a plurality of pixels 11 electrically connected to the scanning lines and the data lines. The pixels 11 include, for example, a light emitting diode (not illustrated) and a pixel circuit (not illustrated) for controlling the light emitting diode.
The scan driver 20 supplies scanning signals to the scanning lines S1, S2, S3, S4, . . . , Sn-1, and Sn using signals output from a shift register (not illustrated). For example, the scan driving circuit 20 supplies scanning signals to each pixel 11 in a single scanning scheme or a sequential scanning scheme. The data driver 30 converts the video signals transmitted from the controller 40 into the data signals appropriate to the pixel structure, and then, sequentially supplies the data signals to data lines D1, D2, D3, . . . , Dm-1, and Dm in the image display portion 10 by each one horizontal line.
The controller 40 generates a control signal and a clock signal to control the scan driver 20 and the data driver 30. Here, the control signal includes a vertical sync signal, a horizontal sync signal, and a start pulse. In addition, the controller 40 stores the video signals to be input to a frame memory (not illustrated), etc., and supplies the video signals to the data driver 30 by each one frame. Here, the controller 40 handles the video signals as first video signals of odd horizontal lines and second video signals of even horizontal lines such that the video signals are suitable for the delta structure. For example, as illustrated in
Displaying a curve or a moving image is best accomplished using a delta-structured display device as opposed to using a stripe pixel structure. For this reason, delta-structured pixel arrangements are preferably used over a stripe-type pixel arrangement. However, the delta-structured display device requires that the input video signals conform to the delta structure, thus requiring complex manipulations of the input RGB video signals to transform them into odd horizontal lines and even horizontal lines while changing the order thereof. Therefore, a large memory and a high-speed operation device such as a CPU needs to be mounted in most delta-structured display devices. This results in an increase of the manufacturing costs of the display device and also an increase in the weight and the size of the display device.
Also, in a small display devices, a control circuit unit arranged as a programmable logic chip type such as a field programmable gate array is used instead of the high-speed operation device such as a CPU. When the small display device uses the delta structure, the small delta-structured display device needs to perform a relatively large amount of operations, but the small display device does not have a high-speed CPU operation device or a large capacity memory to effectively and efficiently process the delta structured video signals. As a result, it is difficult to apply the delta-structured display device in a small display device.
Turning now to
The image display portion 100 includes a plurality of scanning lines S1, S2, S3, S4, . . . , Sn-1, and Sn for transferring scanning signals, and a plurality of data lines D1, D2, D3, . . . , Dm-1, and Dm for transferring data signals, and a plurality of pixels 110 electrically connected to the scanning lines and data lines, respectively. Here, red, green, and blue pixels 110 arranged in two scanning lines forms a delta pixel that displays a unit pixel having a delta structure.
In the display of
The scan driver 200 uses signals output from a shift register (not illustrated) to supply scanning signals to the scanning lines S1, S2, S3, S4, . . . , Sn-1, and Sn. For example, the scan driver 200 supplies the scanning signal to each pixel 110 in any one scanning scheme among a single scanning scheme, a sequential scanning scheme, a dual scanning scheme, an interfaced scanning scheme, and other scanning schemes. Here, each scanning scheme according to the present embodiment can be appropriately adjusted and applied to be suitable for the delta structure.
The data driver 300 supplies data signals or delta video signals to each pixel 110 such that the pixels 110 arranged in the delta structure can display the predetermined images, respectively. For example, after the data driver 300 converts the video signals transferred from the controller 500 into the data signal, it sequentially supplies the data signals having an amount of one horizontal line to each data line D1, D2, D3, . . . , Dm-1, and Dm in the image display portion 100.
In addition, the data driver 300 can perform processing such as gamma correction and D/A conversion in order to convert the delta video signals into the data signals that are suitable for the image display portion. For example, as illustrated in
The shift register 310 respectively provides first and second latch enable signals for sequentially storing delta video signals (Delta RGB) in the first latch 320 and transferring them to the second latch 330 according to a clock signal HCLK and a horizontal sync signal HSYNC. Further, the first latch 320 sequentially stores the delta video signals in response to the first latch enable signal, and the second latch 330 receives the delta video signals of one horizontal line from first latch 320 according to the second enable signal of the shift register 310. Further, the DAC 340 coverts the delta video signals of one horizontal line transferred from the first latch 320 into data signals, and transmits the data signals to the image display portion 100.
Referring back to
The interface 510 receives signals by converting analog video signals input from an external source into digital video signals. On the other hand, the interface 510 can receive the digital video signals input from an external source. In addition, the interface 510 can be implemented with a low-voltage differential signaling (LVDS) interface that uses 3.3V or 1.5V that is lower than the standard 5V voltage typically used in the display device, as an electrical connection between, for example, the controller 500 and the host device (not illustrated) such as a motherboard to which the controller 500 is connected.
The timing controller 520 generates a clock signal and a control signal. Here, the control signal includes a vertical sync signal, a horizontal sync signal, and a start signal, etc. The timing controller 520 supplies the clock signal and the control signal to the video signal converter 530, the scan driver 200, and the data driver 300.
The video signal converter 530 sequentially receives the first line video signals RGB, and the second line video signals RGB, according to the clock signal from the timing controller 520. Here, the first and second line video signals include a plurality of video signals, and each video signal includes a red sub video signal, a green sub video signal, and a blue sub video signal.
The video signal converter 530 also extracts the first sub video signals from any one of the red, green, and blue sub video signals of the even signals in the first line video signals, alternately or sequentially for storage of the first sub video signals into the memory 540. Here, the first sub-video signals stored in the memory 540 form the first line delta video signals.
In addition, the video signal converter 530 extracts the second sub video signals from any one of the red, green, and blue sub video signals of the odd signals in the second line video signals following the first line video signal, alternately or sequentially for storage of the second sub video signals into the memory 540. Here, the second sub-video signals stored in the memory 540 form the second line delta video signals.
The video signal converter 530 also sequentially stores the first line delta video signals and the second line delta video signals into the memory 540 and sequentially reads them and provides them to the data driver 300. The video signal converter 530 is preferably implemented as a programmable logic chip 550 such as a field programmable gate array (FPGA).
The memory 540 is provided as a memory having a capacity where the video signals supplied to at least one horizontal line can be stored. In addition, the memory 540 can have a capacity where the video signals supplied to at least two horizontal lines can be stored to facilitate processing of the video signal. In this case, first, the memory 540 stores the first line delta video signals supplied to the first horizontal lines of the delta structure, and then reads the first line delta video signals while recording the second line delta video signals supplied to the second horizontal lines adjacent to the first horizontal lines at the same time.
In addition, when the memory 540 is provided as a programmable logic chip 550 such as the FPGA, it can be formed within the logic chip 550 along with the video signal converter 530. In this case, the memory 540 can be formed as a line memory having a storage capacity of at least horizontal line. In addition, the memory 540 can be implemented as a random access memory (RAM), a read only memory (ROM), and a video memory such as an additional high-speed memory.
In the following description, a video signal processing method in the controller 500, and in the video signal converter 530 of the controller 500 will be described in detail in conjunction with
Referring to
The controller then sequentially extracts the first sub video signals R1_4, G1_6, and B1_8 of any one of the red, green, and blue sub video signals between at least two successive video signals from the first line video signals, according to a clock signal AD_CLK (S20). Here, the video signals to be transferred to the first horizontal lines are rearranged or mapped to correspond to the first line of the delta structure. The controller then stores the first sub video signals as the first line delta video signals R1_4, G1_6, and B1_8 to be transferred to the first horizontal lines (S30). Next, the controller supplies the first line delta video signals stored in the memory to the data driver (S40).
The controller then sequentially extracts the second sub video signals R2_1, G2_3, B2_5, R2_7, and G2_9 of any one of the red, green, and blue sub video signals between at least two successive video signals from the second line video signals, according to the clock signal AD_CLK (S50). Here, the video signals to be transferred to the second horizontal lines are mapped to correspond to the second line of the delta structure. The controller then stores the second sub video signals as the second line delta video signals R2_1, G2_3, B2_5, R2_7, and G2_9 to be transferred to the second horizontal lines (S60).
The controller then supplies the second line delta video signals stored in the memory to the data driver (S70). Here, the controller supplies the second line delta video signals by delaying them as much as the predetermined clock cycle so that a start position of the second delta video signals are matched to a start position of the first line delta video signals. For example, unlike the stripe pixel structure display device, the delta-structured display device has a difference of 3 clock cycles with respect to the pixel that displays the same color. Therefore, for the delta-structured display device that supplies the same color to the same data line, when the video signals are actually mapped, the second sub video signal of the first one of the even signals are delayed as much as 3 clock cycles to allow the second sub video signal to be input to the data line to which the first sub video signal of the first one of the odd signal.
Further, the first line delta video signals and the second line delta video signals described above are alternately extracted from the respective line video signals input sequentially and mapped. In addition, the first line delta video signals and the second line delta video signals described above can be extracted from the even signals of the first line video signals and the odd signals of the second line video signals, respectively.
Further, when the memory has a storage capacity of more than two horizontal lines, the controller can use the memory in a manner that the controller records the subsequent delta video signals while storing the delta video signals of more than two horizontal lines into the memory or reading one delta video signal.
In addition, the first and second delta video signals described above can be formed such that the first and second sub video signals of the red R, green G, and blue B are sequentially extracted in a different order such as B, G, R instead of the order R, G, B.
Delta images displayed in the delta structure image display portion will now be described with reference to
Referring to
In the delta structure image display portion 100, the delta pixel 130 includes one or two pixels 110 connected to the first line and two or one pixels 110 connected to the second line. In this embodiment, the first line of the delta pixel 130 becomes the odd scanning lines S1, S3, S5, . . . , and S219, and the second line thereof becomes the even scanning lines S2, S4, . . . , and S220.
Further, the delta video signals supplied from the controller to the data driver are D/A converted or gamma corrected before being transmitted to the image display portion 100. In this case, the delta video signals are converted into the corresponding data signals and supplied from the data driver to the respective data lines.
The delta video signals slashed in
Turning now to
Referring to
For example, the first line delta video signals R1_4, G1_6, and B1_8 are extracted from the even signals of the first line video signals, and the second line delta video signals R2_1, G2_3, B2_5, R2_7, and G2_9 are extracted from the odd signals of the second line video signals.
Next, for example, since the start positions of the first and second line delta video signals have one and one half clock cycle difference viewing from the delta structure layout, the controller 500 supplies the second line delta video signals to the data driver 300 by delaying them as much as one and one half clock cycles, when the second delta video signal is supplied to the data driver 300.
Like this, when the delta-structured display device according to an embodiment of the present invention uses an LVDS interface, the image data can be processed more effectively. In addition, in the delta-structured display device according to an embodiment of the present invention, even when the screen display direction is inverted to the top and bottom and left and right, the image data can be processed much more easily.
A method of processing video signals when the screen display direction is inverted in the delta-structured display device will now be described in conjunction with
Turning now to
For the embodiment of
Turning now to
For the above embodiment of
Turning now to
For the embodiment of
In the embodiments described herein, the pixel circuit is an essential pixel circuit in a voltage-writing scheme including the drive transistor M1 and the switching transistor M2. However, the embodiments of the present invention can also be applied to a pixel circuit in a voltage-writing scheme including a transistor for compensating a threshold voltage of the drive transistor and a transistor for compensating a voltage drop other than the switching transistor and the drive transistor. Moreover, the embodiments of the present invention can be applied to a pixel circuit in a current writing scheme where data signals are supplied as data currents, as well as the pixel circuit in the voltage-writing scheme.
In addition, while the above embodiments have been described with reference to a transistor of the pixel circuit having a source, a drain, and a gate, each transistor can be arranged with a first electrode indicating a source or a drain, a second electrode indicating a drain or a source, and a gate. In other words, the MOS transistor in the pixel circuit described above is just illustrative. Therefore, the pixel circuit of the present invention can include other types of transistors besides MOS transistors. For example, the transistor can be implemented as including a first electrode, a second electrode, and a third electrode, and as an active device where a current amount flowing from the second electrode to the third electrode can be controlled by a voltage applied between the first and second electrodes.
In addition, according to the embodiments described above, the second transistor M2 of the pixel circuit is a device for switching electrodes at both sides in response to the scanning signal, and can also be implemented with various switching devices capable of performing the same function.
In addition, according to the embodiments described above, the LEDs can be formed with an electroluminescent device (EL) that can be an inorganic EL device formed with an emission layer with inorganic matter as well as an organic EL device formed with organic matter.
In addition, according to the embodiments described above, the scan driver and the data driver of the display device can be directly mounted on a glass substrate on which the image display portion is formed, and can be replaced with a drive circuit where scanning lines, data lines, and the transistor are is formed coplanar on the substrate having the image display portion thereon. On the other hand, the scan driver and/or the data driver can be provided in a chip on flexible board or a chip on film (COF). In other words, the scan driver and/or the data driver can be mounted as a flexible printed circuit (FPC) or a film attached and electrically connected to the substrate.
According to the present invention, the data driver in the driver IC adapted to the delta-structured display device can be maximized. In addition, the delta-structured display device on which the high-speed operation device is not mounted can appropriately display delta images. Further, a small electronic apparatus mounted with the delta-structured display device for displaying more natural curve or moving picture can be provided at a lower cost.
Although a few embodiments of the present invention have been illustrated and described, it would be appreciated by those skilled in the art that changes might be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2004-0075820 | Sep 2004 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5422658 | Kawaguchi et al. | Jun 1995 | A |
| 5654777 | Shin | Aug 1997 | A |
| 6404410 | Shirae | Jun 2002 | B1 |
| 6768485 | Awamoto et al. | Jul 2004 | B2 |
| 20010022565 | Kimura | Sep 2001 | A1 |
| 20030006978 | Fujiyoshi | Jan 2003 | A1 |
| 20040233185 | Hashimoto et al. | Nov 2004 | A1 |
| 20050225521 | Leo et al. | Oct 2005 | A1 |
| Number | Date | Country |
|---|---|---|
| 2003-122293 | Apr 2003 | JP |
| 1999-0033180 | May 1999 | KR |
| 10-0394886 | Aug 2003 | KR |
| Number | Date | Country | |
|---|---|---|---|
| 20060061531 A1 | Mar 2006 | US |
