Patent Grant
11257437
This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2020-0043270, filed on Apr. 9, 2020 in the Korean Intellectual Property Office (KIPO), the content of which is incorporated by reference herein in its entirety.
The present inventive concept relates to display devices, and more particularly to a light-emitting display device and pixel thereof.
A display device, such as an organic light-emitting diode (OLED) display device, may display an image at a constant frame rate (or a constant frame frequency) of about 60 Hz, or more. However, a frame rate of rendering process by a host processor (e.g., a graphics processing unit (GPU) and/or a graphics card), providing frame data to the OLED display device, may be different from the frame rate (or a refresh rate) of the OLED display device. In particular, when the host processor provides the OLED display device with frame data for a game image (gaming image), or the like, that requires complicated rendering, the frame rate mismatch may be intensified, and a tearing phenomenon may occur where a boundary line is caused by the frame rate mismatch in an image of the OLED display device.
To prevent or reduce the tearing phenomenon, a variable frame mode (e.g., Free-Sync, G-Sync, or the like) may be used in which a host processor provides frame data to an OLED display device at a variable frame rate (or a variable frame frequency) by changing a time length (or a duration of time) of a blank period in each frame period. An OLED display device supporting the variable frame mode may display an image in synchronization with the variable frame rate, thereby reducing or preventing the tearing phenomenon.
However, in an OLED display device operating in a variable frame mode, even if input image data represent a constant gray level, luminance of the OLED display device might not remain constant as the time length of the blank period is changed.
An exemplary embodiment provides a pixel of a light-emitting display device having a substantially constant luminance even if a driving frequency is changed.
An exemplary embodiment provides an organic light-emitting diode (OLED) display device capable of having substantially constant luminance even if a driving frequency is changed.
According to an exemplary embodiment, there is provided a pixel of a light-emitting display device including a capacitor having a first electrode coupled to a line of a first power supply voltage, and a second electrode coupled to a gate node, a first transistor having a gate coupled to the gate node, a first terminal, and a second terminal, a second transistor having a gate receiving a gate writing signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor, a third transistor having a gate receiving a scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node, a fourth transistor having a gate receiving a gate initialization signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of a light-emitting diode, a fifth transistor having a gate receiving a first emission signal, a first terminal coupled to the line of the first power supply voltage, and a second terminal coupled to the first terminal of the first transistor, a sixth transistor having a gate receiving a second emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light-emitting diode, and the light-emitting diode having the anode, and a cathode coupled to a line of a second power supply voltage. The scan signal and the gate writing signal are provided at a first frequency, and the first emission signal, the second emission signal and the gate initialization signal are provided at a second frequency higher than the first frequency.
In an exemplary embodiment, the first, second, fourth and fifth transistors may be P-type metal-oxide-semiconductor (PMOS) transistors, and the third and sixth transistors may be N-type metal-oxide-semiconductor (NMOS) transistors.
In an exemplary embodiment, the first, second, fourth, fifth and sixth transistors may be PMOS transistors, and the third transistor may be an NMOS transistor.
In an exemplary embodiment, the second frequency may be a fixed frequency, and the first frequency may be a variable frequency.
In an exemplary embodiment, the light-emitting diode is an organic light-emitting diode (OLED), the light-emitting display device is an OLED display device, the second frequency may correspond to a double of a maximum frequency of a variable input frame frequency of the OLED display device, and the first frequency may correspond to the second frequency divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency.
In an exemplary embodiment, the light-emitting diode is an organic light-emitting diode (OLED), the light-emitting display device is an OLED display device, a frame period of the OLED display device may include a gate and anode initialization period in which the gate node and the anode are initialized, a data writing period in which a data voltage of the data line is written to the capacitor, a first bias period in which a bias is applied to the first transistor, a first emission period in which the organic light-emitting diode emits light, an anode initialization period in which the anode is initialized, a second bias period in which the bias is applied to the first transistor, and a second emission period in which the organic light-emitting diode emits light.
In an exemplary embodiment, in the gate and anode initialization period, the first emission signal may have an off level, the second emission signal may have an on level, the gate initialization signal may have the on level, the scan signal may have the on level, the gate writing signal may have the off level, the third, fourth and sixth transistors may be turned on, the initialization voltage may be applied to the anode through the fourth transistor, and the initialization voltage may be applied to the gate node through the fourth transistor, the sixth transistor and the third transistor.
In an exemplary embodiment, in the data writing period, the first emission signal may have an off level, the second emission signal may have the off level, the gate initialization signal may have the off level, the scan signal may have an on level, the gate writing signal may have the on level, the second and third transistors may be turned on, the third transistor may diode-connect the first transistor, and the data voltage may be applied to the second electrode of the capacitor through the second transistor and the diode-connected first transistor.
In an exemplary embodiment, in the first bias period, the first emission signal may have an on level, the second emission signal may have an off level, the gate initialization signal may have the off level, the scan signal may have the off level, the gate writing signal may have the off level, the fifth transistor may be turned on, and the first power supply voltage may be applied to the first terminal of the first transistor through the fifth transistor.
In an exemplary embodiment, in each of the first emission period and the second emission period, the first emission signal may have an on level, the second emission signal may have the on level, the gate initialization signal may have an off level, the scan signal may have the off level, the gate writing signal may have the off level, the fifth and sixth transistors may be turned on, and a driving current generated by the first transistor may be provided to the organic light-emitting diode.
In an exemplary embodiment, in the anode initialization period, the first emission signal may have an off level, the second emission signal may have an on level, the gate initialization signal may have the on level, the scan signal may have the off level, the gate writing signal may have the off level, the fourth and sixth transistors may be turned on, and the initialization voltage may be applied to the anode through the fourth transistor.
In an exemplary embodiment, in the second bias period, the first emission signal may have an on level, the second emission signal may have an off level, the gate initialization signal may have the off level, the scan signal may have the off level, the gate writing signal may have the off level, the fifth transistor may be turned on, and the first power supply voltage may be applied to the first terminal of the first transistor through the fifth transistor.
According to an exemplary embodiment, there is provided an OLED display device including a display panel having a plurality of pixels, a scan driver configured to provide a scan signal, a gate writing signal and a gate initialization signal to the plurality of pixels, an emission driver configured to provide a first emission signal and a second emission signal to the plurality of pixels, and a controller configured to control the scan driver and the emission driver. Each of the plurality of pixels includes a capacitor having a first electrode coupled to a line of a first power supply voltage, and a second electrode coupled to a gate node, a first transistor having a gate coupled to the gate node, a first terminal, and a second terminal, a second transistor having a gate receiving the gate writing signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor, a third transistor having a gate receiving the scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node, a fourth transistor having a gate receiving the gate initialization signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of an organic light-emitting diode, a fifth transistor having a gate receiving the first emission signal, a first terminal coupled to the line of the first power supply voltage, and a second terminal coupled to the first terminal of the first transistor, a sixth transistor having a gate receiving the second emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light-emitting diode, and the organic light-emitting diode having the anode, and a cathode coupled to a line of a second power supply voltage. The scan driver provides the scan signal and the gate writing signal to the plurality of pixels at a first frequency, and provides the gate initialization signal to the plurality of pixels at a second frequency higher than the first frequency. The emission driver provides the first emission signal and the second emission signal to the plurality of pixels at the second frequency.
In an exemplary embodiment, the OLED display device further includes a data driver configured to provide data voltages to the plurality of pixels. The controller may control the data driver, may provide a scan start pulse and a gate writing start pulse to the scan driver at the first frequency such that the scan signal and the gate writing signal are provided at the first frequency, may provide a gate initialization start pulse to the scan driver at the second frequency such that the gate initialization signal is provided at the second frequency, and may provide a first emission start pulse and a second emission start pulse to the emission driver at the second frequency such that the first emission signal and the second emission signal are provided at the second frequency.
In an exemplary embodiment, within each frame period, the controller may provide one scan start pulse, one gate writing start pulse and at least two gate initialization start pulses to the scan driver, and may provide at least two first emission start pulses and at least two second emission start pulses to the emission driver.
In an exemplary embodiment, the second frequency may be a fixed frequency, and the first frequency may be a variable frequency.
In an exemplary embodiment, the controller may receive input image data at a variable input frame frequency from an external host processor, the second frequency may correspond to a double of a maximum frequency of the variable input frame frequency, and the first frequency may correspond to the second frequency divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency.
In an exemplary embodiment, the first, second, fourth and fifth transistors may be PMOS transistors, and the third and sixth transistors may be NMOS transistors.
In an exemplary embodiment, the first, second, fourth, fifth and sixth transistors may be PMOS transistors, and the third transistor may be an NMOS transistor.
In an exemplary embodiment, a frame period of the OLED display device may include a gate and anode initialization period in which the gate node and the anode are initialized, a data writing period in which a data voltage of the data line is written to the capacitor, a first bias period in which a bias is applied to the first transistor, a first emission period in which the organic light-emitting diode emits light, an anode initialization period in which the anode is initialized, a second bias period in which the bias is applied to the first transistor, and a second emission period in which the organic light-emitting diode emits light.
According to an exemplary embodiment, a display device includes: a display panel having a plurality of pixels; a scan driver configured to provide a scan signal to the plurality of pixels; and an emission driver configured to provide an emission signal to the plurality of pixels; wherein each of the plurality of pixels includes: a first transistor including a gate coupled to a capacitor, a first terminal, and a second terminal; a second transistor including a gate coupled to the scan driver, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; a third transistor including a gate coupled to the scan driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate of the first transistor; a fifth transistor including a gate coupled to the emission driver, a first terminal coupled to a first power line, and a second terminal coupled to the first terminal of the first transistor; and a sixth transistor including a gate coupled to the emission driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a first terminal of an emission device, wherein the scan driver provides a signal to the plurality of pixels at a first frequency; wherein the emission driver provides a signal to the plurality of pixels at a second frequency greater than the first frequency.
In an exemplary embodiment, the display device may include: a fourth transistor including a gate receiving a signal at the second frequency, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first terminal of the emission device.
In an exemplary embodiment, the first, second, fourth and fifth transistors are PMOS transistors, and at least one of the third or sixth transistors is an NMOS transistor.
In an exemplary embodiment, the second frequency is a fixed frequency, and the first frequency is a variable frequency.
In an exemplary embodiment, the emission device is an organic light-emitting diode (OLED), and the second frequency corresponds to a non-zero multiple of the first frequency.
As described above, in a pixel of an OLED display device and the OLED display device according to an exemplary embodiment, the pixel may include a capacitor, a first transistor, a second transistor having a gate receiving a gate writing signal, a third transistor having a gate receiving a scan signal, a fourth transistor having a gate receiving a gate initialization signal, a fifth transistor having a gate receiving a first emission signal, a sixth transistor having a gate receiving a second emission signal, and an OLED. The scan signal and the gate writing signal may be provided at a first frequency, and the first emission signal, the second emission signal and the gate initialization signal may be provided at a second frequency higher than the first frequency. Accordingly, in the pixel according to an exemplary embodiment, a bias may be applied to the first transistor at the (constant) second frequency, and thus an image may be displayed with substantially constant luminance at the same gray level even if the first frequency (e.g., a driving frequency or a display scan frequency) is changed.
Illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Hereinafter, embodiments of the present inventive concept will be explained in detail with reference to the accompanying drawings.
Referring to
Although an OLED emission device is shown and described, it shall be understood that alternate embodiments may employ alternate emission devices in lieu of and/or in addition to an OLED emission device, such as, for example, an inorganic light-emitting diode emission device. The exemplary embodiments provided herein are provided for ease of understanding, without limitation thereto.
The capacitor CST may store a data voltage transferred through the second transistor T2 and the first transistor T1 that is diode-connected by the third transistor T3. For example, the capacitor CST may be referred to as a storage capacitor for storing the data voltage. In an exemplary embodiment, the capacitor CST may include a first electrode coupled to a line of a first power supply voltage ELVDD, and a second electrode coupled to a gate node NG.
The first transistor T1 may generate a driving current based on a voltage of the gate node NG, or a voltage of the second electrode of the capacitor CST. For example, the first transistor T1 may be referred to as a driving transistor for generating the driving current. In an exemplary embodiment, the first transistor T1 may include a gate coupled to the gate node NG, a first terminal coupled to the second and fifth transistors T2 and T5, and a second terminal coupled to the third and sixth transistors T3 and T6.
The second transistor T2 may transfer the data voltage of a data line DL to the first terminal of the first transistor T1 in response to a gate writing signal GW. For example, the second transistor T2 may be referred to as a switching transistor for transferring the data voltage of the data line DL. In an exemplary embodiment, the second transistor T2 may include a gate receiving the gate writing signal GW, a first terminal coupled to the data line DL, and a second terminal coupled to the first terminal of the first transistor T1.
The third transistor T3 may operate as a diode-connected transistor, such as a metal-oxide semiconductor field-effect transistor (MOSFET) in a saturation region, to diode-connect the first transistor T1 in response to a scan signal SCAN. For example, the third transistor T3 may be referred to as a compensation transistor for compensating a threshold voltage of the first transistor T1. In an exemplary embodiment, the third transistor T3 may include a gate receiving the scan signal SCAN, a first terminal coupled to the second terminal of the first transistor T1, and a second terminal coupled to the gate node NG.
The fourth transistor T4 may apply an initialization voltage VINT to an anode of the organic light-emitting diode EL in response to a gate initialization signal GI. For example, the fourth transistor T4 may be referred to as an initialization transistor for initializing the anode and/or the gate node NG. In an exemplary embodiment, the fourth transistor T4 may include a gate receiving the gate initialization signal GI, a first terminal coupled to a line of the initialization voltage VINT, and a second terminal coupled to the anode of the organic light-emitting diode EL.
The fifth transistor T5 may connect the line of the first power supply voltage ELVDD to the first terminal of the first transistor T1 in response to a first emission signal EM1. For example, the fifth transistor T5 may be referred to as a first emission transistor for generating a current path from the line of the first power supply voltage ELVDD to a line of a second power supply voltage ELVSS. In an exemplary embodiment, the fifth transistor T5 may include a gate receiving the first emission signal EM1, a first terminal coupled to the line of the first power supply voltage ELVDD, and a second terminal coupled to the first terminal of the first transistor T1.
The sixth transistor T6 may connect the second terminal of the first transistor T1 to the line of the second power supply voltage ELVSS in response to a second emission signal EM2. For example, the sixth transistor T6 may be referred to as a second emission transistor for generating the current path from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS. In an exemplary embodiment, the sixth transistor T6 may include a gate receiving the second emission signal EM2, a first terminal coupled to the second terminal of the first transistor T1, and a second terminal coupled to the anode of the organic light-emitting diode EL.
The organic light-emitting diode EL may emit light based on the driving current generated by the first transistor T1 while the fifth and sixth transistors T5 and T6 are turned on. In an exemplary embodiment, the organic light-emitting diode EL may include the anode coupled to the second terminal of the sixth transistor T6, and a cathode coupled to the line of the second power supply voltage ELVSS.
In an OLED display device supporting a variable frame mode (e.g., a Free-Sync mode, a G-Sync mode, a Q-Sync mode, or the like) in which input image data are provided at a variable input frame frequency (or a variable frame rate), a driving frequency of a display panel including a plurality of pixels PX, or a display scan frequency (or a display refresh rate) at which the data voltages are written to the plurality of pixels PX may be changed according to the variable input frame frequency, and a time length of each frame period may be changed according to the driving frequency (or the display scan frequency). In a case where the driving frequency of the display panel is changed, even if the input image data represent the same gray level, luminance of the pixel PX or the display panel may be reduced (in particular, at a high gray level) by a leakage current of the transistors T1 through T6 of the pixel PX, or, in particular, by a leakage current of the transistors T3 and T6 directly or indirectly connected to the capacitor CST as the time length of each frame period increases. For example, as illustrated in
However, in the pixel PX of the OLED display device according to an exemplary embodiment as illustrated in
However, even if the third and sixth transistors T3 and T6 are implemented with the NMOS transistors, a driving characteristic of the first transistor T1 (i.e., the driving transistor) may be changed in the case where the driving frequency of the display panel is changed, and thus the luminance of the pixel PX or the display panel may be increased at the same gray level (in particular, at a low gray level) as the time length of each frame period increases. For example, as illustrated in
However, in an OLED display device according to an exemplary embodiment, in each frame period, the display scan operation that writes the data voltages to the plurality of pixels PX may be performed once, and a self-scan operation that applies the bias to the first transistors T1 of the plurality of pixels PX may be performed twice or more. In an exemplary embodiment, in each frame period, the display scan operation and the self-scan operation may be substantially simultaneously performed once, and then the self-scan operation may be additionally performed once or more. For example, when the display scan operation and the self-scan operation is substantially simultaneously performed, the gate node NG and the anode of the organic light-emitting diode EL may be initialized, the data voltage may be written to the capacitor CST, and the bias may be applied to the first transistor T1. Further, when the self-scan operation is additionally performed, the anode of the organic light-emitting diode EL may be initialized, and the bias may be applied to the first transistor T1.
To perform the display scan operation once and to perform the self-scan operation twice or more, the scan signal SCAN and the gate writing signal GW may be provided to each pixel PX at a first frequency FF1, and the first emission signal EM1, the second emission signal EM2 and the gate initialization signal GI may be provided to each pixel PX at a second frequency FF2 higher than the first frequency FF1. For example, the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN and the gate writing signal GW may be provided to each pixel PX such that the display scan operation and the self-scan operation may be substantially simultaneously performed, and then the first emission signal EM1, the second emission signal EM2 and the gate initialization signal GI may be provided to each pixel PX such that the self-scan operation may be additionally performed. Accordingly, the self-scan operation may be performed at the second frequency FF2 higher than the first frequency FF1 that is a frequency of the display scan operation, or the display scan frequency.
In an exemplary embodiment, the first frequency FF1 may be a variable frequency, and the second frequency FF2 may be a fixed frequency. Thus, the first frequency FF1 may be changed according to the variable input frame frequency, but the second frequency FF2 may be substantially constant even if the variable input frame frequency is changed. Accordingly, since the second frequency FF2 that is a frequency of the self-scan operation, or a self-scan frequency is substantially constant even if the first frequency FF1 that is the frequency of the display scan operation, or the display scan frequency is changed, the bias may be applied at the substantially constant second frequency FF2 to the first transistor T1 of each pixel PX, and thus the first transistor T1 of each pixel PX may have a substantially constant driving characteristic at any driving frequency.
In an exemplary embodiment, the second frequency FF2 may correspond to a double of a maximum frequency of the variable input frame frequency, and the first frequency FF1 may be determined as the second frequency FF2 divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency. For example, in a case where the variable input frame frequency ranges from about 1 Hz to about 120 Hz, the second frequency FF2 may be determined as about 240 Hz that is a double of the maximum frequency of about 120 Hz. Further, the first frequency FF1 may be determined corresponding to the variable input frame frequency in a current frame period among values calculated by diving the second frequency FF2 by N, for example about 120 Hz (in a case where N is 2), about 80 Hz (in a case where N is 3), about 60 Hz (in a case where N is 4), . . . , about 1 Hz (in a case where N is 240), or the like.
As described above, in the pixel PX according to an exemplary embodiment, since the third and sixth transistors T3 and T6 directly or indirectly connected to the capacitor CST are implemented with the NMOS transistors, the leakage current through the third and sixth transistors T3 and T6 from the capacitor CST may be reduced. Further, in the OLED display device including the pixel PX according to an exemplary embodiment, the frequency of the self-scan operation that applies the bias to the first transistor T1 of each pixel PX, or the second frequency FF2 may be the fixed frequency higher than the first frequency FF1. Accordingly, even if the driving frequency of the display panel, or the display scan frequency is changed, the pixel PX and the OLED display device according to an exemplary embodiment may display an image with substantially constant luminance at the same gray level.
In an alternate embodiment, the first through fifth transistors T1, T2, T3′, T4 and T5 may be implemented with PMOS transistors, and the sixth transistor T6 may be implemented with an NMOS transistor that has a relatively low leakage current. In this case, since sixth transistor T6 indirectly connected to the capacitor CST is implemented with the NMOS transistor, a leakage current through the sixth transistor T6 from the capacitor CST may be reduced.
Referring to
In the gate and anode initialization period GAIP, a gate node NG and an anode of an organic light-emitting diode EL may be initialized. As illustrated in
In an exemplary embodiment, as illustrated in
In the gate and anode initialization period GAIP, as illustrated in
In the data writing period DWP, a data voltage of a data line DL may be written to the capacitor CST. As illustrated in
In the data writing period DWP, as illustrated in
In the first bias period BP1, a bias (e.g., an on-bias) may be applied to the first transistor T1. As illustrated in
In the first bias period BP1, as illustrated in
In the first emission period EP1, the organic light-emitting diode EL may emit light. As illustrated in
In the first emission period EP1, as illustrated in
In the anode initialization period AIP, the anode of the organic light-emitting diode EL may be initialized. As illustrated in
In the anode initialization period AIP, as illustrated in
In the second bias period BP2, the bias (e.g., the on-bias) may be applied to the first transistor T1. In an exemplary embodiment, a time length of the second bias period BP2 may range, but not limited to, from two horizontal times (2H time) to eight horizontal times (8H time). The first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN and the gate writing signal GW in the second bias period BP2 may be substantially the same as the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN and the gate writing signal GW in the first bias period BP1, and an operation of the pixel PX in the second bias period BP2 may be substantially the same as an operation of the pixel PX in the first bias period BP1. That is, the voltage of the gate node NG, or the voltage VDAT-VTH where the threshold voltage VTH is subtracted from the data voltage VDAT may be applied to the gate of the first transistor T1, and the first power supply voltage ELVDD may be applied to the first terminal (e.g., the source) of the first transistor T1, and thus the bias corresponding to the on-state, or the on-bias using the first power supply voltage ELVDD may be applied to the first transistor T1. Accordingly, even if the first frequency FF1 that is the driving frequency or the display scan frequency is changed, the bias may be applied to the first transistor T1 at the second frequency FF2 that is the self-scan frequency.
In the second emission period EP2, the organic light-emitting diode EL may emit light. An operation of the pixel PX in the second emission period EP2 may be substantially the same as an operation of the pixel PX in the first emission period EP1. That is, in the second emission period EP2, the organic light-emitting diode EL may emit light based on the driving current corresponding to the data voltage VDAT.
In an exemplary embodiment, the second frequency FF2 may be determined as a fixed frequency (e.g., about 240 Hz) corresponding to a double of the maximum frequency (e.g., about 120 Hz) of the variable input frame frequency, and the first frequency FF1 may be determined as the second frequency divided FF2 by N according to the variable input frame frequency in each frame period, where N is an integer greater than 1 and less than or equal to the maximum frequency.
Referring to
As illustrated in
Referring to
The display panel 310 may include a plurality of pixels PX. Each pixel PX of the display panel 310 may be a pixel PX of
The data driver 320 may provide data voltages VDAT to the plurality of pixels PX based on output image data ODAT and a data control signal DCTRL received from the controller 350. In an exemplary embodiment, the data control signal DCTRL may include, but not limited to, an output data enable signal, a horizontal start signal and a load signal. The data driver 320 may receive, as output image data ODAT, frame data at a first frequency FF1 that is a driving frequency of the display panel 310, or a display scan frequency from the controller 350. In an exemplary embodiment, the data driver 320 and the controller 350 may be implemented with a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED). In other an exemplary embodiment, the data driver 320 and the controller 350 may be implemented with separate integrated circuits.
The scan driver 330 may provide a scan signal SCAN, a gate writing signal GW and a gate initialization signal GI to the plurality of pixels PX based on a scan control signal received from the controller 350. In an exemplary embodiment, the scan control signal may include a scan start pulse SCAN_SP, a gate writing start pulse GW_SP and a gate initialization start pulse GI_SP. The scan driver 330 may sequentially provide the scan signal SCAN to the plurality of pixels PX on a row-by-row basis in response to the scan start pulse SCAN_SP, may sequentially provide the a gate writing signal GW to the plurality of pixels PX on a row-by-row basis in response to the gate writing start pulse GW_SP, and may sequentially provide the gate initialization signal GI to the plurality of pixels PX on a row-by-row basis in response to the gate initialization start pulse GI_SP. In an exemplary embodiment, the scan driver 330 may receive the scan start pulse SCAN_SP and the gate writing start pulse GW_SP at the first frequency FF1, and may receive the gate initialization start pulse GI_SP at a second frequency FF2 that is a self-scan frequency. Further, in an exemplary embodiment, the scan control signal may further include, but not limited to, a scan clock signal, a gate writing clock signal and a gate initialization clock signal. In an exemplary embodiment, the scan driver 330 may be integrated or formed in a peripheral portion of the display panel 310. In other an exemplary embodiment, the scan driver 330 may be implemented with one or more integrated circuits.
The emission driver 340 may provide a first emission signal EM1 and a second emission signal EM2 to the plurality of pixels PX based on an emission control signal received from the controller 350. The emission control signal may include a first emission start pulse EM1_SP and a second emission start pulse EM2_SP. The emission driver 340 may sequentially provide the first emission signal EM1 to the plurality of pixels PX on a row-by-row basis in response to the first emission start pulse EM1_SP, and may sequentially provide the second emission signal EM2 to the plurality of pixels PX on a row-by-row basis in response to the second emission start pulse EM2_SP. In an exemplary embodiment, the emission driver 340 may receive the first emission start pulse EM1_SP and the second emission start pulse EM2_SP at the second frequency FF2. Further, in an exemplary embodiment, the emission control signal may further include, but not limited to, a first emission clock signal and a second emission clock signal. In an exemplary embodiment, the emission driver 340 may be integrated or formed in the peripheral portion of the display panel 310. In other an exemplary embodiment, the emission driver 340 may be implemented with one or more integrated circuits.
The controller 350 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphic processing unit (GPU), an application processor (AP) or a graphic card). In an exemplary embodiment, the input image data IDAT may be RGB image data including red image data, green image data and blue image data. In an exemplary embodiment, the control signal CTRL may include, but not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, or the like The controller 350 may generate the output image data ODAT, the data control signal DCTRL, the scan control signal and the emission control signal based on the input image data IDAT and the control signal CTRL. The controller 350 may control an operation of the data driver 320 by providing the output image data ODAT and the data control signal DCTRL to the data driver 320, may control an operation of the scan driver 330 by providing the scan control signal to the scan driver 330, and may control an operation of the emission driver 340 by providing the emission control signal to the emission driver 340.
According to an exemplary embodiment, a display device 300 includes: a display panel 310 having a plurality of pixels PX; a scan driver 330 configured to provide a scan signal to the plurality of pixels; and an emission driver 340 configured to provide an emission signal to the plurality of pixels; wherein each of the plurality of pixels includes: a capacitor Cst including a first electrode coupled to a first power line ELVDD, and a second electrode; a first transistor T1 including a gate coupled to the second electrode of the capacitor, a first terminal, and a second terminal; a second transistor T2 including a gate coupled to the scan driver, a first terminal coupled to a data line DL, and a second terminal coupled to the first terminal of the first transistor; a third transistor including a gate coupled to the scan driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate of the first transistor; a fifth transistor including a gate coupled to the emission driver, a first terminal coupled to the first power line, and a second terminal coupled to the first terminal of the first transistor; and a sixth transistor including a gate coupled to the emission driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a first terminal of an emission device EL, wherein the scan driver provides a signal to the plurality of pixels at a first frequency FF1; wherein the emission driver provides a signal to the plurality of pixels at a second frequency FF2 greater than the first frequency.
In an exemplary embodiment, the display device may include: a fourth transistor T4 including a gate receiving a signal at the second frequency FF2, a first terminal coupled to a line of an initialization voltage Vint, and a second terminal coupled to the first terminal of the emission device. The first, second, fourth and fifth transistors may be PMOS transistors, and at least one of the third or sixth transistors may be an NMOS transistor. The second frequency may be a fixed frequency, and the first frequency may be a variable frequency. The emission device may be an OLED, and the second frequency may correspond to a non-zero multiple of the first frequency.
The controller 350 of the OLED display device 300 according to an exemplary embodiment may receive the input image data DAT at a variable input frame frequency VIFF from the host processor in a variable frame mode (e.g., a Free-Sync mode, a G-Sync mode, a Q-Sync mode, or the like). For example, as illustrated in
In an exemplary embodiment, the second frequency FF2 that is the self-scan frequency may be a fixed frequency (e.g., about 240 Hz) corresponding to a double of a maximum frequency (e.g., about 120 Hz) of the variable input frame frequency VIFF. Further, the first frequency FF1 that is the driving frequency of the display panel 310, or the display scan frequency may be determined as the second frequency FF2 divided by N according to the variable input frame frequency VIFF in each frame period, where N is an integer greater than 1 and less than or equal to the maximum frequency. Thus, the OLED display device 300 according to an exemplary embodiment may perform a display scan operation that writes the data voltages VDAT corresponding to the output image data ODAT to the plurality of pixels PX at the first frequency FF1 that is the variable frequency, and may perform a self-scan operation that applies a bias to driving transistors of the plurality of pixels PX at the second frequency FF2 that is the fixed frequency. In an exemplary embodiment, in each frame period, the OLED display device 300 may substantially simultaneously perform the display scan operation and the self-scan operation once, and then may additionally perform the self-scan operation once or more.
For example, as illustrated in
To perform the display scan operation at the first frequency FF1 that is the variable frequency and to perform the self-scan operation at the second frequency FF2, the controller 350 may provide the scan start pulse SCAN_SP and the gate writing start pulse GW_SP to the scan driver 330 at the first frequency FF1, may provide the gate initialization start pulse GI_SP to the scan driver 330 at the second frequency FF2, and may provide the first emission start pulse EM1_SP and the second emission start pulse EM2_SP to the emission driver 340 at the second frequency FF2. Further, a time length of each frame period FP may correspond to the first frequency FF1. Thus, in each frame period FP, the controller 350 may provide one scan start pulse SCAN_SP, one gate writing start pulse GW_SP and at least two gate initialization start pulses GI_SP to the scan driver 330, and may provide at least two first emission start pulses EM1_SP and at least two second emission start pulses EM2_SP to the emission driver 340.
For example, as illustrated in
Further, as illustrated in
As described above, in the OLED display device 300 according to an exemplary embodiment, the self-scan frequency, or the second frequency FF2 may be the fixed frequency higher than the first frequency FF1. Accordingly, even if the first frequency FF1 that is the driving frequency of the display panel 310, or the display scan frequency is changed, the OLED display device 300 according to an exemplary embodiment may display an image with substantially constant luminance at the same gray level.
Although exemplary embodiments have been shown and described wherein the higher self-scan frequency is fixed and the potentially lower frequency frame rate is variable, embodiments are not limited thereto. For example, the higher self-scan frequency may be a minimum multiple of the variable frame rate to meet or exceed a threshold frequency.
Referring to
The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a micro processor, a central processing unit (CPU), or the like The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, or the like Further, in An exemplary embodiment, the processor 1110 may be further coupled to an extended bus such as a peripheral component interconnection (PCI) bus.
The memory device 1120 may store data for operations of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAIVI) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc, and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, or the like
The storage device 1130 may be a solid-state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like The I/O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc, and an output device such as a printer, a speaker, or the like The power supply 1150 may supply power for operations of the electronic device 1100. The OLED display device 1160 may be coupled to other components through the buses or other communication links.
The OLED display device 1160 may be substantially similar to the OLED display device 300 of
The inventive concepts may be applied to any OLED display device 1160 supporting a variable frame mode, and any electronic device 1100 including the OLED display device 1160. For example, the inventive concepts may be applied to a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a television (TV), a digital TV, a three-dimensional (3D) TV, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, or the like
Although exemplary embodiments have been described, those of ordinary skill in the pertinent art may readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the teachings of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2020-0043270 | Apr 2020 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 10490128 | Qian et al. | Nov 2019 | B1 |
| 20180174514 | Lee | Jun 2018 | A1 |
| 20190051250 | Lee | Feb 2019 | A1 |
| 20190237010 | Lin et al. | Aug 2019 | A1 |
| Number | Date | Country |
|---|---|---|
| 107945743 | Apr 2018 | CN |
| 110176213 | Aug 2019 | CN |
| Number | Date | Country | |
|---|---|---|---|
| 20210319755 A1 | Oct 2021 | US |
