Patent Grant
7515121
This application is a U.S. National Phase Application under 35 USC 371 of International Application PCT/JP03/07430 filed Jun. 11, 2003.
The present invention relates to a display apparatus including an optical element which performs an optical operation in accordance with a current value, in particular, a light emitting element which emits light with a luminance in accordance with the current value for each pixel, and a driving method of the apparatus.
In general, a display apparatus includes an apparatus of a passive driving system such as a simple matrix, and an apparatus of an active matrix driving system in which a switching transistor is disposed for each pixel. In a liquid crystal display of an active matrix driving system, as shown in
On the other hand, the display apparatus in which an organic EL element is used as a self-luminous element does not require a backlight differently from the liquid crystal display, and is optimum for miniaturization. Moreover, there is not any restriction of a visual field angle differently from the liquid crystal display, and therefore practical use of the display apparatus for the next generation has largely been expected. Different from the liquid crystal element, the organic EL element emits the light by a current flowing inside. Therefore, an emission luminance does not directly depend on the voltage, and depends on current density.
From viewpoints of high luminance, contrast, and fineness, also in the organic EL display, there has been a demand especially for the active matrix driving system in the same manner as in the liquid crystal display. For the organic EL display, the current flowing in the selection period has to be increased in the passive driving system. On the other hand, in the active matrix driving system, an element for holding the voltages applied to opposite ends of the organic EL element is disposed for each pixel in order to maintain continuous emission of each organic EL element at a predetermined luminance so that the light is emitted even in the non-selection period. Therefore, the current value of the flowing current per unit time may be small. However, the organic EL element has only a remarkably small capacity as the condenser. Therefore, when the organic EL element is simply disposed instead of the liquid crystal element 501 in the circuit of the pixel shown in
To solve the problem, for example, as shown in
In general, for the transistor, a channel resistance depends on an ambient temperature, and the channel resistance changes by the use for a long time. Therefore, a gate threshold voltage changes with elapse of time, and the gate threshold voltage of each transistor in the same display region varies. Therefore, when the voltage value of the voltage applied to the gate electrode of the transistor 605 is controlled, the value of the current flowing through the organic EL element 601 is controlled. In other words, when a level of the voltage applied to the gate electrode of the transistor 605 is controlled, it is difficult to exactly control the luminance of the organic EL element 601.
To solve the problem, a technique of controlling the luminance by the current value of the current, not by the level of the voltage applied to the transistor has been researched. That is, instead of a voltage designating system in which the level of the gate voltage is designated in the signal line, a current designating system in which the current value of the current flowing through the organic EL element is directly designated for the signal line is applied to the active matrix driving system of the organic EL display.
However, in the organic EL display of the current designating system, the current value of the designated current is constant in the selection period when the designated current is passed. However, when the current value of the designated current is small, much time is required until the voltage is brought into a stationary state by the designated current. Therefore, the organic EL element does not emit the light at a desired luminance, and this results in a drop in display quality of the organic EL display.
On the other hand, when the selection period is lengthened, selection time becomes longer than a time for bringing the voltage into the stationary state. However, when the selection time lengthens, a display screen blinks. In this manner, the drop in the display quality of the organic EL display is caused.
Therefore, an advantage of the present invention is to perform high-quality display.
To obtain the above-described advantage, according to one aspect of the present invention, for example, as shown in
a plurality of pixels (e.g., pixels Pi,j) which are disposed in intersecting portions of a plurality of scanning lines arranged in a plurality of rows (e.g., selection scanning lines X1 to Xm, power scanning lines Z1 to Zm) and a plurality of signal lines arranged in a plurality of columns (e.g., signal lines Y1 to Yn) and which comprise optical elements (e.g., organic EL elements Ei,j) optically operating by a driving current flowing in accordance with a gradation current from the signal line; and
reset means (e.g., current/voltage changeover portions 7, 107) for setting a potential of the signal line in accordance with electric charges charged in the signal line by the gradation current to a reset voltage (e.g., a reset voltage VR).
In the present invention, when the pixel of the predetermined row is selected, the gradation current flows through each signal line. However, even when a difference between the potential set to be stationary by the gradation current flowing through the signal line for the pixel of the previous row and the potential of the signal line to be set to be stationary by the gradation current passed through the signal line for the pixel of the next row is large, and the current value of the gradation current for the next pixel is small, a reset voltage is applied to the signal line immediately before the next row. Therefore, the signal line can quickly be set to be stationary at the voltage in accordance with the gradation current for the next row.
Moreover, according to another aspect of the present invention, there is provided a display apparatus comprising:
a signal line (e.g., signal lines Y1 to Yn) to which a current is supplied so as to obtain an arbitrary current value;
an optical element (e.g., organic EL elements Ei,j) which optically behaves in accordance with the current value of the current flowing via the signal line; and
stationary voltage supply means for supplying a stationary voltage which sets the current value of the current flowing through the signal line to be stationary to the signal line (e.g., current/voltage changeover portions 7, 107).
In the present invention, when a micro current is passed through the signal line, at the current value of the micro current, the electric charges accumulated in a capacity connected to the signal line beforehand are insufficiently shifted in a predetermined period, and so it is difficult to set the current value of the micro current to be stationary. Even in this case, since the stationary voltage supply means supplies the stationary voltage to the signal line, an electric charge amount of the capacity connected to the signal line can forcibly be changed so that the micro current passed through the signal line can quickly be set to be stationary.
According to another aspect of the present invention, there is provided a driving method of a display apparatus comprising a plurality of pixels (e.g., pixels Pi,j) which are disposed in intersecting portions of a plurality of scanning lines arranged in a plurality of rows (e.g., selection scanning lines X1 to Xm, power scanning lines Z1 to Zm) and a plurality of signal lines arranged in a plurality of columns (e.g., signal lines Y1 to Yn) and which comprise optical elements (e.g., organic EL elements Ei,j) optically operating by a driving current flowing in accordance with a gradation current from the signal line, the method comprising:
a gradation current step of passing the gradation current through the signal lines; and
a reset voltage step of displacing a potential in accordance with electric charges charged in the signal lines setting by the gradation current to a reset voltage.
In the driving method of the display apparatus according to the present invention, since the potential in accordance with the electric charges charged in the signal lines by the gradation current in the gradation current step is displaced to the reset voltage at the reset voltage step, the current flowing through the signal line can quickly be set to be stationary at an arbitrary current value.
Concrete modes of the present invention will be described hereinafter with reference to the drawings. Additionally, the scope of the present invention is not limited to shown examples.
The organic EL display panel 2 includes: a transparent substrate 8; a display portion 4 as a display region in which an image is substantially displayed; a selection scanning driver 5 disposed around the display portion 4, that is, in a non-display region; a power scanning driver 6; and a current/voltage changeover portion 7, to form a basic constitution. These circuits 4 to 7 are formed on the transparent substrate 8.
In the display portion 4, (m×n) pixels P1,1 to Pm,n (m, n are arbitrary natural numbers) are disposed on the transparent substrate 8 in a matrix form. In a column direction, that is, a longitudinal direction, m pixels P1,j to Pm,j (j is an arbitrary natural number, 1≦j≦n) are disposed. Moreover, in a row direction, that is, in a lateral direction, n pixels Pi,1 to Pi,n (i is an arbitrary natural number, 1≦i≦m) are disposed. That is, a pixel which is i-th (i.e. i-th row) from above in the longitudinal direction and j-th (i.e., j-th column) from the left in the lateral direction is a pixel Pi,j.
In the display portion 4, m selection scanning lines X1 to Xm extending in a row direction are juxtaposed in a column direction on the transparent substrate 8. The m power scanning lines Z1 to Zm extending in the row direction are disposed opposite to selection scanning lines X1 to Xm and juxtaposed in the column direction on the transparent substrate 8. Each power scanning line Zk (1≦k≦m−1) is disposed between selection scanning lines Xk and Xk+1, and selection scanning line Xm is disposed between power scanning lines Zm−1 and Zm. The n signal lines Y1 to Yn extending in the column direction are juxtaposed in the row direction on the transparent substrate 8, and these selection scanning lines X1 to Xm, power scanning lines Z1 to Zm, and signal lines Y1 to Yn are insulated from one another by insulation films disposed among these. The selection scanning line Xi and power scanning line Zi are connected to n pixels Pi,1 to Pi,n arranged in the row direction, the signal line Yj is connected to m pixels P1,j to Pm,j arranged in the column direction, and the pixel Pi,j is disposed in a position surrounded with the selection scanning line Xi, power scanning line Zi, and signal line Yj.
Next, each pixel Pi,j will be described with reference to
The pixel Pi,j is constituted of an organic EL element Ei,j which emits light at a luminance in accordance with the current value of the driving current, and a pixel circuit Di,j which is disposed around the organic EL element Ei,j and which drives the organic EL element Ei,j. The pixel circuit Di,j holds the current value of the current flowing through the organic EL element Ei,j in a given emission period based on signals outputted from the data driver 3, selection scanning driver 5, and power scanning driver 6 to hold an emission luminance of the organic EL element Ei,j to be constant for a predetermined period.
The organic EL element Ei,j includes a stacked structure in which a pixel electrode 51 functioning as an anode on the transparent substrate 8, an organic EL layer 52, and the common electrode 53 function as a cathode are stacked in order. The organic EL layer includes function of transporting a hole and electron implanted by an electric field, and includes a re-bonding region in which the transported hole and electron are re-bonded and an emission region in which an exciton generated by the re-bonding is captured to emit the light to function as an emission layer in a broad sense.
The pixel electrode 51 is patterned to be divided for each pixel Pi,j in regions surrounded with two signal lines disposed adjacent to each other in the signal lines Y1 to Yn and two lines disposed adjacent to each other in the selection scanning lines X1 to Xm. A peripheral edge of the electrode is coated with an interlayer insulation film 54 including silicon nitride or silicon oxide with which three transistors 21, 22, 23 of each pixel circuit Di,j are coated, and a middle upper surface of the electrode is exposed by a contact hole 55 of the interlayer insulation film 54. For the interlayer insulation film 54, a second layer formed of the insulation film made of such as polyimide may further be disposed on a first layer of silicon nitride or silicon oxide.
The pixel electrode 51 has not only conductivity but also a transmission property to a visible light. The pixel electrode 51 has a relatively high work function, and preferably efficiently implants the hole into the organic EL layer 52. For example, the pixel electrode 51 is formed of films including main components such as tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In2O3), tin oxide (SnO2) and zinc oxide (ZnO).
The organic EL layer 52 is formed in the film on each pixel electrode 51. The organic EL layer 52 is also patterned for each pixel Pi,j. The organic EL layer 52 contains an emission material (fluorescent material) which is an organic compound, but the emission material may be either a polymer-based material or a low-molecular material. For example, as shown in
In the organic EL display panel 2, full color display or multi-color display is possible. In this is case, the organic EL layers 52 of the respective pixels Pi,1 to Pi,n are emission layers in the broad sense, which have, for example, a function of emitting the light of any of red, green, blue. That is, when each of the pixels Pi,1 to Pi,n selectively emits the light of red, green, blue, color tone obtained by appropriately synthesizing these colors can be displayed.
The organic EL layer 52 is preferably formed of an electronically neutral organic compound, and accordingly the hole and electron are implanted and transported by the organic EL layer 52. A material having an electron transport property may appropriately be mixed in the emission layer in the narrow sense, a material having a hole transport property may appropriately be mixed in the emission layer in the narrow sense, or the materials having the electron and hole transport properties may appropriately be mixed in the emission layer in the narrow sense. A charge transport layer which is an electron transport layer or a hole transport layer may function as the re-bond region, and the fluorescent material may also be mixed in the charge transport layer to emit the light.
The common electrode 53 formed on the organic EL layer 52 is one electrode connected to all the pixels P1,1 to Pm,n. Instead, the common electrode 53 may also be a plurality of striped electrodes connected to each column, constituted of a striped common electrode connected to a group of pixels P1,h−1 to Pm,h−1 (h is an arbitrary natural number and 2≦h≦n) of the column direction, or a striped common electrode connected to a group of pixels P1,h to Pm,h. Additionally, the common electrode may also be a plurality of striped electrodes connected to each column, constituted of a striped common electrode connected to a group of pixels Pg−1,1 to Pg−1,n (g is an arbitrary natural number and 2≦g≦n) of the row direction, to a striped common electrode connected to a group of pixels Pg,1 to Pg,n.
In any case, the common electrode 53 is electrically insulated from the selection scanning line Xi, signal line Yj, and power scanning line Zi. The common electrode 53 is formed of materials having a low work function, such as one unit including at least one of indium, magnesium, calcium, lithium, barium, and rare earth metal, and an alloy. The common electrode 53 may also include the stacked structure in which a plurality of layers of various material are stacked. Concretely, the common electrode may include a stacked structure of a high-purity barium layer having a low work function, disposed on an interface side in contact with the organic EL layer 52, and an aluminum layer with which the barium layer is coated, or a stacked structure in which the lithium layer is disposed in a lower layer and the aluminum layer is disposed in an upper layer. When the pixel electrode 51 is assumed to be a transparent electrode, and the light emitted from the organic EL layer 52 of the organic EL display panel 2 is emitted via the pixel electrode 51 on a transparent substrate 8 side, the common electrode 53 preferably has a shield property with respect to the light emitted from the organic EL layer 52, and further preferably has a high reflection property with respect to the light emitted from the organic EL layer 52.
As described above, in the organic EL element Ei,j which has the stacked structure, when a forward bias voltage is applied between the pixel electrode 51 and common electrode 53, the hole is implanted in the organic EL layer 52 from the pixel electrode 51, and the electron is implanted in the organic EL layer 52 from the common electrode 53. Moreover, the hole and electron are transported by the organic EL layer 52, the hole and electron are re-bonded in the organic EL layer 52 to generate the exciton, the exciton excites the organic EL layer 52, and the organic EL layer 52 emits the light.
Here, an emission luminance (unit cd/m2) of the organic EL element Ei,j depends on the current value of the current flowing through the organic EL element Ei,j. The emission luminance of the organic EL element Ei,j is kept to be constant in an emission period of the organic EL element Ei,j, or the emission luminance is set in accordance with the current value of a gradation signal outputted from the data driver 3. For this purpose, the pixel circuit Di,j which controls the current value of the organic EL element Ei,j is disposed around the organic EL element Ei,j for each pixel Pi,j.
Each pixel circuit Di,j includes the first to third transistors 21, 22, 23 constituted of thin-film transistors (TFT) of a field effect type of an N channel MOS structure, and a capacitor 24.
Each first transistor 21 is a field-effect transistor of MOS type constituted of a gate electrode 21g, gate insulation film 42, semiconductor layer 43, source electrode 21s, and drain electrode 21d. Each second transistor 22 is a field-effect transistor of MOS type constituted of a gate electrode 22g, gate insulation film 42, semiconductor layer 43, source electrode 22s, and drain electrode 22d. Each third transistor 23 is constituted of a gate electrode 23g, gate insulation film 42, semiconductor layer 43, source electrode 23s, and drain electrode 23d.
Concretely, as shown in
The second and third transistors 22 and 23 also have the same constitution as that of the first transistor 21, but a shape, size, dimension of each of the transistors 21, 22, 23, a channel width of the semiconductor layer 43, a channel length of the semiconductor layer 43, and the like are appropriately set in accordance with the functions of the transistors 21, 22, 23.
Moreover, the transistors 21, 22, 23 may simultaneously be formed in the same process. In this case, the transistors 21, 22, 23 have the same compositions of the gate electrode, oxidation insulation film 41, gate insulation film 42, semiconductor layer 43, impurity semiconductor layers 44, 44, source electrode, and drain electrode.
Even when the semiconductor layers 43 of the transistors 21, 22, 23 are amorphous silicon, sufficient driving is possible, but the semiconductor layer may also be poly-silicon or monocrystalline silicon. The structure of the transistors 21, 22, 23 is not limited to the inverse stagger type, and may also be of a stagger or coplanar type.
Each capacitor 24 is connected to an electrode 24A connected to the gate electrode 23g of each third transistor 23, an electrode 24B connected to the source electrode 23s of the transistor 23, and a dielectric including a part of the gate insulation film 42 disposed between the electrodes 24A and 24B, and accumulates electric charges between the source electrode 23s and drain electrode 23d of the transistor 23.
As shown in
In the pixels P1,1 to Pm,n, as shown in
Between the selection scanning line Xi and signal line Yj, and between the power scanning line Zi and signal line Yj, in addition to the gate insulation film 42, a protective film 43A is formed and disposed by patterning the same film as that of the semiconductor layer 43 of each of the transistors 21 to 23.
As shown in
The selection scanning driver 5 is formed of a so-called shifter register. As a result, after a predetermined time (in detail, a reset period TRESET described later), the selection scanning driver 5 successively outputs a scanning signal to the selection scanning line Xm from the selection scanning line X1 in order based on a clock signal from the outside (scanning line X1 next to the scanning line Xm), and the transistors 21, 22 of the scanning lines X1 to Xm are selected.
In detail, as shown in
That is, in the selection period TSE in which any selection scanning line Xi is selected from the selection scanning lines X1 to Xm, when the selection scanning driver 5 outputs the pulse signal of the on-voltage Von to the selection scanning line Xi, the transistors 21, 22 connected to the selection scanning line Xi are brought in the on state (all transistors 21, 22 of the pixel circuits Di,1, Di,2, Di,3 . . . Di,n). When the transistor 21 is in the on state, the current flowing through the signal line Yj can flow through the pixel circuit Di,j. At this time, for the selection scanning lines X1 to Xm, the respective transistors 21, 22 of the X1 to Xi−1 Xi+1 to Xm other than the selection scanning line Xi are in the non-selection period TNSE. Therefore, the off-voltage Voff is outputted and both the transistors 21, 22 are in the off state. When the transistors 21, 22 are in the off state in this manner, the current flowing through the signal line Yj cannot flow through the pixel circuit Di,j.
Here, the selection period TSE of the i-th row does not continue to that of the (i+1)-st row, and a reset period TRESET shorter than the selection period TSE exists between the selection periods TSE of the i-th row and the (i+1)-st row. That is, after elapse of the reset period TRESET after the pulse signal of the on-voltage Von is completely outputted to the selection scanning line Xi of the i-th row, the selection scanning driver 5 outputs the pulse signal of the on-voltage Von to the selection scanning line Xi+1 of the (i+1)-th row. Accordingly, after the elapse of the reset period TRESET after the completion of the selection of the i-th row, the i+1-st row is selected.
The details will be described later. In each selection period TSE in which the selection scanning lines X1 to Xm are selected, when the data driver 3 appropriately passes the current through current terminals OT1 to OTn, a gradation designating current appropriately flows through the signal lines Y1 to Yn along a direction shown by an arrow of
The power scanning driver 6 shown in
In detail, as shown in
Next, the power voltage VDD will be described.
Moreover, in
As described above, in the unsaturated region, even when the drain/source voltage VDS slightly changes, the current value IDS of the source/drain current changes. However, in the saturated region, when the gate/source voltage VGS is determined, the current value IDS of the drain/source current is uniquely determined irrespective of the source/drain voltage VDS.
Here, the current value IDS of the drain/source current at a time when the maximum gate/source voltage VGSMAX is applied to the third transistor 23 is set to the current value of the current flowing between the pixel electrode 51 and common electrode 53 of the organic EL element Ei,j which emits the light at the maximum luminance.
Even when the gate/source voltage VGS of the third transistor 23 is maximum VGSMAX, the following condition equation (1) is preferably satisfied so that the transistor 23 maintains the saturated region.
VDD−VE−VSS≧VTHMAX (1),
where VE is a predicted maximum voltage divided into the organic EL element Ei,j at a maximum luminance time, which gradually increases for high resistance of the organic EL element Ei,j in an emission life period of the organic EL element Ei,j, and VTHMAX is a saturated threshold voltage between the source and drain of the third transistor 23 at a time of VGSMAX. The power voltage VDD is determined so as to satisfy the above condition equation.
As shown in
The reset voltage VR is set to a voltage higher than a highest gradation voltage Vhsb. This highest gradation voltage Vhsb is a voltage V set to be stationary in accordance with the electric charges charged in the signal lines Y1 to Yn by the gradation designating current having a current value equal to that of a maximum gradation driving current IMAX flowing through the organic EL elements E1,1 to Em,n, when the organic EL elements E1,1 to Em,n emit the light at a brightest maximum gradation luminance IMAX in the selection period TSE. The reset voltage VR is preferably not less than an intermediate voltage which has an intermediate value between a lowest gradation voltage Vlsb set to be stationary in accordance with the electric charges charged in the signal lines Y1 to Yn by the gradation designating current having a current value equal to that of a minimum gradation driving current IMIN flowing through the organic EL elements E1,1 to Em,n, when each of the organic EL elements E1,1 to Em,n has a minimum gradation luminance LMIN (additionally, the current value of the current exceeds 0 A), and the highest gradation voltage Vhsb, more preferably a value equal to or more than the lowest gradation voltage Vlsb, most preferably a voltage equal to the charge voltage VCH.
A switch circuit Sj (the switch circuit Sj is connected to the signal line Yj of the j-th column) switches to either one of the passing of the current through the signal line Yj in accordance with the signal from the current terminal OTj of the data driver 3 and the outputting of the reset voltage VR of a predetermined voltage level from the reset voltage input terminal 141 to the signal line Yj. That is, when the switch signal φ inputted into the switch circuit Sj from the switch signal input terminal 140 is of a high level, the switch circuit Sj cuts the sink current of the current terminal OTj, and outputs the reset voltage from the reset voltage input terminal 141 to the signal line Yj. On the other hand, when the switch signal φ inputted into the switch circuit Sj from the switch signal input terminal 140 is of a low level, the switch circuit Sj passes the sink current between the current terminal OTj and signal line Yj, and cuts the reset voltage VR from the reset voltage input terminal 141.
In this manner, when the source/drain voltage of the third transistor 23 is set to be a high voltage in the saturated region shown in
Here, a display apparatus is considered assuming that the current/voltage switch portion 7 of the present invention is not disposed and the data driver 3 derives the current directly from the signal line Yj.
In the pixel Pi,j of the i-th row and j-th column, in the selection period of the i-th row, the second transistor 22 connected to the selection scanning line Xi is brought in the on state. Accordingly, the charge voltage VCH is applied to the gate of the third transistor 23 from the power scanning line Zi, and the electric charges are charged into the capacitor 24 from one electrode 24A side of the third transistor 23. That is, the gate voltage of the transistor 23 of the selection period is always substantially constant at the charge voltage VCH. At this time, the potential of the source 23s of the transistor 23 is equal to that of the signal line Yj because the transistor 21 is in the on state. The potential of the signal line Yj is controlled by the data driver 3. Moreover, the data driver 3 forcibly passes the gradation designating current having the predetermined current value between the source and drain of the transistor 23. Therefore, when the current value of the gradation designating current is large, the gate/source voltage of the transistor 23 is high, and therefore the potential of the signal line Yj is relatively lower.
More concretely, as shown in
Moreover, when the sink current (additionally, not non-current) having the minimum current value is passed through the signal line Yj in order to emit the light from the organic EL element Ei+1,j of the pixel Pi+1,j of the next (i+1)st row at the minimum gradation luminance (minimum luminance), the lowest gradation voltage Vlsb has to be set in order to charge the electric charges meeting the current value of the current in the capacitor 24. The lowest gradation voltage Vlsb is approximate to the charge voltage VCH so that the gate/source voltage of the third transistor 23 is low, and is sufficiently higher than the highest gradation voltage Vhsb. However, since the current value of the minimum gradation designating current flowing through the signal line Yj is remarkably small, the potential difference of the signal line Yj displaced in a unit time is small. Therefore, much time is required from when the capacitor 24 is charged up until the potential of the signal line Yj is set to be stationary at the lowest gradation voltage Vlsb from the highest gradation voltage Vhsb. Especially, when the number of rows of the display apparatuses is large with the increase in the number of pixels, the selection period TSE has to be set to be short. Without reaching the lowest gradation voltage Vlsb, a difference of a voltage VDF is generated, and the organic EL element Ei+1,j of the pixel Pi+1,j cannot emit the light at an exact luminance.
On the other hand, since the current/voltage switch portion 7 is disposed in the display apparatus 1 of the present embodiment, as shown in
Next, one example of the switch circuit Sj will be described. The switch circuit Sj is constituted of a fourth transistor 31 which is the field-effect transistor of the P channel type, and a fifth transistor 32 which is the field-effect transistor of the N channel type. The gate electrodes of the fourth and fifth transistors 31, 32 are connected to the switch signal input terminal 140. The source electrode of the fourth transistor 31 is connected to the signal line Yj, and the drain electrode is connected to the current terminal OTj. The drain electrode of the fifth transistor 32 is connected to the signal line Yj, and the source electrode is connected to the reset voltage input terminal 141. In this constitution, when the switch signal φ from the switch signal input terminal 140 is of the high level, the fifth transistor 32 obtains the on state, and the fourth transistor 31 obtains the off state. On the other hand, when the switch signal φ from the switch signal input terminal 140 is of the low level, the fourth transistor 31 obtains the on state, and the fifth transistor 32 obtains the off state. Different from this embodiment, the fourth transistor 31 is set to be of the P channel type, the fifth transistor 32 is set to be of the N channel type, and the high/low level of the switch signal φ may be brought in a reverse phase to change over the switching of the switch circuit Sj.
Here, a period of the switch signal φ inputted into the switch signal input terminal 140 will be described. When the selection scanning driver 5 applies the on-voltage Von to any of the selection scanning lines X1 to Xm as shown in
The data driver 3 passes the gradation designating current to the current terminals OT1 to OTn by the clock signal from the outside. When the switch signal φ inputted into the switch signal input terminal 140 is of the low level, the data driver 3 synchronously takes the gradation designating current into all the current terminals OT1 to OTn. When the switch signal φ inputted into the switch signal input terminal 140 is of the high level, the data driver 3 does not take the gradation designating current from any of the current terminals OT1 to OTn.
Therefore, in the selection period TSE of each row, the gradation designating current flows into the current terminals OT1 to OTn from the signal lines Y1 to Yn, On the other hand, in the reset period TRESET of each row, the reset voltage VR is applied to the signal lines Y1 to Yn to obtain the stationary state.
Next, the gradation designating current of the data driver 3 will be described in detail. In the selection period TSE of each row, the data driver 3 generates the gradation designating current toward the respective current terminals OT1 to OTn from the power scanning lines Z1 to Zm which output the charge voltage VCH through the third transistor 23, first transistor 21, signal lines Y1 to Yn, and switch circuits S1 to Sn. The current value of the gradation designating current has the level in accordance with the image data. That is, the current value of the gradation designating current is equal to that of the current flowing through the organic EL elements E1,1 to Em,n in order to emit the light at the luminance gradation in accordance with the image data.
Next, the display operation and driving method of the display apparatus 1 constituted as described above will be described.
As shown in
Moreover, since the switch signal φ inputted into the switch signal input terminal 140 has the low level in the selection period TSE of each row, the fourth transistors 31 of the switch circuits S1 to Sn obtain the on state, and the fifth transistors 32 obtain the off state. On the other hand, since the switch signal φ inputted into the switch signal input terminal has the high level in the reset period TRESET of each row, the fourth transistors 31 of the switch circuits S1 to Sn obtain the off state, and the fifth transistors 32 obtain the on state. That is, when the current/voltage switch portion 7 disconnects the signal lines Y1 to Yn from the reset voltage input terminal 141 in the selection period TSE of each row, the portion is to pass the gradation designating current equal to the current value of the current flowing through the organic EL elements E1,1 to Em,n in order to emit the light at the luminance gradation in accordance with the image data. The portion further functions not to apply the reset voltage VR to the signal lines Y1 to Yn. On the other hand, in the reset period TRESET of each row, the current/voltage switch portion 7 disconnects the signal lines Y1 to Yn from the current terminals OT1 to OTn, and connects the signal lines Y1 to Yn to the reset voltage input terminal 141. Accordingly, the portion functions so as to quickly set the potential of each of the signal lines Y1 to Yn to the reset voltage VR.
Here, a timing at which the on-voltage Von is outputted to the selection scanning line Xi substantially agrees with that at which the charge voltage VCH is outputted to the power scanning line Zi, a time length of the on-voltage Von is substantially the same as that of the charge voltage VCH, and the pulse signal is outputted between the time ti to time tiR (this period is the selection period TSE of the i-th row). That is, the period in which the on-voltage Von outputted from the selection scanning driver 5 shifts is synchronized with that in which the charge voltage VCH outputted from the power scanning driver 6. When the pulse signal of the on level is outputted to the selection scanning line Xi, the switch signal φ inputted into the switch signal input terminal 140 has the low level, and therefore the transistor 31 obtains the on state.
Since the charge voltage VCH outputted to the power scanning line Zi is not more than the reference voltage Vss in the selection period TSE, the gradation designating current does not flow through the organic EL elements Ei,1 to Ei,n. Therefore, the gradation designating current of the current value meeting the gradation flows through the data driver 3 from the transistor 23. Therefore, the electric charges are written in the capacitor 24 so as to maintain the exact voltage between the gate and source of the transistor 23, which is required for the third transistor 23 to pass the gradation designating current. As a result, the transistor 23 can continuously pass the driving current of the current value equal to that of the gradation designating current even in an emission period TEM. Since the transistor 21 has the off state in the emission period TEM, this driving current does not flow through the signal lines Y1 to Yn, and flows through the organic EL elements Ei,1 to Ei,n, and current control of a precise luminance gradation is possible.
As described above, when the selection scanning driver 5 and power scanning driver 6 linearly successively shift the pulse signal to the m-th row from the first row, the pixels P1,1 to P1,n of the first row to the pixels Pm,1 to Pm,n of the m-th row are successively updated based on the gradation designating current of the data driver 3. When this linearly successive scanning is repeated, the display portion 4 of the organic EL display panel 2 displays the image.
Here, the update of the pixels Pi,1 to Pi,n of the selected i-th row in one scanning period TSC, and the gradation representation of the pixels Pi,1 to Pi,n of the selected i-th row will be described.
In the selection period TSE of the i-th row, when the selection scanning driver 5 outputs the pulse signal of the high level to the selection scanning line Xi of the i-th row, the transistors 21 and 22 of all the pixel circuits Di,1 to Di,n connected to the selection scanning line Xi obtain the on state in the selection period TSE. Furthermore, in the selection period TSE of the i-th row, the power scanning driver 6 applies the pulse signal of the low level as the charge voltage VCH which is the same as or lower than the reference voltage Vss to the power scanning line Zi of the i-th row. At this time, since the transistor 22 has the on state, the voltage is also applied to the gate electrode 23g of the third transistor 23, and the third transistor 23 obtains the on state.
On the other hand, since the switch signal φ inputted into the switch signal input terminal 140 has the low level in the selection period TSE of the i-th row, the transistors 31 of all the switch circuits S1 to Sn have the on state, and the transistors 32 have the off state. Furthermore, in accordance with the image data inputted into the data driver 3 in the selection period of the i-th row, in all the pixel circuits Di,1 to Di,n of the i-th row, the gradation designating current flows through the data driver 3 set to the relatively low voltage so that the gradation designating current flows through the power scanning line Zi to which the charge voltage VCH of the relatively high voltage is applied→third transistor 23→first transistor 21→fourth transistor 31. At this time, the source/drain current of the third transistor 23 has the current value of the gradation designating current and the voltage between the gate and source of the transistor 23 obtains the current value of the gradation designating current flowing between the source and drain of the transistor 23 in the emission period TEM. To obtain this voltage, the electric charges are charged in the capacitor 24.
In this manner, in the selection period TSE of the i-th row, the gradation designating current having a constant level is forcibly passed through the power scanning line Zi→the third transistors 23 of the pixel circuits Di,1 to Di,n→the first transistors 21 of the pixel circuits Di,1 to Di,n→the signal lines Y1 to Yn→the fourth transistors 31 of the switch circuits S1 to Sn→the current terminals OT1 to OTn of the data driver 3. Accordingly, in the selection period TSE of the i-th row, the voltages in the power scanning line Zi, the transistors 23 of the pixel circuits Di,1 to Di,n, the transistors 21 of the pixel circuits Di,1 to Di,n, the signal lines Y1 to Yn, the transistors 31 of the switch circuits S1 to Sn, and the current terminals OT1 to OTn of the data driver 3 obtain the stationary state. Moreover, in any column of the first to n-th columns, the current value of the driving current flowing through the organic EL elements Ei,1 to Ei,n in the emission period TEM reaches the current value of the gradation designating current flowing through the signal lines Y1 to Yn.
That is, the gradation designating current flows through the transistor 23, and the voltage in the power scanning line Zi→ the transistors 23 of the pixel circuits Di,1 to Di,n → the transistors 21 of the pixel circuits Di,1 to Di,n → the signal lines Y1 to Yn →the transistors 31 of the switch circuits S1 to Sn →the current terminals OT1 to OTn of the data driver 3 obtains the stationary state. Accordingly, the voltage of the level in accordance with the current value of the gradation designating current flowing through the transistor 23 is applied between the gate electrode 23g and source electrode 23s of the transistor 23, and the electric charges having a size in accordance with the level of the voltage between the gate electrode 23g and source electrode 23s of the transistor 23 is charged in the capacitor 24. In other words, in the selection period TSE of the i-th row, in the pixel circuits Di,1 to Di,n of the i-th row, the transistors 21 and 22 function to pass the gradation designating currents flowing through the signal lines Y1 to Yn through the transistors 23, the transistors 23 function to obtain the gate/source voltage in accordance with the current value of the forcibly flowing gradation designating current, and the capacitor 24 functions so as to hold the level of the gate/source voltage.
Here, in each current flowing path through the power scanning line Zi through which the gradation designating current flows, the transistors 23 of the pixel circuits Di,1 to Di,n, the transistors 21 of the pixel circuits Di,1 to Di,n, the signal lines Y1 to Yn, the transistors 31 of the switch circuits S1 to Sn, and the current terminals OT1 to OTn of the data driver 3, assuming that an electrostatic capacity of the current path to each of the signal lines Y1 to Yn from the source electrode 23s of each transistor 23 is C, electric charges Q charged in each current path at a voltage v are as follows:
Q=Cv (2); and
dQ=C·dv (3).
Assuming that the current value of the gradation designating current of the predetermined pixel Pi,j is Idata (Idata is constant in the selection period TSE), for a time dt required for bringing the voltage in the power scanning line Zi, the third transistor 23 of the pixel circuit Di,j, the first transistor 21 of the pixel circuit Di,j, the signal line Yj, the fourth transistor 31 of the switch circuit Sj, and the current terminal OTj of the data driver 3 into the stationary state, the following equation is established:
dt=dQ/Idata (4),
where dQ denotes a change amount of the electric charge of the current path in the time dt, and also denotes the change amount of the electric charge of the signal line Yj in the potential difference dv. As described above, as Idata decreases, dt lengthens. As dQ increases, dt lengthens.
As described above, in the selection period TSE of the i-th row, the sizes of the electric charges charged in the capacitors 24 of the pixel circuits Di,1 to Di,n of the i-th row are updated from the previous one scanning period TSC, and the current values of the driving currents flowing through the transistors 23 of the pixel circuits Di,1 to Di,n Of the i-th row are updated from the previous scanning period TSC.
Here, the potential in the arbitrary point in the transistor 23→the first transistor 21→the signal line Yj changes with internal resistances of the transistors 21, 22, 23 which change with the elapse of time. However, in the present embodiment, for the current value of the gradation designating current flowing through the transistor 23→the transistor 21→the signal line Yj, even when the internal resistances of the transistors 21, 22, 23 change with the elapse of time, the current value of the gradation designating current flowing through the transistor 23→the transistor 21→the signal line Yj is as desired.
Moreover, in the selection period TSE Of the i-th row, the common electrode of the organic EL elements Ei,1 to Ei,n of the i-th row is the reference voltage Vss. The charge voltage VCH the same as or lower than the reference voltage Vss is applied to the power scanning line Zi, therefore reverse bias voltages are applied to the organic EL elements Ei,1 to Ei,n of the i-th row, the current does not flow through the organic EL elements Ei,1 to Ei,n of the i-th row, and the organic EL elements Ei,1 to Ei,n do not emit the light. Moreover, by the gradation designating current flowing through the signal lines Y1 to Yn, the signal lines Y1 to Yn become stationary at a voltage lower than the charge voltage VCH. The charges to the capacitors 24 for passing the driving current through the organic EL elements Ei,1 to Ei,n are uniquely determined by the gradation designating current flowing through the data driver 3 from the signal lines Y1 to Yn.
Subsequently, in the end time tiR of the selection period TSE of the i-th row (i.e., the start time of the non-selection period TNSE of the i-th row), the selection scanning driver 5 ends the output of the pulse signal of the high level to the selection scanning line Xi, and the power scanning driver 6 ends the output of the pulse signal of the low level to the power scanning line Zi. That is, in the non-selection period TNSE till a start time t1 of the next selection period TSE Of the i-th row from an end time t2, the off-voltage Voff is applied to the gate electrodes 21g of the transistors 21 and the gate electrodes 22g of the transistors 22 of the pixel circuits Di,1 to Di,n of the i-th row by the selection scanning driver 5, and the power voltage VDD is applied to the power scanning line Zi by the power scanning driver 6.
Therefore, in the non-selection period TNSE of the i-th row, the transistors 21 of the pixel circuits Di,1 to Di,n of the i-th row obtain the off state, and the gradation designating current flowing through the signal lines Y1 to Yn from the power scanning line Zi is cut. Furthermore, in the non-selection period TNSE of the i-th row, in any of the pixel circuits Di,1 to Di,n of the i-th row, the second transistor 22 obtains the off state. The electric charges charged in the capacitor 24 in the previous selection period TSE of the i-th row are confined by the transistors 21 and 22. That is, in the non-selection period TNSE and the previous selection period TSE, the gate/source voltages VGS of the third transistor 23 become equal. Therefore, between the gate and source of the transistor 23, the voltage for passing the current having the current value equal to that of the gradation current flowing in the selection period TSE continues to be applied even over the non-selection period TNSE.
In the non-selection period TNSE of the i-th row, since the VDD satisfying the above condition equation (1) is applied from the power scanning line Zi, the third transistors 23 of the pixel circuits Di,1 to Di,n of the i-th row continuously pass the same driving current as the gradation designating current in the previous selection period TSE. Moreover, in the non-selection period TNSE of the i-th row, the common electrode of the organic EL elements Ei,1 to Ei,n of the i-th row has the reference voltage Vss. Moreover, the power scanning line Zi has the power voltage VDD higher than the reference voltage Vss. Therefore, forward bias voltages are applied to the organic EL elements Ei,1 to Ei,n of the i-th row. Furthermore, since each transistor 21 of the i-th row has the off state, the driving current does not flow through the signal lines Y1 to Yn via the transistors 21, and flows through the organic EL elements Ei,1 to Ei,n of the i-th row by the function of the transistor 23, and the organic EL elements Ei,1 to Ei,n emit the light.
That is, in the pixel circuits Di,1 to Di,n, the transistors 21 and 22 function to confine the electric charges of the capacitors 24 charged in accordance with the gradation designating current between the source and drain of each transistor 23 in the selection period TSE in the non-selection period TSE. Each transistor 21 functions so as to electrically disconnect the signal line Yj from the transistor 23 so that the driving current flowing through each transistor 23 does not flow through the signal lines Y1 to Yn in the non-selection period TSE. Furthermore, each capacitor 24 functions so as to charge the electric charges for holding the gate/source voltage of each transistor 23 set to be stationary when the transistor 23 passes the gradation designating current. Each transistor 23 functions so as to pass the driving current having the current value equal to that of the gradation designating current through the organic EL elements Ei,1 to Ei,n in accordance with the gate/source voltage held by each capacitor 24.
As described above, in the selection period TSE of the i-th row, the gradation designating current having the desired current value is forcibly passed through the transistors 23 of the pixel circuits Di,1 to Di,n of the i-th row, therefore the current value of the driving current through the organic EL elements Ei,1 to Ei,n is obtained as desired, and the organic EL elements Ei,1 to Ei,n emit the light at a predetermined gradation luminance.
When the current designating system is applied to the active matrix driving display apparatus, the current value of the driving current flowing through each organic EL element per unit time can be reduced. For this, in the non-selection period, with the gradation designating current having the current value equal to that of the driving current, a capacity C of a current path to the signal line Yj from the source 23s of the third transistor 23 has to be quickly charged.
Here, in the pixel Pi,j, the current value of the gradation designating current, which is passed through the signal line Yj in order to emit the light from the organic EL element Ei,j at a highest gradation luminance Lhsb in the non-selection period TNSE of the i-th row, is defined as Ihsb in the selection period TSE of the i-th row. Subsequently, in the pixel Pi+1,j, the current value of the gradation designating current, which is passed through the signal line Yj in order to emit the light from the organic EL element Ei+1,j at a lowest gradation luminance Llsb (additionally, the micro current flows, and the organic EL element Ei+1,j emits the light at a low luminance) in the non-selection period TNSE of the (i+1)st row, is defined as Ilsb in the selection period TSE of the (i+1)st row. Then, the following relation is obtained:
Ihsb>Ilsb (5).
The voltage applied to one end of the signal line Yj on the side of the data driver 3 is defined as Vhsb so that the signal line Yj obtains the stationary state at the current value Ihsb. The voltage applied to one end of the signal line Yj on the side of the data driver 3 is defined as Vlsb so that the signal line Yj obtains the stationary state at the current value Ilsb. Then, the following relation is obtained:
VCH>Vlsb>Vhsb (6)
That is, when the potential difference between the drain 23d and source 23s of the transistor 23 is VCH−Vlsb and low, the current value of the source/drain current flowing through the transistor 23 decreases to Ilsb. When the potential difference between the drain 23d and source 23s of the transistor 23 is VCH−Vhsb and high, the current value of the source/drain current flowing through the transistor 23 increases to Ihsb.
A charge amount Q1 accumulated in the current path to the signal line Yj from the source electrode 23s of the transistor 23 in order to modulate the lowest gradation luminance Llsb to the highest gradation luminance Lhsb is as follows:
Q1=C(Vlsb−Vhsb) (7),
the current value of the current flowing through the signal line Yj in order to accumulate the charge amount Q1 is Ihsb, and the charge amount Q1 can quickly be charged because of a relatively large current. C denotes the capacity of the current path.
On the other hand, a charge amount Q2 accumulated in order to modulate the highest gradation luminance Lhsb to the lowest gradation luminance Llsb is equation an absolute value of the charge amount Q1, but the current flowing through the signal line Yj at this time is Ilsb.
Here, in the constitution according to a comparative example in which the current/voltage switch portion 7 is removed from the display apparatus 1 of the present invention, the voltage Vhsb is applied in one end of the signal line Yj on the data driver 3 side in order to pass the gradation designating current having the current value Ihsb through the signal line Yj in the selection period TSE of the i-th row and to obtain the stationary current value Ihsb. Thereafter, the voltage Vlsb is applied in one end of the signal line Yj on the data driver 3 side in order to pass the gradation designating current having the current value Ilsb through the signal line Yj in the selection period TSE of the (i+1)st row and to obtain the stationary gradation designating current. In this case, since the current value Ilsb of the gradation designating current is remarkably small, as shown in
However, in the display apparatus 1 in which the current/voltage switch portion 7 is disposed as shown in
The reset voltage VR is set to at least a voltage higher than the highest gradation voltage Vhsb set to be stationary in accordance with the electric charges charged in the signal lines Y1 to Yn by the gradation designating current having the current value equal to that of the maximum gradation driving current IMAX flowing through the organic EL elements E1,1 to Em,n, when the organic EL elements E1,1 to Em,n emit the light at the brightest maximum gradation luminance LMAX in the selection period TSE. The reset voltage VR is preferably set to be not less than the intermediate voltage which has the intermediate value between the lowest gradation voltage Vlsb set to be stationary in accordance with the electric charges charged in the signal lines Y1 to Yn by the gradation designating current having the current value equal to that of the minimum gradation driving current IMIN flowing through the organic EL elements E1,1 to Em,n, when each of the organic EL elements E1,1 to Em,n has the minimum gradation luminance LMIN (additionally, the current value exceeds 0 A), and the highest gradation voltage Vhsb, more preferably the value equal to or more than the lowest gradation voltage Vlsb, most preferably the voltage equal to the charge voltage VCH.
In this manner, since the reset voltage VR is higher than at least the highest gradation voltage Vhsb, in the reset period, the potential difference between the source and drain of the transistor 23 can be set to be lower than VCH−Vhsb. That is, the electric charges of the capacity C of the current path to the signal line Yj from the source electrode 23s of the third transistor 23 is charged so that the relatively low gradation driving current, that is, the relatively small gradation designating current can quickly be stationary, and the potential of the signal lines Y1 to Yn is quickly stationary at the reset voltage VR.
Moreover, when the selection period TSE of the (i+1)st row starts, in the same manner as in the i-th row, a selection scanning line Xi+1 and power scanning line Zi+1 are selected by the selection scanning driver 5 and power scanning driver 6, and further the fourth transistor 31 obtains the on state. Accordingly, in each column, the gradation designating current flows through the power scanning line Zi+1→the third transistor 23→the transistor 21→the signal line Y→the fourth transistor 31→the data driver 3. Thereafter, in the non-selection period TNSE of the (i+1)st row, in the same manner as in the i-th row, the organic EL elements Ei+1,1 to Ei+1,n of the (i+1)st row emit the light at the luminance gradation in accordance with the current value of each driving current.
Here, the time dt required for bringing the voltage in the power scanning line Zi+1, the transistor 23, the transistor 21, the transistor 31, and the data driver 3 into the stationary state by the gradation designating current in the selection period TSE of the (i+1)st row is represented by the above equations (2) to (4). If the current value of the gradation designating current flowing through the signal lines Y1 to Yn in the selection period TSE of the i-th row is large, and the current value of the gradation designating current flowing through the signal lines Y1 to Yn in the selection period TSE of the (i+1)st row is small like the current value Ilsb at a lowest gradation luminance Llsb time, the voltage for the signal lines Y1 to Yn to obtain the gradation designating current of the (i+1)st row is set to be stationary. Then dt lengthens as represented by the above equations (2) to (4), and there is possibility that dt is longer than the selection period TSE. Therefore, if the current value of the gradation designating current is small in the selection period TSE of the (i+1)st row as described above, for the display apparatus 1 in which the current/voltage switch portion 7 is not disposed, as shown in
However, since the current/voltage switch portion 7 is disposed in the display apparatus 1 of the present embodiment, the reset period TRESET is set immediately before the selection period TSE of the (i+1)st row. In order to set the signal lines Y1 to Yn to be stationary at the current value of the gradation designating current when the organic EL elements Ei+1,1 to Ei+1,n of the (i+1)st row emit the light at the low luminance, the reset voltage VR is applied so as to quickly charge the electric charges in the capacity C of the current path, and the potential of the signal lines Y1 to Yn quickly rises. Especially, when the reset voltage VR is set to a value in the vicinity of the charge voltage VCH or the lowest gradation voltage Vlsb, and even when the current of the low luminance such as the lowest gradation current Ilsb for the lowest gradation luminance Llsb is passed through the signal lines Y1 to Yn in the selection period TSE of the (i+1)st row, as represented by the above equations (2) to (4), the change amounts of the electric charges of the signal lines Y1 to Yn in the reset period TRESET and in the selection period TSE of the (i+1)st row can be minimized.
Therefore, even when the gradation designating current of the (i+1)st row is the lowest gradation current Ilsb for the lowest gradation luminance Llsb, the signal lines Y1 to Yn obtain the stationary state at the lowest gradation voltage Vlsb in the selection period TSE of the (i+1)st row. The electric charges can be charged in the capacitor 24 in accordance with the current value of the gradation designating current in the selection period TSE, and the luminance gradation of the pixel can quickly be updated.
Moreover, in the same pixel Pi,j, the capacitor 24 is charged with a large charge amount to obtain the high gradation luminance in the previous scanning period TSC (or the previous emission period TEM). In the state, when the charge amount of the capacitor 24 is reduced to update the luminance to the low gradation luminance in the next scanning period TSC, that is, when the current path varies to the low gradation high voltage controlled by the micro gradation designating current from the high gradation low voltage controlled by the large gradation designating current, the current by the reset voltage VR is passed through the signal lines Y1 to Yn immediately before. Accordingly, the electric charges of the current path are shifted on the low gradation high voltage side. Therefore, when the signal lines Y1 to Yn and the capacitor 24 are regarded as one capacitor, the charge amount of the capacitor can be brought close to a low gradation side before the selection period TSE. That is, the potential of the capacitor 24 and signal lines Y1 to Yn can quickly be stationary so as to quickly charge the electric charges in each capacitor 24 in accordance with the low gradation designating current, even when the current value of the desired low gradation designating current is small.
Therefore, the voltage of one pole of each capacitor 24 of the pixels P+1,1 to Pi+1,n in the selection period TSE of the (i+1)st row and the potential of the signal lines Y1 to Yn quickly obtain the stationary state without depending on the current value of the gradation designating current. Therefore, with any gradation, the current value of the driving current in the emission period TEM (non-selection period TNSE) is the same as that of the designated current of the previous selection period TSE, and the organic EL elements Ei+1,1 to Ei+1,n emit the light at the desired emission luminance. In other words, without lengthening the selection period TSE of each row, the organic EL element Ei,j emits the light at the desired luminance. Therefore, the display screen does not blink, and the display quality of the display apparatus 1 can be raised.
The organic EL display panel 102 includes: the transparent substrate 8; the display portion 4 in which the image is substantially displayed; the selection scanning driver 5 disposed around the display portion 4; the power scanning driver 6; and a current/voltage conversion portion 107, to form the basic constitution. These circuits 4 to 6, 107 are formed on the transparent substrate 8. The display portion 4, selection scanning driver 5, power scanning driver 6, and transparent substrate 8 are the same as in the display apparatus 1 of the first embodiment. Therefore, even with the organic EL display 101 of the second embodiment, the voltage application timing by the selection scanning driver 5, the voltage application timing by the power scanning driver 6, the update of the pixels P1,1 to Pm,n, and the gradation representation of the pixels P1,1 to Pm,n are the same as in the display apparatus 1 of the first embodiment.
In the current/voltage conversion portion 107, the switch circuits Sj to Sn constituted of the fourth transistor 31 and fifth transistor 32 are disposed for each column. Additionally, current mirror circuits M1 to Mn and transistors U1 to Un and transistors W1 to Wn control the current mirror circuits M1 to Mn are disposed. One end of the current/voltage conversion portion 107 is connected to the signal lines Y1 to Yn, and the other end is connected to the shift register 103.
The current mirror circuit Mj is constituted of a capacitor 30 and two MOS type transistors 61, 62. The transistors 61, 62, 31, 32, U1 to Un, and W1 to Wn are field-effect thin film transistors of the MOS type, especially a-Si transistors in which amorphous silicon is used as a semiconductor layer, but may also be a p-Si transistor in which polysilicon or monocrystalline silicon is used in the semiconductor layer. The structures of the transistors 31, 32, U1 to Un, and W1 to Wn may also be of an inverse stagger type or coplanar type. In the following, the transistors 61, 62, 32, U1 to Un, and W1 to Wn will be described as the field-effect transistors of the N channel type, and the transistor 31 will be described as the field-effect transistor of the P channel type.
A channel length of the transistor 61 is the same as that of the transistor 62, and a channel width of the transistor 61 is longer than that of the transistor 62. That is, a channel resistance of the transistor 62 is higher than that of the transistor 61. For example, the channel resistance of the transistor 62 is ten times that of the transistor 61. In this manner, when the channel resistance of the transistor 62 is higher than that of the transistor 61, the channel lengths of the transistors 61 and 62 may not be the same.
Each column will be described. For the current mirror circuit Mj, the drain electrode of the transistor 61 is connected to the source electrode of the transistor Wj, and the gate electrodes of the transistors 61 and 62 are connected to the source electrode of the transistor Uj, and also to one pole of the capacitor 30. The drain electrode of the transistor 62 is connected to the source electrode of the transistor 31. The source electrodes of the transistors 61 and 62 are connected to each other, also to the other pole of the capacitor 30, and further to a low voltage input terminal 142 of a low current/voltage switch portion VCC at a constant level. The low current/voltage switch portion VCC of the low voltage input terminal 142 is lower than the reference voltage Vss, further lower than the charge voltage VCH, and for example, −20 [V].
In the j-th column, the drain electrodes of the transistors 31, 32 are both connected to the signal line Yj, and the gate electrodes of the transistors 31, 32 are both connected to the switch signal input terminal 140. The source electrode of the transistor 32 of each column is connected to the reset voltage input terminal 141.
The gate electrodes of the transistors Uj and Wj are connected to each other, and connected to an output terminal Rj of the shift register 103. The drain electrodes of the transistors Uj and Wj are connected to each other, and connected to a common gradation signal input terminal 170.
The shift register 103 shifts the pulse signal based on the clock signal from the outside, successively outputs the pulse signal of an on level to an output terminal Rn from output terminal R1 in order (the output terminal R1 is next to the output terminal Rn), and accordingly successively selects the current mirror circuits M1 to Mn. One shift period of the shift register 103 is shorter than that of the selection scanning driver 5 or the power scanning driver 6. While the selection scanning driver 5 or power scanning driver 6 shifts the pulse signal to the (i+1)st row from the i-th row, the shift register 103 shifts the pulse signal for one row to the output terminal Rn from output terminal R1 in order, and outputs n pulse signals of the on level.
The gradation signal input terminal 170 outputs of the gradation signal of an external data driver, and this gradation signal is set such that the current mirror circuits M1 to Mn successively selected by the pulse signal of the shift register 103 pass the gradation designating current having the current value in accordance with the gradation. By the gradation designating current, in the selection period TSE, the current in accordance with the luminance gradation of the organic EL elements E1,1 to Em,n is passed between the source and drain of the transistor 23 and through the signal lines Y1 to Yn. Accordingly, in the non-selection period TNSE (emission period TEM) the current flows between the source and drain of the transistor 23 and through the organic EL elements E1,1 to Em,n in accordance with the luminance gradation. The gradation designating current may also be an analog or digital signal, and is inputted into the drain electrodes of the transistors U1 to Un and W1 to Wn at a timing at which the pulse signal of the on level is inputted from the output terminals R1 to Rn of the shift register 103. The period of the gradation designating current for one row is shorter than one shift period of the selection scanning driver 5 or power scanning driver 6. While the selection scanning driver 5 or power scanning driver 6 shifts the pulse signal to the (i+1)st row from the i-th row, n gradation designating currents are inputted.
The switch signal φ is inputted into the switch signal input terminal 140 from the outside. The period of the switch signal φ is the same as one shift period of the selection scanning driver 5 or power scanning driver 6. A timing when the switch signal φ of the on level of the transistor 31 is inputted is a time at which the selection scanning driver 5 or power scanning driver 6 outputs the on-level pulse signals of the transistors 21, 22. Therefore, while the selection scanning driver 5 or power scanning driver 6 shifts to the m-th row from the first row, m on-level voltages of the switch signal φ are inputted.
When the gradation signal is outputted from the gradation signal input terminal 170, the voltages are applied to the drain electrode and gate electrode of the transistor 61, and the current flows between the drain and source of the transistor 61. At this time, the current also flows between the drain and source of the transistor 62. Here, the channel resistance of the transistor 62 is higher than that of the transistor 61, and the gate electrode of the transistor 62 has the same voltage level as that of the gate electrode of the transistor 61. Therefore, the current value of the current between the drain and source of the transistor 62 is smaller than that of the current between the drain and source of the transistor 61. Concretely, the current value of the current between the drain and source of the transistor 62 is substantially a value (product) obtained by multiplying a ratio of the channel resistance of the transistor 62 to that of the transistor 61 by the current value of the current between the drain and source of the transistor 61. The current value of the current between the drain and source of the transistor 62 is lower than that of the current between the drain and source of the transistor 61. Therefore, the micro gradation designating current flowing through the transistor 62 can easily be gradated/controlled. The ratio of the channel resistance of the transistor 62 to that of the transistor 61 will hereinafter be referred to as a current decrease ratio.
Next, the operation of the display apparatus 101 constituted as described above will be described. In the same manner as in the first embodiment, as shown in
On the other hand, as shown in
Here, when the shift register 103 outputs the pulse signal of the on level to the output terminal Rj, the gradation signal input terminal 170 inputs the gradation signal of the level indicating the gradation luminance of the i-th row and j-th column. At this time, since the transistors Uj and Wj of the j-th column have the on state, the gradation signal of the current value indicating the value for the gradation luminance of the i-th row and j-th column is inputted into the current mirror circuit Mj, the transistors 61 and 62 obtain the on state, and the electric charges having the size in accordance with the current value of the gradation signal is charged in the capacitor 30. That is, the transistors Uj and Wj function so as to take the gradation signal into the current mirror circuit Mj at a selection time of the j-th column.
When the transistor 61 obtains the on state, in the current mirror circuit Mj, the current flows through the gradation signal input terminal 170→the transistor 61→the low voltage input terminal 142. The current value of the current flowing through the gradation signal input terminal 170→the transistor 61→the low voltage input terminal 142 follows that of the gradation signal.
At this time, since the level of the switch signal input terminal 140 corresponds to the off level of the transistor 31, the transistor 31 of the j-th column has the off state, and the gradation designating current flowing through the current mirror circuit Mj and signal line Yj does not flow.
Subsequently, when the shift register 103 outputs the pulse signal to the output terminal Rj+1, the gradation signal of the current value indicating the value for the gradation luminance of the i-th row and (j+1)st column is inputted. In the same manner as in the j-th column, the electric charges having the size in accordance with the current value of gradation signal is charge in the capacitor 30 of the (j+1)st column. At this time, even when the transistors Uj, Wj of the j-th column obtain the off state, the electric charges charged in the capacitor 30 of the j-th column is confined by the transistor Uj, and therefore the transistors 61 and 62 of the j-th column maintain the on state. That is, the transistor Uj functions so as to hold the gate voltage level in accordance with the current value of the current of the gradation signal at the selection time of the j-th column even at the non-selection time of the j-th column.
As described above, when the shift register 103 shifts the pulse signal, the electric charges having size in accordance with the current value of the gradation signal is successively charged into the capacitor 30 of the n-th column from the capacitor 30 of the first column. When the charging into the capacitor 30 of the n-th column ends, the shift of the shift register 103 once ends, the switch signal φ of the switch signal input terminal 140 switches to the off level from the high level. All the transistors 31 simultaneously obtain the on state, and all the transistors 32 obtain the off state. At this time, since the charges are charged in the capacitors 30 of all the columns, the transistors 61, 62 have the on state. Moreover, since this time is the selection period of the i-th row, the gradation designating current flows through the power scanning line Zi→the transistor 23→the transistor 21→the signal lines Y1 to Yn→the transistor 62→the low voltage input terminal 142 in all the pixel circuits Di, to Di,n of the i-th row. At this time, in any column of the first to n-th column, by the function of the current mirror circuit Mj, the current value of the gradation designating current flowing in the direction of the power scanning line Zi→the transistor 23→the transistor 21→the signal lines Y1 to Yn→the transistor 62→the low voltage input terminal 142 is a value obtained by multiplying the current value of the current flowing in the direction of the gradation signal input terminal 170→the transistor 61→the low voltage input terminal 142 by the current decrease ratio of the current mirror circuit Mj.
In any of the signal lines Y1 to Yn, the relatively large gradation designating current having the high luminance is passed in the selection period TSE of the previous row, the electric charges are accumulated in the capacity of the current path to the signal line Yj from the source 23 of the transistor 23, and the potential lowers. In this case, even when the current value of the gradation designating current flowing in the next selection period TSE is small, the potential of the current path is high by the reset voltage VR applied in the previous reset period TRESET. Therefore, it is possible to quickly set the potential of the signal lines Y1 to Yn to be stationary at the potential in accordance with the gradation sink current.
Subsequently, the pulse signals of the selection scanning driver 5 and power scanning driver 6 shift to the (i+1)st row, and the non-selection period TSE of the i-th row is obtained. In the same manner as in the first embodiment, the gradation luminance of the organic EL elements Ei,1 to Ei,n of the i-th row is updated.
Subsequently, the switch signal input terminal 140 reaches the high level, and the shift register 103 similarly repeats the shift of the pulse signal to the n-th column from the first column. Accordingly, to update the gradation luminance of the organic EL elements Ei+1,1 to Ei+1,n of the (i+1)st row, the electric charges are successively charged in the capacitors 30 of the n-th column from the first column.
In the second embodiment, since the current mirror circuit Mj is disposed outside the display portion 4, the number of transistors disposed for each pixel can be minimized, and the drop of numerical aperture of the pixel can be inhibited. Since the current mirror circuit Mj is disposed, and even when the gradation signal slightly deviates from the current value to be originally outputted because of ambient noises or parasitic capacities in the gradation signal input terminal 170, the deviation of the gradation designating current value of the signal line Yj is minimized according to the current decrease ratio, and further the deviation of the luminance gradation of the organic EL element E can be suppressed.
In the embodiment shown in
In the above embodiment, the switch circuits S1 to Sn include CMOS structures of N channel and P channel transistors, but as shown in
Furthermore, the channel type of the transistor of the current/voltage conversion portion 107 is the same as that of the transistors 21 to 23 in the display portion 4. Then, the transistor in the current/voltage conversion portion 107 can collectively be formed with the transistors 21 to 23 in the display portion 4. If the transistor of the same channel type as that of the transistors 21 to 23 of the display portion 4 is partially disposed in the current/voltage conversion portion 107, needles to say, the transistors can simultaneously be formed.
In a display apparatus 201 shown in φ (
is logic negation) as a reverse signal of the switch signal φ is inputted.
As shown in φ, functions as a switch for passing a micro gradation designating current to the power scanning lines Z1 to Zm, transistor 23, transistor 21, signal lines Y1 to Yn, transistor 62, and low voltage input terminal 142, and obtains the off state in the reset period TRESET. The transistor 132 obtains the off state in the selection period TSE by the switch signal φ, obtains the on state in the reset period TRESET, and functions as the switch for applying the reset voltage VR to the signal lines Y1 to Yn. Also in the switch circuits S1 to Sn shown in
In the embodiment shown in
The present invention is not limited to the above-described embodiments, and may variously be modified and changed in design without departing from the scope of the present invention.
For example, in the display apparatus 1, the gradation luminance is designated in the pixel Pi,j by the current value of the sink current extracted from the pixel Pi,j. However, conversely, the current may be passed through the pixel Pi,j from the signal line Yj, and the pixel Pi,j may emit the light at the gradation luminance in accordance with the current value of the current. This display apparatus of the active matrix driving system may also be used.
Even in this case, the switch circuit passes the designated current of the data driver through the signal line in the selection period of each row, and the constant voltage of the constant level is applied to the signal line in the reset period between the selection periods. However, when the luminance gradation is higher, the signal line voltage is high and the signal line current is large. When the luminance gradation is low, the signal line voltage is low and the signal line current is small. Therefore, a potential relation is obtained such that the voltages VR, Vlsb, Vhsb are vertically revered in
Further in this case, the circuit of the pixel Pi,j may appropriately be changed. When the scanning line is selected, the designated current flowing through the signal line is passed through the pixel circuit to convert the current value of the designated current to the voltage level. When the scanning line is not selected, the designated current flowing through the scanning line is cut. The voltage level converted when the scanning line is not selected is held. Moreover, the pixel circuit for passing the driving current having the level in accordance with the held voltage level through the organic EL element is preferably disposed around each organic EL element.
In the embodiment, the organic EL element is used as the light emitting element. However, for example, there may be used a light emitting element in which the current does not flow when the reverse bias voltage is applied while it flows when the forward bias voltage is applied, and which may emit the light at the luminance in accordance with the size of the current flowing therein. Examples of the light emitting elements may include a light emitting diode (LED) element other than the organic EL element.
According to the present invention, when the pixel of the predetermined row is selected, the gradation current flows through each signal line. Even when a difference between the voltage set to be stationary by the gradation current flowing through the signal line for the pixel of the previous row and the voltage to be set to be stationary by the gradation current passed through the signal line for the pixel of the next row is large, and the current value of the gradation current for the next pixel is small, the reset voltage is applied to the signal line before the next row, thereby the signal line can quickly be set to be stationary at the voltage in accordance with the gradation current for the next row.
Therefore, after the next scanning line is selected, the current value of the driving current flowing through the light emitting element is the same as that of the designated current, and the light emitting element emits the light at the desired luminance. That is, without lengthening the period in which each scanning line is selected, the light emitting element emits the light at the desired luminance. Therefore, the display screen does not blink, and the display quality of the display apparatus is high.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2002-180284 | Jun 2002 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP03/07430 | 6/11/2003 | WO | 00 | 3/11/2004 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO04/001714 | 12/31/2003 | WO | A |
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