DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the invention is presented below in the form of a light phase modulator based on the GAA (Gate All Around) architecture. This embodiment is illustrated by the following figures:
FIG. 1 is a schematic view of a gate-all-around transistor according to the invention. a) 3D fly's eye view; b) Cross section; c) and d) lateral cross sections showing possible doping configuration.
FIG. 2 shows different possible architectures of the invention. a) GAA transistor; b) Side wall transistor; c) Double gate transistor; d) Tri-gate transistor; e) Vertical GAA transistor; f) Triangular GAA; g) Polygonal GAA; h) Ovoid GAA.
FIG. 3 shows an example of the invention when developed in the three-gate configuration.
FIG. 4 shows an example of a final mask layout for the fabrication of the invention shown in FIG. 3.
FIG. 5 shows an example of use of the invention in the cavity of a resonant optical structure to form an intensity modulator.
FIG. 6 illustrates a process which can be used for a tri-gate implementation according to the invention.
The following numerical references are used in the figures:
- 101: Conductive wrapping
- 102: Gate dielectric
- 103: Silicon core
- 200: Silicon core
- 201: Conductor
- 202: Insulator
- 300: Silicon layer
- 301: First dielectric
- 302: Second dielectric (might be identical to the first dielectric)
- 303: Heavily doped implants—hole/electron source
- 304: Conductive wrapping
- 305: Gate dielectric
- 306: Bragg grating mirror
- 307: Substrate
- 308: Contact
- 401: Silicon waveguiding layer
- 402: Conductive wrapping
- 403: Heavily doped implants—hole/electron source
- 404: Contact
- 501: GAA modulator
- 502: Bragg grating mirror
- 503: Silicon layer
- 504: Silicon ring resonator
FIG. 1
a) shows a crystalline Si core which is wrapped in a SiO2 gate oxide and in a conductive material as gate to form a MOSFET transistor with the gate completely wrapping the silicon photonic wire channel. FIG. 1b) shows the cross section of this device with a typical possible embodiment of the device. Any combination of thicknesses of the three materials giving tguide<1 μm is to be considered a possible optional embodiment of the invention. FIG. 1c) and FIG. 1d), show possible doping conditions of the device. Connecting both p+(n+) regions to ground and giving a bias voltage Vg on the n+(p+) region (FIGS. 1c and 1d), the structure is in a capacitive configuration resulting in very high frequency operation together with very low power consumption and negligible parasitic heating effects. In a possible embodiment of the device the conductive wrapping can be doped polycrystalline silicon.
Different architectures are possible in the fabrication of a multi-gate transistor for light phase modulation. FIG. 2 shows the cross sections of some of the most useful possible architectures schemes. FIG. 2a) is a GAA transistor configuration similar to the one described in detail in FIG. 1. FIG. 2b) is a side wall transistor configuration and FIG. 2c) is a double gate (DG) configuration. FIG. 2d) is a tri-gate (or π-gate) configuration while FIG. 2e) is a vertical GAA structure. FIG. 2f) shows the cross section of a possible triangular shaped GAA transistor, FIG. 2g) shows a possible polygonal shaped GAA transistor and FIG. 2h) shows a possible round or oval configuration. All those configurations are to be considered possible embodiments of the invention and also two or more combinations of those are to be considered possible embodiments of the invention (for example a triangular double gate or a rhomboidal tri-gate and so on).
In an example of the invention the transistor can be manufactured in a tri-gate configuration with the following process flow. FIG. 3 shows the a possible final sketch of the invention using a SOI wafer with 1 μm thick buried oxide and 0.34 μm thick silicon device layer, p-type doping are about 5×1014−1015.
In FIG. 4 a possible mask layout for the realization of the invention in the form represented in FIG. 3 is presented.
In order to create an intensity modulator the phase modulator must be placed in a resonant structure, either by etching Bragg gratings at either end, which could for example be done by a FIB at the end of processing, or by including an additional e-beam step. Alternatively, the modulator can be placed in the ring, of a ring resonator as illustrated in FIG. 5.
FIG. 6 illustrates a process which can be used for a tri-gate implementation according to the invention. For simplicity, only the fabrication of the phase modulator and a possible p+-connection to the core are represented. In fact, at least two source/drain connections are required as shown in the figures, and the final modulator might consist of several series-connected modules.
The process is defined by the following steps:
FIG. 6A
1. Protective oxide layer at surface
2. Photolithography.
3. P+-implantation of the “source” and “drain” regions. 1021 at surface, 1019 in depth
4. Thermal activation of dopants.
5. Removal of resist.
FIG. 6B
1. Deposition of hard mask
2. Photolithography.
3. Dry etching of hard mask.
4. Dry etching of silicon
FIG. 6C
1. Thermal oxidation of the wafer, in order to reduce roughness after dry etching of the surface.
FIG. 6D
1. Photolithography—opening of gate region.
2. Wet etch of thermal oxide and LTO mask.
FIG. 6E
1. Removal of resist.
2. Gate oxide ˜10 nm.
FIG. 6F
1. Deposition of poly-silicon 50-100 nm.
2. Poly-oxidation or deposition of protecting oxide.
3. Blanket doping of poly silicon
4. Doping ˜1019.
FIG. 6G
1. Photolithography.
2. Dry etch of poly.
3. Isolating oxide
4. Photolithography.
5. Metallization.
6. Photolithography—metal lines.
It should be noted that the present invention is not limited to the above cited embodiment.
Patent Application
20080030838
