The present disclosure relates generally to computing devices that include input/output (I/O) ports. More specifically, the present disclosure relates to systems and methods for limiting an in-rush current that may be output via an I/O port of a computing device.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Over the years, certain technology, such as Universal Serial Bus (USB) technology, has commonly been used to transfer data between two computing devices. In addition to transferring data, USB technology has also been capable of outputting a limited amount of power to USB devices via a USB port. As more users rely on USB ports to provide power for their USB devices, USB ports are now designed to provide increased power output to meet this increased demand
In recent years, a USB Power Delivery (PD) specification has called for providing more flexible power delivery, as well as data transmission, over a single cable. In addition to providing more flexible power deliver (e.g., increased power output), the USB PD specification aims at operating within the existing USB ecosystem, which includes USB 1.x, 2.0, 3.0, and 3.1 devices with A, B, and C-type connections. For example, the USB PD specification includes a power output capability of 100 watts with up to 5 amps of current. To effectively provide power output signals at these higher power levels, devices that output these elevated amounts of power may use a certain amount of input capacitance (e.g., greater than 10 μF) to improve the quality of a voltage signal output to other devices. For instance, USB ports disposed on various types of computing devices may use a certain amount of capacitance to filter alternating current (AC) noise from direct current (DC) voltage signals output to connected USB devices. However, when certain types of USB devices are coupled to the USB port, the input capacitance of the USB port may cause a certain amount of in-rush current (e.g., greater than 100 mA) to be output to the connected USB device when the USB device is initially coupled to the USB port. In some cases, the in-rush current associated with the input capacitance may exceed maximum load properties specified for the connected USB device or the cable coupling the USB device to the USB port. As such, although the increased power capabilities provided by the USB PD specification should allow users to have more flexible access to power sources to power various types of devices, older USB devices may not be equipped to receive such levels of power.
A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects that may not be set forth below.
As discussed above, the Universal Serial Bus Power Delivery (USB PD) specification calls for providing higher amounts of power (e.g., 100 watts) via a USB port, as compared to previous USB specifications (e.g., 4.5 watts for USB 3.0). However, often times, outputting these elevated amounts of power via the USB port may also include outputting a certain amount of in-rush current (e.g., greater than 100 mA) to a USB device when the USB device is initially coupled to the USB port. In some cases, the in-rush current associated with the input capacitance may exceed maximum load properties specified for the connected USB device or the cable coupling the USB device to the USB port, and thus may damage the USB device, the cable, or both.
To address these problems, a current limiting circuit may be coupled to the input capacitance of the USB port to limit the in-rush current that may be output to the connected USB device. For example, a current-limiting resistor may be coupled in series with the input capacitance to limit the amount of in-rush current output to the USB device. In addition to the current limiting resistor, a switch may be coupled in parallel with the current-limiting resistor to allow current to bypass the current-limiting resistor after the in-rush current has passed. As such, the switch may be open during the in-rush current event and closed after the in-rush current event has passed. After the switch is closed and the current bypasses the current-limiting resistor via the switch, the input capacitance may again filter AC noise from the DC voltage signal output by the USB port. By including the circuitry to limit the in-rush current present at the USB port while maintaining the presence of the input capacitance, the USB port may output power that may induce in-rush currents that exceed the specifications of older USB devices without causing damage to these devices. Moreover, since the current-limiting resistor is effectively removed from the circuit after the in-rush current event has passed, the input capacitance may still be utilized to provide filtered voltage signals to connected devices.
Various refinements of the features noted above may exist in relation to various aspects of the present disclosure. Further features may also be incorporated in these various aspects as well. These refinements and additional features may exist individually or in any combination. For instance, various features discussed below in relation to one or more of the illustrated embodiments may be incorporated into any of the above-described aspects of the present disclosure alone or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of embodiments of the present disclosure without limitation to the claimed subject matter.
Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:
One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “embodiments” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.
As discussed above, the Universal Serial Bus Power Delivery (USB PD) specification provides that power up to 100 watts may be delivered or output via a USB port for various devices capable of coupling to the USB port. However, certain types of USB devices (e.g., USB 1.0) may not be designed to receive the amount of in-rush current that may be provided based on an input capacitance at the USB port when the USB device is initially connected to the USB port. That is, this in-rush current may cause damage to the connected USB device or to the cable connecting the USB device to the USB port.
With the foregoing in mind, a current-limiting resistor may be coupled in series with the input capacitance of a USB port to limit the amount of in-rush current provided to a connected USB device. In addition to the current limiting resistor, a switch, such as a MOSFET transistor, may be coupled parallel with the current-limiting resistor to allow current to bypass the current-limiting resistor after the in-rush current has passed. To ensure that the switch is closed after the in-rush current event has passed, the gate of the transistor may be coupled to a resistor-capacitor (RC) filter that may be designed to provide the gate with a threshold voltage when the in-rush current is expected to have passed. As such, the switch will close after the in-rush current event, thus allowing the remaining current to bypass the current-limiting resistor via the switch. As a result, the in-rush current output via the USB port may be limited to a specified value based on the value of the current-limiting resistance. Moreover, the input capacitor at the USB port may still be employed to remove AC noise from a DC voltage signal output by the USB port after the in-rush current event has passed, thereby maintaining a quality of the power signal output by the USB port.
By way of introduction,
As shown in
Before continuing further, it should be noted that the system block diagram of the device 10 shown in
Considering each of the components of
In one embodiment, one or more of the I/O ports 12 may include current-limiting circuitry 30, as discussed above. Additional details regarding the current-limiting circuitry 30 and the manner in which it may reduce the amount of in-rush current received by a device connected to the I/O ports 12 will be discussed with reference to
The input structures 14 may enable user input to the electronic device, and may include hardware keys, a touch-sensitive element of the display 28, and/or a microphone. The processor(s) 16 may control the general operation of the device 10. For instance, the processor(s) 16 may execute an operating system, programs, user and application interfaces, and other functions of the electronic device 10. The processor(s) 16 may include one or more microprocessors and/or application-specific microprocessors (ASICs), or a combination of such processing components. For example, the processor(s) 16 may include one or more instruction set (e.g., RISC) processors, as well as graphics processors (GPU), video processors, audio processors and/or related chip sets. As may be appreciated, the processor(s) 16 may be coupled to one or more data buses for transferring data and instructions between various components of the device 10. In certain embodiments, the processor(s) 16 may provide the processing capability to execute an imaging applications on the electronic device 10, such as Photo Booth®, Aperture®, iPhoto®, Preview®, iMovie®, or Final Cut Pro® available from Apple Inc., or the “Camera” and/or “Photo” applications provided by Apple Inc. and available on some models of the iPhone®, iPod®, and iPad®.
A computer-readable medium, such as the memory 18 or the nonvolatile storage 20, may store the instructions or data to be processed by the processor(s) 16. The memory 18 may include any suitable memory device, such as random access memory (RAM) or read only memory (ROM). The nonvolatile storage 20 may include flash memory, a hard drive, or any other optical, magnetic, and/or solid-state storage media. The memory 18 and/or the nonvolatile storage 20 may store firmware, data files, image data, software programs and applications, and so forth.
The network device 22 may be a network controller or a network interface card (NIC), and may enable network communication over a local area network (LAN) (e.g., Wi-Fi), a personal area network (e.g., Bluetooth), and/or a wide area network (WAN) (e.g., a 3G or 4G data network). The power source 28 of the device 10 may include a Li-ion battery and/or a power supply unit (PSU) to draw power from an electrical outlet or an alternating-current (AC) power supply.
The display 26 may display various images generated by device 10, such as a GUI for an operating system or image data (including still images and video data). The display 26 may be any suitable type of display, such as a liquid crystal display (LCD), plasma display, or an organic light emitting diode (OLED) display, for example. Additionally, as mentioned above, the display 26 may include a touch-sensitive element that may represent an input structure 14 of the electronic device 10. The imaging device(s) 28 of the electronic device 10 may represent a digital camera that may acquire both still images and video. Each imaging device 28 may include a lens and an image sensor capture and convert light into electrical signals.
As mentioned above, the electronic device 10 may take any number of suitable forms. Some examples of these possible forms appear in
The notebook computer 40 may include an integrated imaging device 28 (e.g., a camera). In other embodiments, the notebook computer 40 may use an external camera (e.g., an external USB camera or a “webcam”) connected to one or more of the I/O ports 12 instead of or in addition to the integrated imaging device 28. In certain embodiments, the depicted notebook computer 40 may be a model of a MacBook®, MacBook® Pro, MacBook Air®, or PowerBook® available from Apple Inc. In other embodiments, the computer 40 may be portable tablet computing device, such as a model of an iPad® from Apple Inc.
The electronic device 10 may also take the form of portable handheld device 60 or 70, as shown in
The display device 26 may display images generated by the handheld device 60 or 70. For example, the display 26 may display system indicators that may indicate device power status, signal strength, external device connections, and so forth. The display 28 may also display a GUI 52 that allows a user to interact with the device 60 or 70, as discussed above with reference to
Having provided some context with regard to possible forms that the electronic device 10 may take, the present discussion will now focus on the current-limiting circuitry 30 shown in
With the foregoing in mind,
For certain power applications (e.g., as may be specified by the USB PD specification), when certain versions of USB devices (e.g., USB 1.0 or 2.0 devices or cables) connect to the electrical nodes 92, the in-rush current provided to the connected USB devices due to the capacitance of the capacitor 82 may exceed the respective specifications of the connected USB devices. That is, with increased power being provided via the electrical nodes 92 as compared to previous versions of USB ports, the capacitance of the capacitor 82 may be larger than used in previous USB port circuitry. This increased capacitance may enable the current-limiting circuitry 30 to filter additional noise due to the increase power output and improve the quality of the power being output via the electrical nodes 90. However, along with the improved filtering ability provided by the larger capacitor 82, the capacitor 82 may also store more energy as compared to capacitors used in previous versions of the USB ports. As such, when devices are coupled to the electrical nodes 92, the connected devices may be subject to more in-rush current from the stored energy of the capacitor 82 as compared to the smaller capacitors used in the previous versions of the USB ports. Since some versions of USB devices are not designed receive these increased amounts of current (e.g., 5 amps) that may be induced by the capacitor 82, these USB devices may be damaged when connected to the electrical nodes 92 having the capacitor 82 and the application circuit 90.
With the foregoing in mind, the current-limiting circuitry 30 may limit the amount of capacitive load that a device connected to the I/O port 12 may be exposed to when initially connecting to the I/O port 12 (e.g., plugging into the I/O port 12). In other words, the current-limiting circuitry 30 may limit the initial current output via the capacitor 82 for a period of time until the stored energy of the capacitor 82 has been dissipated. After the excess charge of the capacitor 82 has been dissipated, the current-limiting circuitry 30 may cease operation, such that the capacitor 82 may perform its designed function of filtering the output of the application circuit 90. As a result, the capacitor 82 may be employed to improve the quality of power or voltage output via the application circuit 90 while the in-rush current received by a device connected to the I/O port 12 may be limited when necessary.
To limit the in-rush current received by the connected device, the current-limiting resistor 84 may be coupled in series with the capacitor 82 as shown in
Also, it should be noted that in some embodiments, the application circuit 90 may be capable of outputting different voltages. In this case, the resistance value of the current-limiting resistor 84 may be determined using the largest voltage output capable of being output by the application circuit 90. As such, the in-rush current output via the capacitor 82 may still be limited to prevent damage from occurring on any device connected to electrical nodes 92.
Referring back to
To control the operation of the switch 86 such that the current-limiting resistor 84 is bypassed after the in-rush current has passed, the RC circuit 88 may be coupled to the gate of the switch 86 and designed to provide a threshold voltage to the gate after the in-rush current has passed. As such, the RC circuit 88 determines when to switch the switch 86 on and off. With this in mind, the RC circuit 88 of resistor 90 and capacitor 94 may be designed to have a time constant τ1 that is larger than a time constant τ0 associated with the current-limiting resistor 84 and the capacitor 82 circuit to ensure that the in-rush current event has passed. That is, the resistance and capacitance values of the RC circuit 88 may be selected such that the voltage at the capacitor 94 of the RC circuit 88 does not exceed the threshold voltage of the switch 86 until the in-rush current event associated with the capacitor 82 has ended.
The RC circuit 88 may also be sized such that the voltage of the gate of the switch 86 may not exceed the threshold voltage until the capacitor 82 is charged at or above 85%, 90%, 95%, or the like. At this time, the in-rush current event has likely passed and the capacitor 82 may be effectively used to improve a quality of voltage output by the application circuit 90. As such, the time period for the RC circuit 88 to output the threshold voltage to the gate of the switch 86 may be designed to be, for example, between 3τ0 and 5τ0. The time period for the RC circuit 88 to output the threshold voltage to the gate of the switch 86 may be designed to be greater than 2τ0, 3τ0, or any other suitable time that may correspond to when the in-rush current event has likely passed. Although the RC circuit 88 is described above as operating based on a certain percent charge of the capacitor 82 or designed using a range of time constants, it should be noted that the values described herein are subject to tolerances and should be not be limited to the values presented herein.
With the foregoing in mind, a non-limiting example related to the design of RC circuit 88 is provided below for reference. A 5V USB Type-C adapter (V1=5V) may desire an in-rush current to be limited to less than 10 mA. As such, the current-limiting resistor 84 (R1) may be sized as follows:
-ti R1=5V/10 mA=500Ω
If the capacitor 82 (C0) is a 47 μF capacitor, the time constant τ0 for the current-limiting resistor 84 and the capacitor 82 circuit is determined as follows:
τ0=(C0) R1=47 μF·500Ω=23.5 ms
With this in mind, the RC circuit 88, which is used to control the gate of the switch 86, may then be sized such that the gate of the switch 86 does not reach its threshold voltage prior to the capacitor 82 from being charged to some value (e.g., 95%). Assuming that the value is 95% charge of the capacitor 82, the time constant τ1 of the RC circuit 88 may be calculated to be 3τ0. Moreover, assuming that the threshold voltage is 0.9V (V0=0.9V), the time constant τ1 of the RC circuit 88 may be calculated as follows:
Accordingly, the resistance (R2) and the capacitance (C1) of the RC circuit 88 may be selected as R2=150 kΩ and C1=2.2 μF, thereby yielding a time constant τ1 of 330 ms as shown below.
τ1=R2*C1=150 lΩ*2.2 μF=330ms
It should be noted that the resistance value R1 for the current-limiting resistor 84, the time constant τ0 for the current-limiting resistor 84 and the capacitor 82 circuit, and the time constant τ1 of the RC circuit 88 calculated in the example provided above are minimum values. As such, when designing the RC circuit 88, it should be understood that the current-limiting resistor 84, the resistance (R2) of the RC circuit 88, and the capacitance (C1) of the RC circuit 88 may be sized to be greater than the values determined using the calculations provided above.
A simulation example of the behavior of the current-limiting circuitry 80 is shown on
Moreover, after the voltage is output via the electrical nodes 92, the voltage across the capacitor 94 (C1) increases according to curve 108. As the voltage across the capacitor 94 increases, the voltage across the capacitor 94 will eventually reach the threshold voltage (e.g., 0.9V) of the gate of the switch 86. As such, at time T1, the switch 86 may close and thus the current-limiting resistor 84 may be effectively removed from the current-limiting circuit 80. After the switch 86 closes, the capacitor 82 becomes fully charged and may thus cause a slight increase in in-rush current 109 as shown in the curve 102 after time T1.
Although the RC circuit 88 described above may be used to activate and deactivate the switch 86, other types of circuits may be used as well. For example, the current-limiting circuit described above may be implemented using a voltage divider and diodes used to dissipate stored energy of the capacitor 94. For example,
The zener diode 124 may limit a gate voltage provided to the switch 86. That is, the zener diode 124 may serve as a voltage clamp for the gate of the switch 86 to ensure that the gate-to-source voltage rating of the switch 86 is not exceeded. The diode 126 may dissipate power or current stored in the capacitor 94 and the capacitor 82 after the application circuit 90 stops outputting power or after a USB device disconnects from the electrical nodes 90. That is, the diode may provide a path for current dissipating from the capacitor 82 to flow, thereby discharging the capacitor 82.
With the foregoing in mind, when the application circuit 90 outputs a voltage and a device is initially coupled to the electrical nodes 92, the voltage provided to the capacitor 94 of the RC circuit 88 may be reduced according to the resistance values of the voltage divider 88. Generally, the RC circuit 88 may eventually output a voltage to the gate of the bypass switch 86 after a certain amount of time passes, such that the in-rush current output by the capacitor 82 has likely passed. As a protective feature to limit the voltage provided to the gate of the switch 86, the zener diode 124 may limit the voltage output by the voltage divider 122. Later, when the device is disconnected from the electrical nodes 92 or when the application circuit 90 stops outputting voltage, energy stored in the capacitor 82 and the capacitor 94 of the RC circuit 88 may be dissipated throughout the current-limiting circuitry 30A via the diode 126.
Although
It should be noted that the individual components (e.g., resistors R1, R2, R3, capacitor C1, RC circuit 88) of the current-limiting circuit 30, the current-limiting circuit 30A, and the current-limiting circuit 30B are not limited to the components described herein. Instead, other suitable components may be used to perform the same or similar functions of the components described with respect to
Regardless of the technology used to control the operation of the switch 86 of the current-limiting circuit 30,
At block 146, the current-limiting circuit 30 may wait for an in-rush current event to pass. That is, the current-limiting circuit 30 may use, for example, the RC circuit 88 to provide a threshold voltage to the gate of the switch 86 after an amount of time for the in-rush current event has passed. As discussed above, this amount of time may correspond to 3 to 5 times the time constant τ0 associated with the capacitor 82 and the current-limiting resistor 84, an amount of time to charge the capacitor 82 to some level, or the like. After the in-rush current event has passed, the current-limiting circuit 30 may, at block 148, send a signal to close the switch 86, thereby bypassing the current-limiting resistor 84 from the current-limiting circuit 30. As a result, the current-limiting resistor 84 may effectively limit the in-rush current to some maximum value and the capacitor 82 may be no longer be inhibited by the presence of the current-limiting resistor 84 after the in-rush current event has passed.
The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.