Patent Application
20120044730
This application claims priority under 35 U.S.C. §119 to European Patent Application No. 10173154.5 filed in Europe on Aug. 18, 2010, the entire content of which is hereby incorporated by reference in its entirety.
The present disclosure relates to inverter topologies, such as a solar inverter topology for supplying a grid.
A solar inverter is used to convert a DC voltage produced by solar cells into an AC voltage with high efficiency. Known generic inverter can use 2-level (line-to-neutral) topology, where an output is tied either to the positive pole or the negative pole of a DC link. The efficiency can be increased by using a 3-level (line-to-neutral) topology, where the output can be tied to three potentials: positive or negative pole of the DC link or a neutral point.
A solar inverter can also be used to minimize high-frequency common-mode voltages between the DC link and the protective ground. When these high-frequency common-mode voltages are present, high-frequency common-mode currents may flow through parasitic capacitances of the photovoltaic panels and possibly damage the photovoltaic panels. The minimizing of the common-mode voltage can therefore be important in photovoltaic inverter applications.
The publication A new neutral-point-clamped PWM inverter, A. Nabae, I. Takahashi, & H. Akagi discloses an NPC (Neutral Point Clamped) describes an inverter topology which can be used to minimize the generation of the harmful high-frequency common-mode voltage. The NPC inverter uses 3-level (line-to-neutral) modulation and can have 5-level (line-to-line) output voltage, where the output voltage is measured between two output lines.
To avoid the common-mode voltage, a “neutral point zero state” (zero state) can be used in the NPC inverters. In a zero state, the output lines have no connection to the DC link. In addition, the outputs can be tied to the same potential, which is the neutral point, in a neutral point zero state. The outer switches in the inverter legs are in a non-conducting state and the current flows through two inner switches and two diodes.
By using the neutral point zero state and 3-level (line-to-line) output, voltage generation the common-mode voltage can be eliminated. The use of a 3-level (line-to-neutral) modulation also increases efficiency compared to a 2-level (line-to-neutral) modulation.
However, one of the disadvantages associated with the above arrangement is that there are always four power semiconductors on the route of the current. These power semiconductors on the route of the current increase power losses.
An exemplary inverter for supplying a grid is disclosed. The inverter comprising a DC link including two capacitor units in series and a neutral point (VDC0) between the capacitor units, and a first and a second inverter leg, wherein both inverter legs are connected between the poles (VDC+ and VDC−) of the DC link and both inverter legs comprising four switching devices (Sn1-Sn4) connected in series, wherein each switch has a conductive state and a non-conductive state and the switches together forming a low resistance route from the positive pole of the DC link to the negative pole of the DC link when all are in the conducting state, an upper connection point (Vn12) between two topmost switching devices (Sn1, Sn2) of the four switching devices, a lower connection point (Vn34) between two bottommost switching devices (Sn3, Sn4) of the four switching devices, an output (Vn23) between two middle switching devices (Sn2, Sn3) of the four switching devices, a first rectifier device (Dn1) connected between a neutral point (VDC0) of the DC link and an upper connection point (Vn12) of the leg allowing flow of current from the DC link neutral point (VDC0) to the upper connection point (Vn12), and a second rectifier device (Dn2) connected between the DC link neutral point (VDC0) and a lower connection point (Vn34) of the leg allowing flow of current from the lower connection point (Vn34) to the DC link neutral point (VDC0), wherein each inverter leg further comprises a third rectifier device (Dn3) connected the between upper connection point (Vn12) of the leg and an output (Vm23) of the other leg allowing flow of current from the output (Vm23) of the other leg to the upper connection point (Vn12), and a fourth rectifier device (Dn4) connected between the output (Vm23) of the other leg and the lower connection point (Vn34) of the leg allowing flow of current from the lower connection point (Vn34) to the output (Vm23) of the other leg.
An exemplary method for controlling an inverter having a DC link including two capacitor units in series and a neutral point (VDC0) between the capacitor units, and a first and a second inverter leg, wherein both inverter legs are connected between the poles (VDC+ and VDC−) of the DC link and both inverter legs comprising four switching devices (Sn1-Sn4) connected in series, wherein each switch has a conductive state and a non-conductive state and the switches together forming a low resistance route from the positive pole of the DC link to the negative pole of the DC link when all are in the conducting state, an upper connection point (Vn12) between two topmost switching devices (Sn1, Sn2) of the four switching devices, a lower connection point (Vn34) between two bottommost switching devices (Sn3, Sn4) of the four switching devices, an output (Vn23) between two middle switching devices (Sn2, Sn3) of the four switching devices, a first rectifier device (Dn1) connected between a neutral point (VDC0) of the DC link and an upper connection point (Vn12) of the leg allowing flow of current from the DC link neutral point (VDC0) to the upper connection point (Vn12), and a second rectifier device (Dn2) connected between the DC link neutral point (VDC0) and a lower connection point (Vn34) of the leg allowing flow of current from the lower connection point (Vn34) to the DC link neutral point (VDC0), wherein each inverter leg further comprises a third rectifier device (Dn3) connected the between upper connection point (Vn12) of the leg and an output (Vm23) of the other leg allowing flow of current from the output (Vm23) of the other leg to the upper connection point (Vn12), and a fourth rectifier device (Dn4) connected between the output (Vm23) of the other leg and the lower connection point (Vn34) of the leg allowing flow of current from the lower connection point (Vn34) to the output (Vm23) of the other leg is disclosed. The method comprising setting one or more of the middle switching devices to conducting state so that the inverter is set to a neutral point zero state.
An exemplary inverter for supplying a grid is disclosed. The inverter comprising a DC link including two capacitor units in series and a neutral point (VDC0) between the capacitor units, and a first and a second inverter leg, wherein both inverter legs are connected between the poles of the DC link. Each inverter leg comprising four switching devices connected in series and the switches together form a low resistance route from the positive pole of the DC link to the negative pole of the DC link, a first rectifier device connected between a neutral point of the DC link and an upper connection point of the leg allowing flow of current from the DC link neutral point to the upper connection point, and a second rectifier device connected between the DC link neutral point and a lower connection point of the leg allowing flow of current from the lower connection point to the DC link neutral point. Each inverter leg also comprises a third rectifier device connected the between upper connection point of the leg and an output of the other leg allowing flow of current from the output of the other leg to the upper connection point, and a fourth rectifier device connected between the output of the other leg and the lower connection point of the leg allowing flow of current from the lower connection point to the output of the other leg.
In the following the disclosure will be described in greater detail by means of preferred embodiments with reference to the attached drawings, in which
Exemplary embodiments of the present disclosure provide new paths for current in the neutral point zero state. Routes with only two power semiconductors can be established by clamping the inverter legs also from the line side. The power losses thus decrease and better efficiency can be achieved.
The inverter further includes a first inverter leg and a second inverter leg, both legs being connected between the poles VDC+ and VDC− of the DC link. Both inverter legs have four switching devices Sn1-Sn4 (nε{1,2}) connected in series. Each switching device Sn1-Sn4 has a conducting state and a non-conducting state and the switching devices Sn1-Sn4 together form a low resistance route from the positive pole of the DC link to the negative pole of the DC link when all switching devices Sn1-Sn4 are in the conducting state. The switching devices Sn1-Sn4 can be, for example, IGBTs or power MOSFETs or any other suitable switching device as desired. In an exemplary embodiment, each switching device S11-S14 and S21-S24 is paired with a freewheeling diode. In other exemplary embodiments of the present disclosure, some of the switching devices may be IGBTs and some power MOSFETs.
Both inverter legs can include an upper connection point Vn12 between the two topmost switching devices Sn1 and Sn2, a lower connection point Vn34 between the two bottommost switching devices Sn3 and Sn4, and an output Vn23 between the two middle switching devices Sn2 and Sn3. The output can be filtered with a balanced LCL filter.
The inverter legs can be clamped to the neutral point VDC0. For example, both inverter legs include a first rectifier device Dn1 which is connected between the DC link neutral point VDC0 and the leg upper connection point Vn12 allowing flow of current from the DC link neutral point VDC0 to the leg upper connection point Vn12, and a second rectifier device Dn2 connected between the DC link neutral point VDC0 and the leg lower connection point Vn34 allowing flow of current from the leg lower connection point Vn34 to the DC link neutral point VDC0. The first rectifier device Dn1 and second rectifier Dn2 device tie the output Vn23 of each inverter leg to the neutral point in the neutral point zero state.
The inverter legs can also be clamped from the output line side. For example, both inverter legs include a third rectifier Dn3 device connected between the upper connection point Vn12 of the leg and the output Vm23 (Mε{1,2}, m≠n) of the other leg allowing flow of current from the output Vm23 of the other leg to the leg upper connection point Vn12, and a fourth rectifier device Dn4 connected between the output Vm23 of the other leg and the lower connection point Vn34 of the leg allowing flow of current from the lower connection point Vn34 to the output Vm23 of the other leg.
The third rectifier Dn3 and fourth rectifier Dn4, in cooperation with the inverter leg middle switches Sn2 and Sn3, provide a path for current which has only two power semiconductors: a diode Dn3 or Dn4 and a switch Sn2 or Sn3, respectively.
Table 1 below illustrates a 3-level (line-to-line) output voltage modulation scheme for an embodiment according to the present invention. The scheme has five switching states: +UDC, +0, ±0, −0 and −UDC, represented in Table 1 by five main columns labelled respectively. The rows of the table represent the states of the individual switches where “1” stands for the conducting state and “0” for the non-conducting state.
The voltage between the inverter leg outputs can in this modulation scheme be set to three potentials: +UDC, 0 and −UDC, where UDC is the voltage potential of the DC link and 0 is zero potential. Each of these potentials can be formed without changes in common-mode voltage.
The potentials +UDC and −UDC can be formed by using states +UDC and −UDC, respectively. The upmost switching devices Sn1 and Sn2 of an inverter leg and the two bottommost switching devices Sn3 and Sn4 of the other inverter leg are set to a conducting state, as shown in Table 1. The switching devices provide a path for current from the DC link to the grid.
The zero potential 0 is formed using one of three neutral point zero states +0, ±0 or −0. The state +0 provides two paths for current in the same direction as in state +UDC. The routes c and d for current in the state +0 are illustrated in section +0 of
Neutral point zero states can also be formed with one path for current. In a zero state, a neutral point zero state with one current path (c, d, e or f) can be formed by setting only one of the middle switching devices S12, S13, S22 or S23 to a conducting state.
In other exemplary embodiments, various combinations of routes for current in the neutral point zero state are also possible. For instance, both middle switching devices of an inverter leg may be set to a conducting state. The leg thus provides routes to both directions of current.
In an exemplary embodiment, the DC link of an inverter is supplied by a switching converter with galvanic isolation, modulation methods with 5-level output voltage (line-to-line) can be used because the galvanic isolation can effectively prevent the common-mode voltages from advancing to the grid side.
In other exemplary embodiments, various modulation methods and switching combinations can be used to control an inverter according to the present disclosure.
Thus, it will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restricted. The scope of the invention is indicated by the appended claims rather than the foregoing description and all changes that come within the meaning and range and equivalence thereof are intended to be embraced therein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10173154.5 | Aug 2010 | EP | regional |
