Patent Application
20080022143
The embodiments of the present invention will now be described by reference to the following figures, in which identical reference numerals in different figures indicate identical elements and in which:
Referring now to
The system 10 comprises a PON host 20, a plurality of substantially identical (for purposes of the present discussion) PON subscribers 30, of which an exemplary subscriber is shown in detail, a PON host optical module 40, at least one optical splitter 50, a plurality of fibers 60, 61 and a plurality of PON subscriber optical modules 70.
The host 20 is connected to the host optical module 40 by a pair of serial connections 25 and 26. Serial connection 26 conveys serial data from the host 20 to the host optical module 40 (downstream data) while serial connection 25 conveys serial data from the host optical module 40 to the host 20 (uplink data). As mandated by the PON standard specifications, the downstream data is transmitted in continuous fashion while the uplink data is received in bursts.
As shown in
The host 20 accepts as an input a global frequency reference 24, which it uses to time its downstream data.
As is discussed below, the host 20 also comprises a burst CDR circuit 23 in accordance with the present invention, with which the host 20 maintains a receiver sampling clock that is synchronized to each uplink data burst received along serial connection 22.
Each subscriber 30 is connected to a corresponding subscriber optical module 70 by a pair of serial connections 31 and 32. Serial connection 31 conveys serial data from the subscriber 30 to the subscriber optical module 70 (uplink data) while serial connection 32 conveys serial data from the subscriber optical module 70 to the subscriber 30 (downstream data). As mandated by the PON standard specifications, the downstream data is received in continuous fashion while the uplink data is transmitted in bursts.
The subscriber 30 recovers a clock signal from the downstream data and uses it to retime its uplink data intended for the host 20, thus ensuring relative identity of frequency for all uplink data intended for the host 20.
The host optical module 40 is connected to the host 20 by serial connections 25 and 26 and to a single optical fiber 60 feeding into the optical splitter 50. The host optical module 40 converts the downstream serial data received along serial connection 26 from the electrical domain into the optical domain and transmits it along host optical fiber 60 at a first downstream wavelength. Similarly, it converts the uplink optical data it receives along host optical fiber 60 at a second upstream wavelength back down to the electrical domain and transmits it in serial form along serial connection 25 to the host 20.
The optical splitter 50 is connected to the host optical module 40 by the host optical fiber 60 and to a plurality of subscriber optical fibers 61 each feeding into a corresponding subscriber optical module 70. The optical splitter 50 divides downstream signals arriving along the host optical fiber 60 at the downstream wavelength to each of the subscriber optical fibers 61 and collects uplink signals arriving along the various subscriber fibers 61 at the uplink wavelength and merges them into the host fiber 60.
Those having ordinary skill in the art will readily recognize that depending upon the number of subscribers in the PON, a plurality of optical splitters, either in parallel or cascaded may be implemented to accommodate the subscribers, with additional fibers (not shown) interconnecting them.
Turning now to
It comprises a voltage controlled oscillator (VCO) 231, which is preferably but not limited to an inductive/capacitive (LC) VCO, acting as a variable phase/frequency clock source. The VCO 231 is adjustable in frequency as a function of either input voltage or input current. Those having ordinary skill in this art will readily recognize that the LC VCO is an oscillation source with variable phase/frequency. Alternatively fixed phase VCO sources followed by phase rotators to provide phase interpolation could be used. Those having ordinary skill in this art will readily recognize that a ring oscillator with calibrated parameters related to PLL bandwidth could also be used.
At all times, the oscillator used in the inventive burst CDR circuit 23 to generate the receiver frequency is highly bandwidth constrained. Preferably, this is achieved by use of an LC VCO, which is chosen for its tight control of bandwidth-related parameters in conventional silicon processes. Those having ordinary skill in this art will readily recognize that any controllable oscillator with tight control of bandwidth related parameters could be suitably used.
Those having ordinary skill in this art will also recognize that conventional PON receivers using an oversampled synchronization scheme do not face such bandwidth constraints, so that ring oscillators are more typically used. Ring oscillators are well understood, low cost and of simple implementation. While they also produce much wider bandwidth variation, this is not significant in conventional oversampled synchronization approaches.
The inventive burst CDR circuit 23 modifies a conventional linear CDR circuit to overcome the timing constraints endemic to such circuits. Specifically, before a burst of uplink data arrives, the inventive linear CDR circuit 23 is synchronized to the same local frequency reference source 24 that times the downstream data stream, so that all of the subscribers 30 are already synchronized to this frequency and the time to achieve frequency synchronization is minimized.
In order to frequency lock the VCO to the master frequency reference, a frequency comparison circuit 232 compares the output 237 of the VCO 231 with the PON master frequency reference 24. The master frequency reference 24 is the same local frequency reference source that times the downstream data stream, so that all of the subscribers 30 are already synchronized to this frequency. Accordingly, the time to achieve frequency synchronization can be minimized. Typically, since the master frequency reference 24 operates at a lower frequency than the LC VCO 231, a divided version of the VCO 231 is actually compared against the master frequency reference 24.
Those having ordinary skill in this art will recognize that either the local sample clock, the reference, or both signals may be divided prior to the frequency/phase comparison. Accordingly, for the purposes of this invention, the term “frequency and/or phase lock” incorporate comparing a divided first signal with a higher rate second signal. In such circumstances, frequency and/or phase lock is said to have occurred when a pair of similar transitions occur at the same time (or within a predetermined tolerance) in both signals, even though in the higher rate signal the transitions are not necessarily consecutive.
The frequency comparison circuit 232 provides a correaction signal 236 to be used in a feedback loop to adjust the sample clock frequency during an initial lock to reference state. In the lock to reference state, the correaction signal 236 is fed through a PLL selector 233 and into a charge pump 237 that drives an integrating filter circuit 238 that feeds back into an input of the LC VCO 231. The integrating filter circuit 238 provides noise immunity and stability for the feedback loop. In the lock to reference state the local sample clock is locked in both frequency and phase to the master reference.
Preferably, the frequency comparison circuit 232 comprises a phase-frequency detector that locks the output signal 237 of the LC VCO 231 to the PON master frequency reference 24. Those having ordinary skill in the relevant art will recognize that such a phase-frequency detector will not lock the LC VCO 231 to data, but only to a tone, such as the master frequency reference 24.
The frequency comparison circuit 232 causes the LC VCO 231 to remain locked to the master reference frequency 24 between uplink bursts. When an uplink data burst arrives, a PLL selection switch 233 causes the burst CDR circuit 23 to switch to a lock to data state in which the correaction signal for a feedback phase locked loop (PLL) comprising the VCO 231, integrating filter circuit 238 and charge pump 237 is derived from the data, not the master reference frequency 24.
Preferably the arrival of the uplink data burst is detected and signalled by a data detection circuit 241 that monitors the uplink data stream from serial connection 25. Alternatively, the host 20 may provide an external signal (not shown) when it obtains information about the anticipated arrival time of the burst. Still further, a signal may be obtained from the optics (not shown) to initiate phase lock.
The data detection circuit 241, or an external signal indicating the presence of a data burst, transmits a signal 242 to a system controller 235 when data is received along the serial connection 25, so that the LC VCO 231 should be locked to data as opposed to the master reference source 24.
The system controller 235 is preferably a state machine consisting of a plurality of timers (not shown). In order to optimize phase lock to the data burst, the receiver remains in the lock to data state only when uncorrupted data is present. The timers ensure that this is the case.
A first timer provides a delay before initiating data lock after data has been signalled to be present by either the data detection circuit 241 or an external signal. This first delay provides a settling period for the data (not shown) after laser turn on at the subscriber 30. During this delay period, the VCO 231 remains locked to the master reference 24. If phase lock to data is attempted before the data has settled, the burst CDR 23 could be driven out of frequency lock before uncorrupted data arrives. In such an event, the long time period to reacquire frequency lock would result in the loss of the data in the data burst.
Prior to arrival of the burst, the inventive CDR 23 is placed in a high bandwidth state. This state speeds phase lock during the preambular period. The initiation of the higher bandwidth state is achieved by supplying control signals to both the charge pump 237 and the integrating filter circuit 238, thus increasing the gain of each while still meeting PLL requirements for stability and linearity. The bandwidth setting for the lock to data state is beyond the range usually associated with broadband standards.
The time with expanded bandwidth is limited by a second timer in the system controller 235 to limit jitter effects caused by the expanded bandwidth. A high bandwidth CDR will be subject to high pattern-dependent recovered clock jitter when recovering a clock from random data. If a tone is used for the preamble, this higher pattern-dependent jitter is not present. For this reason the inventive burst receiver 23 is only placed in its high bandwidth state when bursts are not present or during a tonal preamble. Following the timeout of the second timer (set to expire prior to the arrival of payload data) the CDR will be forced to a low bandwidth state. Again, this bandwidth optimization is accomplished using control signals to the charge pump 237 and the integrating filter circuit 238.
Eventually, once the uplink data burst has been determined to have ended, the inventive burst CDR 23 will be returned to a high bandwidth state. The end of the burst is determined by the system state machine detecting that a sufficient number of 0s have occurred to guarantee that the subscriber laser is off and that the pattern is not simply a valid occurrence of a long string of 0s within the burst. This is implemented with a third timer in the state machine. An external control signal from the host can also be used to signal the end of the burst. When data has been determined to be no longer present, the VCO 231 is locked to the master reference 24 in preparation for the next burst.
If frequency lock is lost, as a result of drift in the absence of data it will take a considerable period of time to reacquire lock. It is for this reason, after the burst is complete, that the system controller 235 causes the burst CDR 23 to lock to the master reference frequency 24 so that the absence of data will not cause frequency lock to be lost.
Those having ordinary skill in this art will also readily recognize that a collision of two bursts may also cause the linear CDR to lose frequency lock. For example, if during normal operation a subscriber sends data during an invalid timing window (for that subscriber) or during ranging mode when multiple subscribers simultaneously send bursts to allow system calibration, a conventional CDR will lose frequency lock. To regain frequency lock, the system will either have to wait for CDR recovery or the host must recognize the delivery of corrupt data and immediately force the CDR to lock to the master reference. As collision events are rare, a CDR recovery period is allowable within the standard.
When the CDR is in the lock to data state, the phase comparison circuit 239 compares the output signal 237 of the LC VCO 231 to the received data stream delivered from serial connection 25 and generates an output voltage or current 240 that is a linear function of the phase difference between a transition in the uplink data stream and a transition in the output signal 237 of the LC VCO 231. The output signal 240 is fed into the PLL selection switch 233 and in the lock to data state, through the charge pump 237 and the integrating filter circuit 238 and back into the LC VCO 231. Thus, the feedback circuit fixes the LC VCO 231 in a stable state at an optimal phase that corresponds with the center of the data eye. Those having ordinary skill in this art will recognize that the center of the eye depends on the shape of the eye. The phase of the CDR may be adjusted slightly to optimize the bit error rate of the system and the center of the eye should be understood as that phase that is most optimal for transmission of data. A CDR may also be centered slightly off center and still provide sufficient performance for some systems.
Preferably, the phase comparison circuit 239 comprises a modified Hogge-type phase detector circuit. The Hogge-type circuit works in conjunction with the charge pump 237 to drive a linear current output as an input into the integrating filter circuit 238 and ultimately providing a correction signal to the LC VCO 231. Alternatively, those having ordinary skill in this art will readily recognize that many other types of linear and non-linear phase detectors could be used, including but not limited to a bang-bang phase detector, SAW filter, mixer, and sample&hold phase detector.
Finally, a demultiplexing circuit 243 converts the recovered high speed serial data stream from the phase comparison circuit 239 at a data rate suitable for conventional digital processing by the host 20.
In operation, at all times the system controller 235 monitors the frequency of the VCO 231 and compares it to that of the master reference 24 or divided versions thereof. This is done by counting transitions of the divided VCO clock and the master reference within a fixed time duration. The difference between counts translates to the frequency deviation between the two clocks. If the count period is long enough to provide sufficient resolution and the counts differ beyond a threshold that defines frequency lock (˜1 loop bandwidth) then the burst CDR 23 will be forced into frequency lock with the master reference 24 to resynchronize the VCO with the PON master reference frequency. This monitor function overrides all other system controller 235 functions because no other states are valid if there is excessive frequency deviation between the frequency of the master reference 24 and the frequency of the VCO 231.
The frequency monitoring time to provide a resolution of 1 loop bandwidth is substantially longer than the time to achieve frequency lock. Transition from the lock to reference state to the lock to data state can only occur after the frequency comparison circuit 232 has completed a measurement. In order to speed frequency lock after a collision (or other event forcing loss of frequency lock), the frequency comparison circuit 232 resolution is relaxed below the traditional value for transport systems of 1 loop bandwidth. The monitor measures gross loss of frequency lock but has its resolution set low enough so that it does not gate the readiness of the CDR for the next burst. The time for frequency lock is known and the monitor resolution is set so that frequency lock will be guaranteed in the time that is takes to monitor the frequency.
Following the transition to the lock to reference state, the system controller 235 forces the inventive burst CDR receiver 23 to remain in the lock to reference state until the VCO 231 frequency matches that of the master frequency reference 24. While in the lock to reference state, the LC VCO 231 will be in its high bandwidth setting so as to promote fast frequency locking.
Once frequency lock has been acquired, and when data is thereafter detected by the data detection circuit 241, the system controller 235 will delay for a pre-determined delay to ensure that the data has settled. Thereafter, the system controller 235 will signal the PLL selection switch 233 using timer signal 236 to lock to data in an attempt to acquire phase lock.
Thereafter, after a further pre-determined delay, the bandwidth of the CDR will be lowered for optimal circuit jitter performance. This second delay is chosen to ensure that sufficient phase lock has occurred.
Presence of data is determined by the presence of optical output at the receiver of the host 20 when the subscriber optical module laser (not shown) is activated and transmitting a minimum number of 1s in a given time period. The minimum number is determined from analysis of typical data, which is permitted to have a limited sequence of consecutive 0s under the transmission protocol. The PON standards statistically permit up to 72 consecutive 0s in real data, however those persons having ordinary skill in the art will readily recognize that 72 is just an example. Accordingly, if the system controller 235 times out because of an excessive number of 0s in the pattern, for example, after a period corresponding to 72 consecutive 0s, it will conclude that data has been lost and revert to the lock to reference state.
It is possible to have a time between bursts of less than 72 bits. If this is true then the burst CDR 23 relies on external input from the host to determine the expected beginning and end of a burst. In order for the PON to function without collisions, the latency between the host and each subscriber must be calibrated in a ranging/discovery period within the PON protocol. During this ranging period the host compiles the timing data that is necessary to supply an external host signal to the burst receiver indicating a gap between burst. This signal allows the use of the timers in the system controller 235 to optimize bandwidth, expanding it for phase acquisition, and after phase lock, contracting it for jitter immunity. If an external signal is not available then the burst CDR 23 will be subject to effects including lack of filtering at laser turn on and the inability to have a different bandwidth during the preamble and the payload data. The burst receiver 23 can still function with these restrictions but performance will be sub-optimal.
Because the inventive burst CDR 23 does not employ oversampling, it is better suited to enable host receiver synchronization at higher PON data rates, for example, at 1.24416 Gbit/s and higher. Indeed, as data rates increase, synchronization times improve because there are more data transitions available to more rapidly force phase lock. Also there is a fundamental stability ratio relation for a linear CDR between the CDR clock rate and the CDR bandwidth. Higher clock rates allow higher bandwidth and therefore faster locking time. By contrast, conventional oversampling systems are constrained to relatively lower data rates because sampling must take place at a significant multiple of the data rate. In today's 0.13 μm silicon technology, 10 Gbit/s conventional (non burst) linear receivers are widely available. The same technology has only delivered 1.25 Gbit/s oversampled receivers with sufficient resolution to be used in the longer reach optical links required in PON standards such as GPON. Baud rate sampling will always allow a higher maximum receiver rate within a given technology as compared to oversampling.
Simulations have predicted that the inventive burst CDR 23 will achieve frequency lock to the master reference within 12 μs and will typically achieve phase lock to data within 10 ns. In particular without bandwidth widening during the preambular period, the inventive burst CDR 23 will achieve lock in less than 250 ns at data rates below 1.2 Gb/s. Above this data rate, other components in the system overwhelm the ratio between the preambular time and the bit period, so that the standards will fix the phase lock period to less than 250 ns. This provides significant margin in the GPON timing budget that may now be used by other components in the system and compares favourably to the lock time period of approximately 15,000 bit periods using a conventional (CDR or oversampling) system.
When the inventive CDR 23 has a variable bandwidth that may be increased as previously discussed during the pre-ambular period, the inventive burst CDR 23 will require a maximum of 30 bits to achieve lock.
The inventive burst mode receiver 23 is constructed in conventional and economic CMOS processes and it allows other elements in the systems to be designed with relaxed specifications thus providing multiple cost advantages.
The present invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combination thereof. Apparatus of the invention can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and methods actions can be performed by a programmable processor executing a program of instructions to perform functions of the invention by operating on input data and generating output. The invention can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language.
Suitable processors include, by way of example, both general and specific microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in ASICs (application-specific integrated circuits).
The system may comprise a processor, a random access memory, a hard drive controller, and an input/output controller coupled by a processor bus.
It will be apparent to those skilled in this art that various modifications and variations may be made to the embodiments disclosed herein, consistent with the present invention, without departing from the spirit and scope of the present invention.
Other embodiments consistent with the present invention will become apparent from consideration of the specification and the practice of the invention disclosed therein.
Accordingly, the specification and the embodiments are to be considered exemplary only, with a true scope and spirit of the invention being disclosed by the following claims.
