Claims
- 1. A method for flexibly expanding a digital bus input signal with an efficient implementation for a linear function utilizing spare gates in a Programmable Logic Array or Field Programmable Gate Array for generating an output digital signal for controlling a target digital modules comprising the steps of:
- (a) generating a difference signal Xd in an UP-DOWN counter module which represents the value of a source-setting pulse stream signal (A) reduced by a feedback pulse stream digital signal (C);
- (b) adding a N-bit digital intercept parameter value "a" to said Xd signal to generate an N-bit digital signal, such that Xd+a=Xa.
- (c) multiplying said N-bit digital signal Xa by a slope parameter "b" to develop an (N+q) bit digital output signal Y, where q represents the digital offset value in binary notation corresponding to the specific value of the slope parameter "b" such that bXa=Y and thus Y=bXd+ba.
- 2. The method of claim 1 which includes the step of:
- (d) converting said digital output signal Y to a precise voltage for controlling said target module.
- 3. The method of claim 1 wherein step (a) includes the step of:
- (a1) synchronizing the digital pulses of said feedback digital signal (C) with the digital pulses of said source setting signal (A) in order that the count of pulses of said signal (A) will be reduced by the count of pulses of said signal (C).
- 4. A system, in a network having a linear functional relationship between an input digital signal X and an output digital signal Y, for efficiently developing and implementing in spare rates of a programmable logic array, a digital output control signal Y for a target module, comprising:
- (a) means for generating a first pulsed sequence signal (A) representing a source generated setting signal of a sequence of pulses for a first input to an arbitration-synchronization module;
- (b) means for generating a second pulsed sequence signal (C) representing a digital feedback signal from said target module utilizing a sequence of pulses as a second input to said arbitration-synchronization module;
- (c) said arbitration-synchronization module having a high speed common clock signal for synchronizing said first pulsed sequence signal (A) and said second pulsed sequence signal (C) to produce an up count of pulses of said first signal (A) and down-count of pulses for said second signal (C) into a difference counter means;
- (d) said difference counter means providing an output signal X=A-C which signal x is output on a N-Bit bus to a multiplier means;
- (e) said multiplier means for multiplying said signal X by a slope parameter value "b" to generate said digital output control signal Y as output on a (N+q) bit bus where N is the number of bit lines fed into said multiplier means and q is a digital offset value in binary notation corresponding to the value of the slope parameter "b".
- 5. The system of claim 4 which includes:
- (f) driver means for adapting said signal Y to said target module.
- 6. The system of claim 4 wherein said target module includes:
- (g) means to generate a sequence of digital feedback pulses as signal C to said arbitration-synchronization module to indicate any deviation between signal C and signal A.
- 7. The system of claim 4 which includes:
- (h) a third input signal "a" of N-bits fed to said difference counter means for adding in an intercept value which represents the value of Y when X=0.
- 8. A system for digitally generating an output control signal Y to a target module utilizing a linear function generator, which develops a digital difference signal Xd which is integrated with an intercept parameter "a" and multiplied by a slope parameter "b" to establish said output control signal Y in the relation Y=ba+bXd, said system comprising:
- (a) Up/Down Counter means for generating an input digital signal Xa=Xd+a on an N bit input bus to a multiplier means where Xd is the digital difference between a digital source-setting signal (A) and a digital feedback signal (C) from said target module;
- (b) said multiplier means for multiplying said input digital signal "Xa" by a slope parameter "b" to develop said output control signal Y=ba+bXd on a digital output bus of N+q bits where q represents the digital offset value in binary notation corresponding to the specific value of the slope parameter "b".
- 9. The system of claim 8 wherein said signal "Xa" is operative in a linear functional relationship such that the parameter "a" is the value of Y when X=0 and the parameter "b" is the slope of the line representing the linear relationship between Xa and Y.
- 10. The system of claim 8 wherein said Up/Down Counter means, said N bit input bus, said multiplier means, and said N+q bit output bus are implemented in gates of a Programmable Logic Array.
CROSS-REFERENCE TO RELATED APPLICATIONS
This disclosure is related to a co-pending application entitled "Digital Device Control Method and System Via Linear Function Generator Implementation Using Adder for Intercept" filed Aug. 28, 1997 as U.S. Ser. No. 919,389, Allowed and which is incorporated by reference.
US Referenced Citations (7)