This disclosure generally relates to the detection of microseismic events within subterranean formations. More particularly, this disclosure relates to linear inversion of microseismic event location using seismic data image file attributes.
Historically microseismic event location within subterranean formations has been done by time picking for each seismic receiver placed in the field or energy scanning for seismic data acquired at each receiver in the seismic data domain. The microseismic event location inversion problem has been formulated in 3D or 2D space due to its nature. Typically, the relation between time pick and event location is given by:
where T is the arrival time of a seismic wave (P or S), sis slowness (inverse of formation velocity) along the propagation path from event location to receiver, delta (Δ) is the distance of the event from the receiver (event location) measured along the propagation path, and To is origin time of the event. To solve the event location, the origin time can be inverted using a known velocity model. Further, the dataset can be time picked, and P and S waves labeled properly since slowness for P and S waves are different. In the production monitoring application, formation velocity is typically unavailable, and labeled time picks are often difficult to obtain. Even if formation velocity information is available, receivers must be evenly distributed in 3D space for appropriate accuracy, which is not possible for single well monitoring. The same is true for a 2D problem for single well monitoring as at least the velocity model will be unavailable.
Optical fiber distributed acoustic sensing (DAS) is triggering innovations in a wide area of subsurface sensing. In production monitoring (oil/gas/geothermal), people are interested in reservoir deformation monitoring related to stimulation, injection, and/or extraction through strain and microseismic data analysis of optical fiber data. However, microseismic processing of those data is challenging because of the larger data volume (on the order of 2-4 times larger as compared to conventional methods), and relatively low signal to noise ratios (SNR). Those characteristics push current processing techniques far beyond their limits.
There is a desire, therefore, for processes and systems that can determine the existence of and the estimated location for microseismic events within subterranean formations without knowledge of a velocity model.
This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.
Processes and systems for microseismic event detection are provided. In some embodiments, the process for estimating a subterranean depth of one or more microseismic events within a subterranean formation, can include: acquiring seismic data from the subterranean formation with the dense seismic receiver array and converting the seismic data into an image domain dataset. The process can also include detecting within the image domain dataset one or more seismic waveform edges and characterizing within the image domain dataset one or more linear segments which each define a portion of one or more of the one or more seismic waveform edges, and where the linear segments are functions of one or more seismic arrival times and one or more subterranean depths. The process can also include estimating the subterranean depth of the one or more microseismic events within a subterranean formation based on the one or more linear segments.
In some embodiments, the system can include a dense seismic receiver array configured to acquire seismic data from a subterranean formation and at least one processor configured to execute an executable code to implement at least the functionality of estimating a subterranean depth of one or more microseismic events within a subterranean formation, including: converting seismic data from the dense seismic receiver array into an image domain dataset. The system can also include the at least one processor configured to execute code to implement at least the functionality of detecting within the image domain dataset one or more seismic waveform edges. The system can also include the at least one processor configured to execute code to implement at least the functionality of characterizing within the image domain dataset one or more linear segments which each define a portion of one or more of the one or more seismic waveform edges, and where the linear segments are functions of one or more seismic arrival times and one or more subterranean depths. The system can also include the at least one processor configured to execute code to implement at least the functionality of estimating the subterranean depth of the one or more microseismic events within a subterranean formation based on the one or more linear segments. Other aspects can also be described and claimed.
The subject disclosure is further described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of the subject disclosure, in which like reference numerals represent similar parts throughout the several views of the drawings.
The particulars shown herein are by way of example and for purposes of illustrative discussion of the examples of the subject disclosure only and can provide what might be the most useful and readily understood description of the principles and conceptual aspects of the subject disclosure. In this regard, no attempt is made to show every structural detail, the description taken with the drawings making apparent to those skilled in the art how the several forms of the subject disclosure can be embodied in practice.
In one or more embodiments, the process 100 may further include disposing the dense seismic receiver array along or within a wireline cable or any other downhole system that may include a dense seismic receiver array. In other embodiments, the process 100 may further include forming a casing within a wellbore and deploying the dense seismic receiver array behind or within a casing formed within the wellbore. In further embodiments, the process 100 may further include deploying a tubing within the wellbore, where the dense seismic receiver array is disposed behind or within the tubing. Additionally, in one or more embodiments, the process 100 may further include increasing or decreasing a pressure within a well during production operations based on the estimated subterranean depth of the one or more microseismic events.
Referring to
In one or more embodiments, edge enhancement processing can be performed to enhance seismic wave arrivals in the image domain dataset. The edge enhanced seismic data can be analyzed to characterize one or more continuous structures such as parabolas and/or other higher order features. In some embodiments, a one-dimension (1D) Hough transform can be utilized to characterize the one or more linear segments. The linear segments information in the seismic image can correspond to an apparent slowness of the seismic data. In some embodiments, a slope of a linear segment can be used to estimate a subterranean depth of the microseismic event. Thus, as discussed further below, the apparent slowness of seismic wave arrivals can be computed to detect within the image domain dataset the one or more seismic arrival times of an edge of the one or more seismic waveform edges at a subterranean depth relative to the subterranean depth of the dense seismic receiver array (Block 106). In some embodiments filters can be applied to the edge detected signal or the Hough transform domain signal for further regularization. Further, in one or more embodiments, the 1D Hough transform can be performed to determine non-seismic features within the image domain dataset and to trim the non-seismic features from the image domain dataset.
where v′ is the apparent velocity at the location R (0, 302), v is the velocity of the seismic wave 311), θ or angle 304, is the incident angle of the seismic wave measured from the wellbore 225 axis. The edge detection and linear segment detection described above can measure the angle 304 of the linear segments in the seismic data, which is the local apparent slowness, s′. Equation 1.1 can be re-written in the following form:
Where s is the measured slowness and the angle 304 is the incident angle of the wave relative to the wellbore 225. As seen in
The above calculations infer slowness in the image domain but do not infer θ for the 2D case. For a single dimension or 1D measurement case, equation 1.2 can be re-expressed in terms of θ, to arrive at the following equation.
Therefore equation (1.2) can be estimated by the following:
Equation 1.4 can be utilized to estimate the subterranean depth of the one or more microseismic events within a subterranean formation relative to the subterranean depth of the dense seismic receiver array 220 as a function of a subterranean depth within the image domain dataset (Block 107). For example the microseismic event at location E(re, ze) or E (315, 320) in
To achieve its desired functionality, the computing system 512 can include various hardware and software components. Among these components can be one or more processors 514 and a microseismic events controller 540. These hardware components can be interconnected through the use of a number of electrical connections, busses, and/or network connections. In one embodiment, the processor 514, the chip 505, the chip 521, and the microseismic events controller 540 can be communicatively coupled via a bus 522. The bus 522 can be or include any know computing system bus. The microseismic events controller 540 can be internal to a data storage device 516.
The chip 505, the chip 521, and/or the microseismic events controller 540 can include, either separately or in some combination, software and hardware, including tangible, non-transitory computer readable medium (not shown), for estimating the location for one or more microseismic events within the subterranean formation. The microseismic events controller 540 can be integrated into the chip 505, the chip 521, and/or the processor 514. The chip 505 and/or the chip 521 can be integrated into the processor 514. Although microseismic events controller 540 is depicted as being internal to the data storage device 516, in other examples, the controller module 534 can be a peripheral device (not shown) coupled to the computing system 512 or included within a peripheral device (not shown) coupled to the computing system 512. In other examples, the microseismic events controller 540 can be a peripheral device (not shown) coupled to the computing system 512 or included within a peripheral device (not shown) coupled to the computing system 512.
The microseismic events controller 540 can include instructions that when executed by the microseismic events controller 540 can cause the microseismic events controller 540 to implement at least the functionality of acquiring seismic data with a dense seismic receiver array disposed within the subterranean formation, on the surface above the subterranean formation, or a combination thereof; converting the seismic data into an image domain dataset; detecting within the image domain dataset one or more seismic waveform edges; characterizing within the image domain dataset one or more linear segments, where each of the one or more linear segments define a portion of an edge of the one or more of the seismic waveform edges as a function of seismic arrival time and subterranean depth; and estimating the subterranean depth of the one or more microseismic events based on the one or more linear segments. Further, in some embodiments, the instructions can, when executed by the microseismic events controller 540, cause the microseismic events controller 540 to output a signal indicating whether pressure should be increased or decreased within a well during production operations based on the estimated subterranean depth of the one or more microseismic events. In some embodiments, the microseismic events controller 540 can work in conjunction with the processor 514 to implement the functionality described above. In some embodiments, the microseismic events controller 540 can execute firmware code stored on the computing system 512, such as on the chip 505, the chip 521, and/or the processor 514. The functionality of the computing system 512 and/or the microseismic events controller 540 can be in accordance with the processes of the present specification described herein. In the course of executing code, the processor 514 and/or the microseismic events controller 540 can receive input from and provide output to a number of the remaining hardware units.
The computing system 512 can be implemented in an electronic device. Examples of electronic devices include servers, desktop computers, laptop computers, cloud based computers, personal digital assistants (“PDAs”), mobile devices, smartphones, gaming systems, and tablets, among other electronic devices. The computing system 512 can be utilized in any data processing scenario including, stand-alone hardware, mobile applications, through a computing network, or combinations thereof. Further, the computing system 512 can be used in a computing network, a public cloud network, a private cloud network, a hybrid cloud network, other forms of networks, or combinations thereof. In one example, the methods provided by the computing system 512 are provided as a service by a third party.
To achieve its desired functionality, the computing system 512 can include various other hardware components. Among these other hardware components can be a number of data storage devices or tangible, non-transitory computer readable medium 516, a number of peripheral device adapters 518, and a number of network adapters 520. These hardware components can be interconnected through the use of a number of electrical connections, busses, and/or network connections. In one example, the processor 514, data storage device 516, peripheral device adapters 518, and a network adapter 520 can be communicatively coupled via a bus, for example the bus 522 as depicted in
The chip 505, the chip 521, and/or the processor 514 can include the hardware and/or firmware/software architecture to retrieve executable code from the data storage device 516 and execute the executable code. The executable code can, when executed by the chip 505, the chip 521, and/or the processor 514, cause the chip 505, the chip 521, and/or the processor 514 to implement at least the functionality of acquiring seismic data with a dense seismic receiver array disposed within the subterranean formation, on the surface above the subterranean formation, or a combination thereof; converting the seismic data into an image domain dataset; detecting within the image domain dataset one or more seismic waveform edges; characterizing within the image domain dataset one or more linear segments, where each of the one or more linear segments define a portion of an edge of the one or more of the seismic waveform edges as a function of seismic arrival time and subterranean depth; and estimating the subterranean depth of the one or more microseismic events based on the one or more linear segments.
The data storage device 516 can store data such as executable program code that is executed by the processor 514, the microseismic events controller 540, or other processing devices. The processor 514 can be a central processing unit that is to execute an operating system in the computing system 512. As will be discussed, the data storage device 516 can specifically store computer code representing a number of applications that the processor 514 and/or the microseismic events controller 540 can execute to implement at least the functionality described herein.
The data storage device 516 can include various types of memory modules, including volatile and nonvolatile memory. In one or more embodiments, the data storage device 516 of the present example can include Random Access Memory (“RAM”) 524, Read Only Memory (“ROM”) 526, and Hard Disk Drive (“HDD”) storage 528. Many other types of memory can also be utilized, and the present specification contemplates the use of many varying type(s) of memory in the data storage device 516 as can suit a particular application of the principles described herein. In certain examples, different types of memory in the data storage device 516 can be used for different data storage requirements. In one or more embodiments, in certain examples the processor 514 can boot from Read Only Memory (“ROM”) 526, maintain nonvolatile storage in the Hard Disk Drive (“HDD”) memory 528, and execute program code stored in Random Access Memory (“RAM”) 524. In examples, the chip 505, and the chip 521 can boot from the Read Only Memory (“ROM”) 526.
The data storage device 516 can include a computer readable medium, a computer readable storage medium, or a non-transitory computer readable medium, among others. In one or more embodiments, the data storage device 516 can be, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the computer readable storage medium can include, for example, the following: an electrical connection having a number of wires, a portable computer diskette, a hard disk, a RAM, a ROM, an EPROM, a Flash memory, a portable compact disc read only memory (“CD-ROM”), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium can be any tangible medium that can contain, or store computer usable program code for use by or in connection with an instruction execution system, apparatus, or device. In another example, a computer readable storage medium can be any non-transitory medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The hardware adapters 518, 520 in the computing system 512 can enable the processor 514 to interface with various other hardware elements, external and internal to the computing system 512. In one or more embodiments, the peripheral device adapters 518 can provide an interface to input/output devices, such as, for example, a display device 530, a mouse, and/or a keyboard. The peripheral device adapters 518 can also provide access to other external devices such as an external storage device, a number of network devices such as, for example, servers, switches, and routers, client devices, other types of computing devices, and combinations thereof.
The display device 530 can be provided to allow a user of the computing system 512 to interact with and implement the functionality of the computing system 512. Examples of display devices 530 can include a computer screen, a laptop screen, a mobile device screen, a personal digital assistant (“PDA”) screen, and/or a tablet screen, among other display devices 530.
The peripheral device adapters 518 can also create an interface between the processor 514 and the display device 530, a printer, or other media output devices. The network adapter 520 can provide an interface to other computing devices within, for example, a network, thereby enabling the transmission of data between the computing system 512 and other devices located within the network. The network adapter 520 can provide an interface to an external telecommunications network such as a cellular phone network or other radio frequency enabled network, thereby enabling the transmission of data between the computing system 512 and other external devices such as an external storage device, a number of network devices such as, for example, servers, switches, and routers, client servers, radio frequency enabled devices, other client devices, other types of computing devices, and combinations thereof.
The computing system 512 can further include a number of modules used in the implementation of the systems and methods described herein. The various modules within the computing system 512 can include executable program code that can be executed separately. In this example, the various modules can be stored as separate computer program products. In another example, the various modules within the computing system 512 can be combined within a number of computer program products; each computer program product including a number of the modules.
The present disclosure further relates to any one or more of the following numbered paragraphs:
Certain embodiments and features have been described using a set of numerical upper limits and a set of numerical lower limits. It should be appreciated that ranges including the combination of any two values, e.g., the combination of any lower value with any upper value, the combination of any two lower values, and/or the combination of any two upper values are contemplated unless otherwise indicated. Certain lower limits, upper limits and ranges appear in one or more claims below. All numerical values are “about” or “approximately” the indicated value, and take into account experimental error and variations that would be expected by a person having ordinary skill in the art.
Various terms have been defined above. To the extent a term used in a claim is not defined above, it should be given the broadest definition persons in the pertinent art have given that term as reflected in at least one printed publication or issued patent. Furthermore, all patents, test procedures, and other documents cited in this application are fully incorporated by reference to the extent such disclosure is not inconsistent with this application and for all jurisdictions in which such incorporation is permitted.
Although only a few examples have been described in detail above, those skilled in the art will readily appreciate that many modifications can be possible in the examples without materially departing from this subject disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures. Thus, although a nail and a screw may not be structural equivalents in that a nail employs a cylindrical surface to secure wooden parts together, whereas a screw employs a helical surface, in the environment of fastening wooden parts, a nail and a screw can be equivalent structures. It is the express intention of the applicant not to invoke 35 U.S.C. § 112, paragraph 6 for any limitations of any of the claims herein, except for those in which the claim expressly uses the words ‘means for’ together with an associated function.
This application claims the benefit of U.S. Provisional Application No. 63/278,383, entitled “Linear Inversion of Micro-Seismic Event Location Using Seismic Data Image File Attributes,” filed Nov. 11, 2021, the disclosure of which is incorporated by reference in its entirety.
Filing Document | Filing Date | Country | Kind |
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PCT/US2022/049698 | 11/11/2022 | WO |
Number | Date | Country | |
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63278383 | Nov 2021 | US |