Patent Application
20240319752
The present invention claims priority under 35 U.S.C. § 119 to Japanese Application, 2023-048152, filed on Mar. 24, 2023, the entire contents of which being incorporated herein by reference.
The present disclosure relates to a linear power circuit.
Linear power circuits are used for power circuits of various elements.
Patent document 1 provides an example of such linear power circuits.
Details of the embodiments are provided with the accompanying drawings below. Generic or specific examples expressed by way of embodiments are described below. Values, shapes, materials, constituting elements, and configuration positions and connections of the constituting elements described in the embodiments below are merely examples, and are not intended as limitations to the present disclosure. Moreover, regarding the constituent elements in the following embodiments, constituent elements that are not described in an independent technical solution representing the most superordinate concept are described as arbitrary constituent elements. Further, for illustrations purposes, scales of sizes of the accompanying drawings may be exaggerated to reveal the presence of situations different from actual scales.
For example, an input voltage Vin is input to the positive input terminal INP. For example, a feedback current Ierr from the output terminal OUT is input to the negative input terminal INN. The input unit 1 is input with input signals and generates and outputs first current signals I11 and I12 corresponding to the input signals, wherein the input signals are the input voltage Vin input to the positive input terminal INP and the feedback current Ierr input to the negative input terminal INN. The current-voltage converter 2 converts currents I21 and I22 generated by a first current mirror circuit 11 and a second current mirror circuit 12 as mirror currents of the first current signals I11 and I12 into a first voltage signal V1, and outputs the first voltage signal V1. A value of the first voltage signal V1 changes according to a balance between the current I21 and the current I22. The voltage-current converter 3 converts the first voltage signal V1 into second current signals I31 and I32, and outputs the second current signals I31 and I32. The output unit 4 generates an output current Io as an output current signal Io from the second current signals I31 and I32 using a third current mirror circuit 41 and a fourth current mirror circuit 42, and outputs the output current signal Io to the output terminal OUT.
The input unit 1 includes a buffer circuit 10. The buffer circuit 10 includes, for example, a single ended push-pull (SEPP) circuit. In the buffer circuit 10, an input impedance of a positive input terminal + is higher, and an input impedance of a negative input terminal − is lower in comparison. That is to say, as a characteristic of a current feedback operational amplifier, the negative input terminal − is equivalent to an output terminal of the buffer circuit 10, and so the input impedance of the negative input terminal − is lower. The positive input terminal INP is connected to the positive input terminal + of the buffer circuit 10, and the negative input terminal INN is connected to the negative input terminal-of the buffer circuit 10.
The current-voltage (I/V) converter 2 includes a bias circuit 20. The bias circuit 20 is connected to the buffer circuit 10 via the first current mirror circuit 11 and the second current mirror circuit 12.
For example, as shown in
For example, as shown in
In addition, the configurations of the first current mirror circuit 11 and the second current mirror circuit 12 are not limited to the configurations described above. A current mirror circuit is a commonly known technique in the prior art, and thus an appropriate configuration can be appropriately selected by a designer.
In the first current mirror circuit 11, the power supply terminal is supplied with a DC voltage of the first DC power supply VCC1, the reference current terminal is connected to a first terminal a of the buffer circuit 10, and the mirror current terminal is connected to a first terminal c of the bias circuit 20. In the second current mirror circuit 12, the power supply terminal is grounded, the reference current terminal is connected to a second terminal b of the buffer circuit 10, and the mirror current terminal is connected to a second terminal d of the bias circuit 20. The first transistor Q1 of the first current mirror circuit 11 and the third transistor Q3 of the second current mirror circuit 12 are included in the input unit 1. The second transistor Q2 of the first current mirror circuit 11 and the fourth transistor Q4 of the second current mirror circuit 12 are included in the current-voltage converter 2.
The input unit 1 and the current-voltage converter 2 constitute a current feedback operational amplifier 5.
The buffer circuit 10, according to the input signals input to the positive input terminal + and the negative input terminal −, for example, the input voltage Vin and the feedback current Ierr, generates the first current signal I11 at the first terminal a and generates the first current signal I12 at the second terminal b. The first current mirror circuit 11 generates the current I21 having a predetermined mirror ratio with respect to the first current signal I11, and the current I21 is input to the first terminal c of the bias circuit 20. The second current mirror circuit 12 generates the current I22 having a predetermined mirror ratio with respect to the first current signal I12, and the current I22 is output from the second terminal d of the bias circuit 20. The bias circuit 20 outputs the first voltage signal V1 corresponding to the currents I21 and I22 to between a third terminal e and a fourth terminal f. The first voltage signal V1 is input to a first terminal g and a second terminal h of the voltage-current converter 3.
The voltage-current converter 3 converts the input first voltage signal V1 into the second current signals I31 and I32, and outputs the second current signals I31 and I32 to the output unit 4. In the voltage-current converter 3, the power supply terminal is supplied with the DC voltage having the first DC power supply VCC1.
The output unit 4 includes a third current mirror circuit 41 and a fourth current mirror circuit 42. The third current mirror circuit 41 and the fourth current mirror circuit 42 are formed in a manner similar to the first current mirror circuit 11 and the second current mirror circuit 12 in
In the third current mirror circuit 41, a power supply terminal is supplied with a DC voltage of a second DC power supply VCC2 having a value different from that of the first DC power supply VCC1, and a reference current terminal is connected to a third terminal i of the voltage-current converter 3. In the fourth current mirror circuit 42, a power supply terminal is grounded, and a reference current terminal is connected to a fourth terminal j of the voltage-current converter 3. A mirror current terminal of the third current mirror circuit 41 is connected to a mirror current terminal of the fourth current mirror circuit 42 via the output terminal OUT.
The third current mirror circuit 41 generates a current I41 of a predetermined mirror ratio as a mirror current of the second current signal I31 flowing through the third terminal i of the voltage-current converter 3. The fourth current mirror circuit 42 generates a current I42 of a predetermined mirror ratio as a mirror current of the second current signal 132 flowing through the fourth terminal j of the voltage-current converter 3. A difference between the current I41 and the current I42 is output as the output current Io to the output terminal OUT. When the output current Io is larger, the current I41 and the output current Io are substantially equal, and the current I42 is substantially zero.
A first resistor R1 can also be provided. The first resistor R1 is connected in parallel with the reference current of the third current mirror circuit 41, that is, between the first main electrode and the second main electrode of the first transistor Q1 through which the second current signal I31 flows. Moreover, a second resistor R2 can also be provided. The second resistor R2 is connected in parallel with the reference current of the fourth current mirror circuit 42, that is, between the first main electrode and the second main electrode of the third transistor Q3 through which the second current signal I32 flows. By providing the output unit 4 with the first resistor R1 and the second resistor R2, a no-load current of the output unit 4 can be absorbed and hence reduced by the first resistor R1 and the second resistor R2.
The voltage-current converter 3 converts the input first voltage signal V1 into second current signals I31 and I32 input to the output unit 4 formed by the third current mirror circuit 41 and the fourth current mirror circuit 42, and outputs the second current signals I31 and I32. By constituting the output unit 4 by the third current mirror circuit 41 and the fourth current mirror circuit 42, an output impedance of the output unit 4 can be increased. In addition, the method of increasing the output impedance of the output unit 4 is not limited to using the output unit 4 formed by the third current mirror circuit 41 and the fourth current mirror circuit 42. Moreover, by constituting the output unit 4 by the third current mirror circuit 41 and the fourth current mirror circuit 42, as shown in
The voltage-current converter 3 and the output unit 4 constitute a class AB amplifier 6. The bias circuit 20 supplies the first voltage signal V1 to the voltage-current converter 3. The first voltage signal V1 is obtained by adding a voltage obtained from current-voltage conversion of the mirror currents I21 and I22 of the first current signals I11 and I12 corresponding to the input signals Vin and Ierr and a bias voltage of the class AB amplifier 6. By constituting the class AB amplifier 6 by the voltage-current converter 3 and the output unit 4, the linear power circuit 100 is provided with a sink ability to suppress an overshoot of the output voltage Vo when an output load changes. Moreover, according to an application procedure, the linear power circuit 100 can exclude the sink ability.
The current feedback operational amplifier 5 is configured to increase transformer impedance by the bias circuit 20. The so-called transformer impedance of the current feedback operational amplifier is equivalent to an open-loop gain in a voltage feedback operational amplifier, and an error in the gain can be reduced by increasing the transformer impedance. In addition, the method for increasing the transformer impedance of the current feedback operational amplifier 5 is not limited to using the bias circuit 20.
Moreover, the voltage feedback operational amplifier usually includes therein a capacitor for phase compensation. In comparison, the current feedback operational amplifier 5 according to an embodiment does not include therein a capacitor for phase compensation. In substitution, the phase compensation of the linear power circuit 100 can be performed by an external output capacitor CL connected between the output terminal OUT and the ground. By increasing the output impedance of the output unit 4, a first pole of the linear power circuit 100 can be implemented by using the external output capacitor CL for the phase compensation, achieving stable operations of the linear power circuit 100. By adjusting capacitance of the external output capacitor CL, the position of the first pole can be easily adjusted. Moreover, a frequency based on the first pole of the output capacitor CL can be reduced by increasing the output impedance of the output unit 4, hence achieving stable operations of the linear power circuit 100.
When the linear power circuit 100 is configured as a buffer amplifier, since the linear power circuit 100 is configured to use a current feedback operational amplifier, a feedback resistor Rf for flowing the feedback current Ierr is inserted on a path connecting the output terminal OUT and the negative input terminal INN. Moreover, a feedback capacitor Cf can also be connected in parallel with the feedback resistor Rf. When phase advance compensation of the linear power circuit 100 is needed, the position of a second pole can be easily adjusted by adjusting capacitance of the external feedback capacitor Cf.
As shown in
Compared to the overshoot, undershoot and response time of the linear power circuit 100, the overshoot, undershoot and response time become at least 10 times in a linear power circuit using a voltage feedback operational amplifier.
In the linear power circuit 100 of the embodiment above, the overshoot, undershoot and response time during a load response can be minimized. That is to say, in the linear power circuit 100, a linear power circuit having fast load response characteristics can be provided, and the linear power circuit can suppress the change in the output voltage when the load current changes sharply to smaller magnitude.
In addition, by minimizing the overshoot and undershoot during a load response, the linear power circuit 100 is capable of reducing the capacitance of the external output capacitor CL, hence achieving a smaller number of parts, lower costs and a smaller area.
In addition, by minimizing the overshoot and undershoot during a load response, the linear power circuit 100 is suitable for internal power supplies of such as low dropout (LDO) regulators and various large-scale integrations (LSI).
Moreover, the embodiments above are examples of the present disclosure. Thus, the present disclosure is not limited to the embodiments, and various modifications in form of other than those of the embodiments may be made according to such as designs without departing from the scope of the technical concept of the present disclosure. (Notes)
A linear power circuit (100) includes:
With the linear power circuit (100) according to Note 1, effects of a linear power circuit that provides fast load response characteristics can be achieved. Moreover, by constituting the output unit (4) by the current mirror circuit (41, 42), an output impedance of the output unit (4) can be increased.
In the linear power circuit (100) of Note 1, the input unit (1) includes:
In the linear power circuit (100) of Note 2, the buffer circuit (10) comprises a single ended push-pull (SEPP) circuit.
The linear power circuit (100) of Note 2 comprises a feedback resistor (Rf) connected between the second input terminal (INN) and the output terminal (OUT). The linear power circuit (100) of Note 4 comprises the feedback resistor (Rf) connected between the second input terminal (INN) and the output terminal (OUT) and can input the feedback current (Ierr) from the output terminal (OUT) to the second input terminal (INN).
The linear power circuit (100) of Note 4 includes a feedback capacitor (Cf) connected in parallel with the feedback resistor (Rf). According to the linear power circuit (100) of Note 5, when phase compensation of the linear power circuit (100) is needed, the position of a second pole can be easily adjusted by adjusting capacitance of the external feedback capacitor (Cf).
In the linear power circuit (100) of any one of Notes 1 to 5, the voltage-current converter (3) and the output unit (4) constitute a class AB amplifier (6). According to the linear power circuit (100) of Note 6, the voltage-current converter (3) and the output unit (4) constitute a class AB amplifier (6), and so the linear power circuit (100) is provided with a sink ability to suppress an overshoot of the output voltage (Vo) when an output load changes.
In the linear power circuit (100) of Note 6, the current-voltage converter (2) includes a bias circuit (20) for the class AB amplifier (6). According to the linear power circuit (100) of Note 7, a gain error can be reduced by increasing transformer impedance by the bias circuit (20).
The linear power circuit (100) of any one of Notes 1 to 7 further includes a resistor (R1, R2) connected in parallel with the current mirror circuit (41, 42). According to the linear power circuit (100) of Note 8, the resistor (R1, R2) connected in parallel with the current mirror circuit (41, 42) can absorb and hence reduce a no-load current of the output unit (4).
In the linear power circuit (100) of any one of Notes 1 to 8, a power supply voltage (VCC1) supplied to the input unit (1) and a power supply voltage (VCC2) supplied to the output unit (4) are different. According to the linear power circuit (100) of Note 9, since the first DC power supply (VCC1) of the input unit (1) and the second DC power supply (VCC2) of the output unit (4) can be differentiated, a wide power supply voltage range can be handled in the linear power circuit 100.
In the linear power circuit (100) of any one of Notes 1 to 8, a power supply voltage (VCC1) supplied to the input unit (1) and the output unit (4) is common. According to the linear power circuit (100) of Note 10, since the power supply voltage (VCC1) supplied to the input unit (1) and the output unit (4) is common, the configuration of the linear power circuit (100) can be simplified.
In the linear power circuit (100) of any one of Notes 1 to 10, a phase compensation is performed by an external output capacitor (CL) connected between the output terminal (OUT) and a ground. According to the linear power circuit (100) of Note 11, a first pole of the linear power circuit (100) can be implemented by using the external output capacitor (CL) for the phase compensation, achieving stable operations of the linear power circuit (100).
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-048152 | Mar 2023 | JP | national |
