Patent Grant
11449085
The invention disclosed herein relates to linear power supplies.
Today, linear power supplies (series regulators such as LDO [low drop-out] regulators) are used as a means for power supply in a variety of devices.
Patent Document 1: Unexamined Japanese patent application publication No. 2018-112963
Patent Document 2: Unexamined Japanese patent application publication No. 2016-200989
A linear power supply that is supplied with a not very stable input voltage (e.g., a battery voltage) has to be configured to provide satisfactory response characteristics (i.e., input transient response characteristics) to cope with transient variations in the input voltage. This is because, with poor input transient response characteristics, a variation in the input voltage results in a variation in the output voltage, possibly leading to poor characteristics, a breakdown, or the like in the load. In particular, nowadays, as linear power supplies are supplied with increasingly low voltages, they are expected to meet increasingly strict requirements in terms of input transient response characteristics.
While the present inventors have hitherto proposed linear power supplies with enhanced input transient response characteristics (Patent Documents 1 and 2 identified below), they still leave room for further improvement when application in a wide load range is taken into account.
In view of the above-mentioned challenge encountered by the present inventors, an object of the invention disclosed herein is to provide a linear power supply that offers enhanced input transient response characteristics over a wide load range.
According to one aspect of what is disclosed herein, a linear power supply includes: an output transistor connected between an input terminal for an input voltage and an output terminal for an output voltage; a driver configured to drive the output transistor such that a feedback voltage commensurate with the output voltage remains equal to a reference voltage; a current detector configured to sense an output current passing through the output transistor; and a voltage adjuster configured to adjust the reference voltage or the feedback voltage such that the differential voltage between a first voltage commensurate with the input voltage and a second voltage commensurate with the output voltage or the reference voltage does not fall below an offset voltage commensurate with the output current.
According to another aspect of what is disclosed herein, a linear power supply includes: an output transistor connected between an input terminal for an input voltage and an output terminal for an output voltage; a first amplifier configured to generate a first driving signal by amplifying the difference between the output voltage or a voltage commensurate therewith and a predetermined reference voltage; a second amplifier configured to generate a second driving signal by amplifying the difference between the input voltage or a voltage commensurate therewith and the output voltage or a voltage commensurate therewith; a driver configured to drive the output transistor in accordance with the first and second driving signal; a current detector configured to generate a control signal by sensing an output current passing through the output transistor; and an offset adder configured to feed the second amplifier with an offset voltage commensurate with the control signal.
Other features, elements, steps, benefits, and characteristics of the present invention will become clear through the following detailed description of embodiments and the accompanying drawings associated therewith.
According to the invention disclosed herein, it is possible to provide a linear power supply that offers enhanced input transient response characteristics over a wide load range.
First, prior to a description of novel embodiments (a first to an eighth embodiment) related to linear power supplies, a comparative example to be compared with them will be described in brief.
The output transistor 10 is connected between an input terminal for the input voltage VIN and an output terminal for the output voltage VOUT, and the conductivity of the output transistor 10 (reversely put, its on-state resistance value) is controlled in accordance with a gate signal G10 from the driver 30. In the illustrated example, as the output transistor 10, a PMOSFET (P-channel MOSFET) is used. Accordingly, the lower the gate signal G10, the higher the conductivity of the output transistor 10, and thus the higher the output voltage VOUT; the higher the gate signal G10, the lower the conductivity of the output transistor 10, and thus the lower the output voltage VOUT. As the output transistor 10, instead of a PMOSFET, an NMOSFET may be used, or a bipolar transistor may be used.
The voltage divider 20 includes resistors 21 and 22 (with resistance values R1 and R2) that are connected in series between the output terminal for the output voltage VOUT and a grounded terminal, and outputs from the connection node between those resistors a feedback voltage VFB (=VOUT×[R2/(R1+R2)]) commensurate with the output voltage VOUT. Instead, in a case where the output voltage VOUT falls within the input dynamic range of the driver 30, the voltage divider 20 may be omitted, in which case, as the feedback voltage VFB, the output voltage VOUT itself may be fed directly to the driver 30.
The driver 30 drives the output transistor 10 by generating the gate signal G10 such that the feedback voltage VFB, which is fed to the non-inverting input terminal (+) of the driver 30, remains equal to a predetermined reference voltage VREF, which is fed to the inverting input terminal (−) of the driver 30. More specifically, the larger the difference ΔV (=VFB−VREF) between the feedback voltage VFB and the reference voltage VREF, the more the driver 30 raises the gate signal G10; the smaller the difference ΔV, the more the driver 30 lowers the gate signal G10.
The reference voltage adjuster 40 includes an offset adder 41, a differential amplifier 42, and a variable voltage source 43. The reference voltage adjuster 40 has a function of adjusting the reference voltage VREF such that the output transistor 10 does not enter a fully on state, in other words, so as to avoid a state in which the driver 30 has lowered the gate signal G10 to as low a level as it can.
The offset adder 41 offsets the output voltage VOUT to the high-potential side by a predetermined offset voltage Voffset. Preferably the offset voltage Voffset is set at a voltage value lower than the minimum input-output voltage difference VSAT defined for the linear power supply 1 (more detail will be given later).
The differential amplifier 42 generates a control signal S43 for the variable voltage source 43 in accordance with the input voltage VIN, which is fed to the inverting input terminal (−) of the differential amplifier 42, and the offset output voltage (=VOUT+Voffset), which is fed to the non-inverting input terminal (+) of the differential amplifier 42.
The variable voltage source 43 includes an NMOSFET (N-channel MOSFET) 43a and a resistor 43b, and adjusts the voltage value of the reference voltage VREF in accordance with the control signal S43 output from the differential amplifier 42.
The NMOSFET 43a is connected between the inverting input terminal (−) of the driver 30 (i.e., an output terminal for the reference voltage VREF) and the grounded terminal, and the conductivity of the NMOSFET 43a is controlled in accordance with the control signal S43 (i.e., gate signal) output from the differential amplifier 42. Accordingly the drain current I43a that passes through the NMOSFET 43a is higher the higher the control signal S43, and is lower the lower the control signal S43.
The resistor 43b (with a resistance value R43b) is connected between an application terminal for a reference voltage VREF0 (corresponding to the steady-state value of the reference voltage VREF) and the inverting input terminal (−) of the driver 30. The resistor 43b receives the drain current I43a that passes through the NMOSFET 43a and thus lowers the reference voltage VREF0 by the voltage drop (I43a×R43b) across the resistor 43b, which thereby generates the reference voltage VREF (=VREF0−I43a×R43b). That is, the reference voltage VREF has the steady-state value (=VREF0) when I43a=0A, and lowers from the steady-state value the more the higher the drain current 143a.
In the linear power supply 1 of this embodiment, when the differential voltage (VIN−VOUT) between the input voltage VIN and the output voltage VOUT is higher than the offset voltage Voffset, the control signal S43 is held at low level, thereby to keep the NMOSFET 43a off and hold the reference voltage VREF at the steady-state value.
On the other hand, when the differential voltage (VIN−VOUT) falls down to the offset voltage Voffset, to prevent a further fall, the control signal S43 is raised, thereby to pass the drain current I43a through the NMOSFET 43a and lower the reference voltage VREF from the steady-state value.
While the above description deals with a configuration where the output voltage VOUT is offset, a configuration is also possible where, instead, the input voltage VIN is offset. Specifically, as indicated in parentheses in
Prior to a discussion of the significance of introducing the reference voltage adjustment function described above, a brief description will be given of input transient response characteristics observed when the reference voltage VREF has a fixed value.
Suppose, for the sake of discussion, the reference voltage VREF has a fixed value. In that case, when the input voltage VIN falls until it becomes lower than a target output value Vtarget (a target value for the output voltage VOUT), the feedback voltage VFB stays constantly lower than the reference voltage VREF. As a result, the driver 30 enters a state in which it has lowered the gate signal G10 to as low a level as it can, and thus the output transistor 10 enters the fully on state (see from time point t12 to time point t15). That is, the driver 30 enters a state in which it operates like a comparator.
When from this state the input voltage VIN rises sharply to a voltage higher than the target output value Vtarget, the driver 30 tends to raise the gate signal G10 to turn off the output transistor 10. However, the gate signal G10, now fallen fully down to low level, is difficult to raise in a way to immediately follow the sharp change in the input voltage VIN. As a result, with the output transistor 10 left in the fully on state, the input voltage VIN is output as it is, causing an overshoot in the output voltage VOUT (see from time point t15 to time point t17). Such an overshoot may lead to the load 2 malfunctioning or breaking down.
The speed at which the output transistor 10 is turned off depends on the response speed of the driver 30, the current capacity in the output stage of the driver 30, the impedances of internal terminals in the driver 30, the gate capacity of the output transistor 10, etc. On the other hand, the convergence time of an overshoot depends on the characteristics (phase margin, response speed) of the driver 30.
Next, a brief description will be given of input transient response characteristics observed when the reference voltage VREF has a variable value.
In the linear power supply 1 of this comparative example, the reference voltage adjuster 40 monitors both the input voltage VIN and the output voltage VOUT. When the differential voltage (VIN−VOUT) between the two voltages is higher than the offset voltage Voffset, the reference voltage adjuster 40 holds the reference voltage VREF at the steady-state value (see before time point t22, or after time point t25); when the differential voltage (VIN−VOUT) falls down to the offset voltage Voffset, to prevent a further fall, the reference voltage adjuster 40 lowers the reference voltage VREF from the steady-state value (see from time point t22 to time point t25).
Through the reference voltage adjustment operation described above, even if the input voltage VIN falls, the target value of the output voltage VOUT can be kept constantly lower than the input voltage VIN. This prevents the output transistor 10 from entering the fully on state, and thus the driver 30 keeps the gate signal G10 at an adequate voltage value (e.g., VIN−Vth, where Vth is the on-threshold voltage of the output transistor 10).
Once in this way the output transistor 10 is prevented from entering the fully on state in response to a fall in the input voltage VIN, even if thereafter the input voltage VIN rises sharply, the gate signal G10 can be raised in a way to immediately follow the gate signal G10. It is thus possible to minimize an overshoot in output voltage VOUT.
Here, lowering the reference voltage VREF entails the output voltage VOUT falling below the intended target value. A fall in the output voltage VOUT may lead to degraded characteristics in the load 2 that is connected in the succeeding stage, and thus the reference voltage VREF needs to be adjusted within such a range as not to bring an adverse effect.
One possible criterion is the minimum input-output voltage difference VSAT defined for the linear power supply 1. The minimum input-output voltage difference VSAT corresponds to the lowest input-output voltage difference (i.e., the differential voltage (=Vin−VOUT) between the input voltage VIN and the output voltage VOUT) that is needed to stably supply a predetermined output current IOUT from the linear power supply 1 to the load 2; generally the minimum input-output voltage difference VSAT depends on the on-state resistance value RON of the output transistor 10 in the fully on state and the current value of the output current IOUT that passes in that state.
In view of the foregoing, it can safely be said that preferably the offset voltage Voffset (corresponding to the degree of the lowering of the output voltage VOUT in response to a fall in the input voltage VIN) is set at a voltage value lower than the minimum input-output voltage difference VSAT. With such a voltage selected, even if the reference voltage adjustment operation described above causes a fall in the output voltage VOUT, it does not interfere with the stable operation of the linear power supply 1.
Though no mention has been made with reference to
Here, in a load region where the output current IOUT passing through the output transistor 10 is low and IOUT×RON<Voffset (called a light-load region in the following description), the reference voltage adjustment function described previously works, so as to suppress an overshoot in the output voltage VOUT resulting from a sharp change in the input voltage VIN.
On the other hand, in a load region where the output current IOUT passing through the output transistor 10 is high and IOUT×RON>Voffset (called a heavy-load region in the following description), the differential voltage (VIN−VOUT) between the input voltage VIN and the output voltage VOUT does not fall below the offset voltage Voffset. As a result, the control signal S43 is constantly at low level, and thus the NMOSFET 43a is kept off, bringing a state where the reference voltage VREF is held at the steady-state value (i.e., a state where the reference voltage adjustment function described previously does not work).
As mentioned previously, in a heavy-load region, the reference voltage adjustment function does not work, and the reference voltage VREF remains held at the steady-state value. Accordingly, when the input voltage VIN lowers until VIN<Vtarget+ION×RON, the output voltage VOUT can no longer be kept at the target output value Vtarget, and thus the feedback voltage VFB stays constantly below the reference voltage VREF. As a result, the driver 30 enters a state where it has lowered the gate signal G10 to as low a level as it can, and thus the output transistor 10 enters the fully on state (see from time point t32 to time point t35).
When from this state the input voltage VIN rises sharply until VIN>Vtarget+ION×RON, the driver 30 tends to raise the gate signal G10 to turn off the output transistor 10. However, the gate signal G10, now fallen fully down to low level, is difficult to raise in a way to immediately follow the sharp change in the input voltage VIN. As a result, with the output transistor 10 left in the fully on state, the input voltage VIN is output as it is, causing an overshoot in the output voltage VOUT (see from time point t35 to time point t37).
As described above, the input transient response characteristics observed in a heavy-load region (
Incidentally, the simplest solution to the inconvenience mentioned above is to raise the offset voltage Voffset. However, an offset voltage Voffset raised on a constant basis causes, in response to a fall in the input voltage VIN, a large fall in the output voltage VOUT irrespective of load heaviness, possibly leading to degraded characteristics.
Proposed below will be various embodiments that provide a solution to the inconvenience mentioned above.
The reference voltage adjuster 40 adjusts the reference voltage VREF such that the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT does not fall below the offset voltage Voffset. More specifically, when the differential voltage (=VIN−VOUT) is higher than the offset voltage Voffset, the 40 holds the reference voltage VREF at the steady-state value; when differential voltage (=VIN−VOUT) falls down to the offset voltage Voffset, to prevent a further fall, the reference voltage adjuster 40 lowers the reference voltage VREF from the steady-state value. This basic operation is no different from that in the comparative example (
The current detector 50 senses the output current IOUT that passes through the output transistor 10, and feeds a sense current commensurate with its current value (e.g., a sense current corresponding to 1/m of the output current IOUT, or a mirror current of such a sense current) to the offset adder 41.
The offset adder 41 is a circuit block that shifts the output voltage VOUT to the high-potential side by the offset voltage Voffset, and additionally has a function of variably controlling the offset voltage Voffset in accordance with a control signal from the current detector 50. The offset voltage Voffset is higher the higher the output current IOUT, and is lower the lower the output current IOUT.
First, the output behavior shown in
Next, the output behavior shown in
However, in a heavy-load region (IOUT>Voffset/RON), the reference voltage adjustment function no longer works. Accordingly, as the input voltage VIN falls, the output transistor 10 may enter the fully on state, and thus the output voltage VOUT may suffer an overshoot. Raising the offset voltage Voffset may widen the load range in which the reference voltage adjustment function works, but as mentioned previously, that is done in a trade-off for a larger fall in output under a light load.
Next, the output behavior shown in
Accordingly, when the input voltage VIN falls, the reference voltage adjustment function described previously works irrespective of the load condition. As a result, it is possible to prevent the output transistor 10 from entering the fully on state over a wide load region, and hence to suppress an overshoot in the output voltage VOUT over a wide load region and thereby enhance the input transient response characteristics of the linear power supply 1.
Moreover, the offset voltage Voffset is set to be minimal in accordance with the output current IOUT; thus in particular under no load (IOUT=0 A) or in a light-load region (IOUT<Voffset/RON) it is possible to prevent an unnecessary fall in the output voltage VOUT.
With the linear power supply 1 of this embodiment, through the reference voltage adjustment operation described previously, even when the input voltage VIN falls, the target value of the output voltage VOUT can be kept constantly lower than the input voltage VIN. Thus the output transistor 10 does not enter the fully on state, and the gate signal G10 is kept at an adequate voltage value. Certainly, as the load is increasingly heavy, the gate signal G10 falls to pass an increasingly high output current IOUT; even then the gate signal G10 is not lowered to as low a level as the driver 30 can.
Preventing in this way the output transistor 10 from entering the fully on state in response to a fall in the input voltage VIN makes it possible, even if thereafter the input voltage VIN rises sharply, to raise the gate signal G10 in a way to immediately follow the sharp change. It is thus possible to minimize an overshoot in the output voltage VOUT.
Moreover, with the linear power supply 1 of this embodiment, in accordance with the output current IOUT, the offset voltage Voffset is variably controlled. This helps keep the degree of the lowering of the output voltage VOUT (i.e., the offset voltage Voffset) the smaller the lighter the load (the lower the output current IOUT). It is thus possible to keep an adequate output voltage VOUT.
The constant voltage source 60 generates a predetermined reference voltage VREF and feeds it to the inverting input terminal (−) of the driver 30.
The feedback voltage adjuster 70 is a circuit block that adjusts the feedback voltage VFB such that the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT does not fall below the offset voltage Voffset. The feedback voltage adjuster 70 includes an offset adder 71, a differential amplifier 72, and a variable voltage source 73.
The offset adder 71 is a circuit block that shifts the output voltage VOUT to the high-potential side by the offset voltage Voffset, and as in the first embodiment (
The differential amplifier 72 generates a control signal S73 for the variable voltage source 73 in accordance with the input voltage VIN, which is fed to the inverting input terminal (−) of the differential amplifier 72, and the offset output voltage (=VOUT+Voffset), which is fed to the non-inverting input terminal (+) of the differential amplifier 72.
The variable voltage source 73 adjusts the voltage value of the feedback voltage VFB in accordance with the control signal S73 output from the differential amplifier 72. More specifically, while the control signal S73 is kept at low level, the variable voltage source 73 does not shift the feedback voltage VFB but feeds it as it is to the non-inverting input terminal (+) of the driver 30; when the control signal S73 rises from low level, the variable voltage source 73 shifts the feedback voltage VFB to the high-potential side the more the higher the voltage value of the control signal S73.
That is, when the differential voltage (=VIN−VOUT) is higher than the offset voltage Voffset, the feedback voltage adjuster 70 delivers the feedback voltage VFB as it is to the driver 30; when the differential voltage ('VIN−VOUT) falls down to the offset voltage Voffset, to prevent the differential voltage (=VIN−VOUT) from further falling, the feedback voltage adjuster 70 delivers the feedback voltage VFB after raising it to the driver 30.
In this way, preventing the output transistor 10 from entering the fully on state can be achieved by adjusting, instead of the reference voltage VREF, the feedback voltage VFB.
The voltage divider 20a includes resistors 23 and 24 (with resistance values R3 and R4) connected in series between the application terminal for the input voltage VIN and the grounded terminal, and outputs from the connection node between those resistors a divided input voltage VIN2 (=VIN×[R4/(R3+R4)]) commensurate with the input voltage VIN.
Here, appropriately selecting the resistors 21 to 24 such that R1:R2=R3:R4 provides a configuration equivalent to one where the reference voltage adjuster 40 is differentially fed with the input voltage VIN and the output voltage VOUT, and it is thus possible to achieve effects similar to those achieved with the first embodiment (
As shown in a balloon in
The source of the PMOSFET 52 is connected to the drain of the PMOSFET 51. The source of the PMOSFET 53 is connected to the drain of the output transistor 10 (i.e., the application terminal for the output voltage VOUT). The respective gates of the PMOSFETs 52 and 53 are both connected to the drain of the PMOSFET 53. The drain of the PMOSFET 53 is connected to the first terminal of the current source 54. The second terminal of the current source 54 is connected to the grounded terminal.
Providing a biasing means as described above helps keep the drain-source voltage of the PMOSFET 51 equal to the drain-source voltage of the output transistor 10. It is thus possible to more accurately generate the sense current I51 commensurate with the output current IOUT (hence the control signal to the offset adder 41).
First, the reference voltage adjuster 40 includes, instead of the offset adder 41 that shifts the reference voltage VREF to the high-potential side by the offset voltage Voffset, an offset adder 41a that shifts the divided input voltage VIN2 to the low-potential side by the offset voltage Voffset. That is, the differential amplifier 42 is differentially fed with the reference voltage VREF and the offset divided input voltage (=VIN2−Voffset). In this way, the offset voltage Voffset may, instead of being added to the reference voltage VREF, be subtracted from the divided input voltage VIN2.
Moreover, the current detector 50 further includes NMOSFETs 55 and 56 as a current mirror for generating a mirror current 155 commensurate with the sense current I51. The drain of the NMOSFET 56 is connected to the drain of the PMOSFET 51 (i.e., an output terminal for the sense current I51). The respective gates of the NMOSFETs 55 and 56 are connected to the drain of the NMOSFET 56. The respective sources of the NMOSFETs 55 and 56 are connected to the grounded terminal. The drain of the NMOSFET 55 is, as an output terminal for the mirror current I55, connected to the offset adder 41a. In this way, as the control signal for the offset adder 41a, a mirror current I55 commensurate with the sense current I51 may be used.
First, as in the third and fourth embodiments (
Moreover, the feedback voltage adjuster 70 includes, instead of the offset adder 71 that shifts the output voltage VOUT to the high-potential side by the offset voltage Voffset, an offset adder 71a that shifts the divided input voltage VIN2 to the low-potential side by the offset voltage Voffset. That is, the differential amplifier 72 is differentially fed with the reference voltage VREF and the offset divided input voltage (=VIN2−Voffset). In this way, the offset voltage Voffset may, instead of being added to the reference voltage VREF, be subtracted from the divided input voltage VIN2.
Furthermore, the variable voltage source 73 includes a PMOSFET 73a of which the conductivity is controlled based on the control signal S73 output from the differential amplifier 72. The gate of the PMOSFET 73a is connected to the output terminal of the differential amplifier 72 (i.e., an application terminal for the control signal S73). The drain of the PMOSFET 73a (an output terminal for the drain current I73a) is connected to an application terminal for the feedback voltage VFB (the connection node between the resistors 21 and 22). The source of the PMOSFET 73a is connected to an internal power source that has a sufficient current capacity to supply the drain current I73a.
The use of the PMOSFET 73a as the variable voltage source 73 entails the reversal of the input polarities of the differential amplifier 72. More specifically, the inverting input terminal (−) of the differential amplifier 72 is fed with the reference voltage VREF, and the non-inverting input terminal (+) of the differential amplifier 72 is fed with the offset divided input voltage (=VIN2−Voffset).
With this configuration, in accordance with the drain current I73a that passes through the PMOSFET 73a, the feedback voltage VFB can be adjusted. Specifically, while the control signal S73 is kept at high level, the PMOSFET 73a is off; thus the drain current I73a does not pass. Accordingly the feedback voltage VFB is not shifted but is as it is fed to the non-inverting input terminal (+) of the driver 30. On the other hand, when the control signal S73 falls from high level, the lower its voltage value, the higher the conductivity oft PMOSFET 73a and thus the higher the drain current I73a that passes through the resistor 22; thus the feedback voltage VFB is shifted to the high-potential side accordingly.
Moreover, as in the fourth embodiment (
Here, appropriately selecting the resistors 21 to 24 such that R1:R2=R3:R4 makes it possible, owing to a deviation in resistance ratio resulting from the insertion of the resistor 25, to generate the offset voltage Voffset.
First, the non-inverting input terminal (+) of the differential amplifier 42 is fed with, instead of the reference voltage VREF, the feedback voltage VFB (i.e., a division voltage of the output voltage VOUT). In this way, in the reference voltage adjuster 40, the reference voltage VREF may be adjusted such that the differential voltage (=VIN2−VFB) between the divided input voltage VIN2 and the feedback voltage VFB does not fall below the offset voltage Voffset.
Moreover, the reference voltage adjuster 40 further includes a resistor 43c (with a resistance value R43c) connected between the output terminal for the reference voltage VREF and the grounded terminal. In this case, the steady-state value of the reference voltage VREF (i.e., the reference voltage VREF as it is when the drain current I43a equals 0 A) equals VREF0×[R43c/(R43b+R43c)]. In this way, the steady-state value of the reference voltage VREF may be set by dividing a given constant voltage (VREF0).
The above modification entails the reversal of the input polarities of the differential amplifier 42. More specifically, the differential amplifier 42 generates the control signal S43 for the variable voltage source 43 (i.e., the gate signal for the PMOSFET 43d) in accordance with the input voltage VIN, which is fed to the non-inverting input terminal (+) of the differential amplifier 42, and the offset output voltage (=VOUT+Voffset), which is fed to the inverting input terminal (−) of the differential amplifier 42.
The linear power supply 1 of this embodiment provides workings and effects similar to those achieved with the third embodiment (
The first to eighth embodiments that have been described above can be implemented in any combination unless inconsistent. For example, in the fourth, sixth, or seventh embodiment (
Next, prior to a description of other novel embodiments (a ninth to a fifteenth embodiment), comparative examples to be compared with them will be described in brief.
The output transistor 110 is connected between an input terminal for the input voltage VIN and an output terminal for the output voltage VOUT, and the conductivity of the output transistor 110 (reversely put, its on-state resistance value) is controlled in accordance with a gate signal G10 from the amplifier 130. In the illustrated example, as the output transistor 110, a PMOSFET (P-channel MOSFET) is used. Accordingly, the lower the gate signal G10, the higher the conductivity of the output transistor 110, and thus the higher the output voltage VOUT; the higher the gate signal G10, the lower the conductivity of the output transistor 110, and thus the lower the output voltage VOUT. As the output transistor 110, instead of a PMOSFET, an NMOSFET may be used, or a bipolar transistor may be used.
The voltage divider 120 includes resistors 121 and 122 (with resistance values R1 and R2) that are connected in series between the output terminal for the output voltage VOUT and a grounded terminal, and outputs from the connection node between those resistors a feedback voltage VFB (=VOUT×[R2/(R1+R2)]) commensurate with the output voltage VOUT. Instead, in a case where the output voltage VOUT falls within the input dynamic range of the driver 130, the voltage divider 120 may be omitted, in which case, as the feedback voltage VFB, the output voltage VOUT itself may be fed directly to the amplifier 130.
The amplifier 130 drives the output transistor 110 by generating the gate signal G10 such that the feedback voltage VFB, which is fed to the non-inverting input terminal (+) of the amplifier 130, remains equal to a predetermined reference voltage VREF, which is fed to the inverting input terminal (−) of the amplifier 130. More specifically, the larger the difference ΔV (=VFB−VREF) between the feedback voltage VFB and the reference voltage VREF, the more the amplifier 130 raises the gate signal G10; the smaller the difference ΔV, the more the amplifier 130 lowers the gate signal G10.
The reference voltage generator 140 generates from the input voltage VIN the reference voltage VREF (with a fixed value). Suitably usable as the reference voltage generator 140 is, for example, a band-gap voltage source, which has low supply dependence and low temperature dependence.
In a case where the reference voltage VREF has a fixed value, when the input voltage VIN falls until it becomes lower than a target output value Vtarget (a target value for the output voltage VOUT), the feedback voltage VFB stays constantly below the reference voltage VREF. As a result, the amplifier 130 enters a state in which it has lowered the gate signal G10 to as low a level as it can, and thus the output transistor 110 enters the fully on state (see from time point t112 to time point t115). That is, the amplifier 130 enters a state in which it operates like a comparator.
When from this state the input voltage VIN rises sharply to a voltage higher than the target output value Vtarget, the amplifier 130 tends to raise the gate signal G10 to turn off the output transistor 110. However, the gate signal G10, now fallen fully down to low level, is difficult to raise in a way to immediately follow the sharp change in the input voltage VIN. As a result, with the output transistor 110 left in the fully on state, the input voltage VIN is output as it is, causing an overshoot in the output voltage VOUT (see from time point t115 to time point t117). Such an overshoot may lead to the load 102 malfunctioning or breaking down.
The speed at which the output transistor 110 is turned off depends on the response speed of the amplifier 130, the current capacity in the output stage of the amplifier 130, the impedances of internal terminals in the amplifier 130, the gate capacity of the output transistor 110, etc. On the other hand, the convergence time of an overshoot depends on the characteristics (phase margin, response speed) of the amplifier 130.
The amplifier 131 outputs a gate signal G1 (corresponding to a first driving signal) by amplifying the difference (=VREF−VFB) between the feedback voltage VFB, which is fed to the inverting input terminal (−) of the amplifier 131, and the reference voltage VREF, which is fed to the non-inverting input terminal (+) of the amplifier 131. The amplifier 131 constitutes a first output feedback loop for keeping the feedback voltage VFB and the reference voltage VREF equal.
The amplifier 132 outputs a gate signal G2 (corresponding to a second driving signal) by amplifying the difference (=VIN−(VOUT+Voffset)) between the input voltage VIN, which is fed to the non-inverting input terminal (+) of the amplifier 132, and the offset output voltage (=VOUT+Voffset), which is fed to the inverting input terminal (−) of the amplifier 132. The amplifier 132 constitutes a second output feedback loop for keeping the input voltage VIN and the offset output voltage (=VOUT+Voffset) equal.
The offset adder 150 is a circuit block that feeds the amplifier 132 with a predetermined offset voltage Voffset. More specifically, the offset adder 150 feeds the output voltage VOUT, for example after shifting it to the high-potential side by the predetermined offset voltage Voffset, to the non-inverting input terminal (+) of the amplifier 132. Preferably the offset voltage Voffset is set at a voltage value lower than the minimum input-output voltage difference VSAT defined for the linear power supply 101.
The gate driver 160 is a circuit block that, with the output terminal of the amplifier 131 diverted to it instead of being directly connected to the gate of the output transistor 110, receives the gate signals G1 and G2 parallelly as a two-channel output feedback signals to generate, in accordance with the gate signals G1 and G2, the gate signal G10 for the output transistor 110. The gate driver 160 includes PMOSFETs 161 and 162, a current source 163, and a resistor 164.
The source of the PMOSFET 161 is connected to the input terminal for the input voltage VIN. The drain of the PMOSFET 161 is connected to the gate of the output transistor 110. The gate of the PMOSFET 161 is connected to an application terminal for the gate signal G1 (i.e., the output terminal of the amplifier 131). Thus the conductivity of the PMOSFET 161 varies with the gate signal G1.
The source of the PMOSFET 162 is connected to the input terminal for the input voltage VIN. The drain of the PMOSFET 162 is connected to the gate of the output transistor 110. The gate of the PMOSFET 162 is connected to an application terminal for the gate signal G2 (i.e., the output terminal of the amplifier 132). Thus the conductivity of the PMOSFET 162 varies with the gate signal G2.
The current source 163 is connected between the gate of the output transistor 110 and the grounded terminal, and generates a predetermined constant current.
The resistor 164 is a resistor with a high resistance value (e.g., several megohms) connected between the input terminal for the input voltage VIN and the gate of the output transistor 110.
When the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT is higher than the offset voltage Voffset, the amplifier 132 keeps the gate signal G2 raised at high level, and thus the PMOSFET 162 is off. Accordingly the amplifier 131 performs ordinary output feedback control (see before time point t122 or after time point t125).
On the other hand, when the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT falls down to the offset voltage Voffset, the amplifier 132 so operates as to apply output feedback control such that the input voltage VIN and the offset output voltage (=VOUT+Voffset) are imaginarily short-circuited together. Specifically, the conductivity of the PMOSFET 162 is changed such that the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT does not become higher than the offset voltage Voffset (see from time point t122 to time point t125).
As a result, the gate signal G10 for the output transistor 110 for the output transistor 110 now changes so as to follow the input voltage VIN while keeping a constant potential difference with respect to the input voltage VIN. That is, the gate signal G10 is no longer pegged at low level, and thus the output transistor 110 does not enter the fully on state.
Once in this way the output transistor 110 is prevented from entering the fully on state in response to a fall in the input voltage VIN, even if thereafter the input voltage VIN rises sharply, the gate signal G10 can be raised in a way to immediately follow the gate signal G10. It is thus possible to minimize an overshoot in output voltage VOUT.
Keeping the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT equal to the offset voltage Voffset entails the output voltage VOUT falling below the intended target output value Vtarget as the input voltage VIN falls. A fall in the output voltage VOUT may lead to degraded characteristics in the load 102 that is connected in the succeeding stage, and thus the offset voltage Voffset needs to be adjusted within such a range as not to bring an adverse effect.
One possible criterion is the minimum input-output voltage difference VSAT defined for the linear power supply 101. The minimum input-output voltage difference VSAT corresponds to the lowest input-output voltage difference (i.e., the differential voltage (=Vin−VOUT) between the input voltage VIN and the output voltage VOUT) that is needed to stably supply a predetermined output current IOUT from the linear power supply 101 to the load 102; generally the minimum input-output voltage difference VSAT depends on the on-state resistance value RON of the output transistor 110 in the fully on state and the current value of the output current IOUT that passes in that state.
In view of the foregoing, it can safely be said that preferably the offset voltage Voffset (corresponding to the degree of the lowering of the output voltage VOUT in response to a fall in the input voltage VIN) is set at a voltage value lower than the minimum input-output voltage difference VSAT. With such a voltage selected, even if the reference voltage adjustment operation described above causes a fall in the output voltage VOUT, it does not interfere with the stable operation of the linear power supply 1.
Though no mention has been made with reference to
Here, in a load region where the output current IOUT passing through the output transistor 110 is low and IOUT×RON<Voffset (called a light-load region in the following description), the output feedback control by the amplifier 132 works effectively, so as to suppress an overshoot in the output voltage VOUT resulting from a sharp change in the input voltage VIN.
On the other hand, in a load region where the output current IOUT passing through the output transistor 110 is high and IOUT×RON>Voffset (called a heavy-load region in the following description), the differential voltage (VIN−VOUT) between the input voltage VIN and the output voltage VOUT does not fall below the offset voltage Voffset. As a result, the gate signal G2 is constantly at high level, and thus the NMOSFET 43a is kept off, bringing a state where the output feedback control by the amplifier 132 does not work.
As mentioned previously, in a heavy-load region, the output feedback control by the amplifier 132 does not work. Thus, when the input voltage VIN falls until VIN<Vtarget+ION×RON, the output voltage VOUT can no longer be kept at the target output value Vtarget, and the feedback voltage VFB remains constantly below the reference voltage VREF. As a result, the amplifier 131 keeps the gate signal G1 raised at high level, and thus the PMOSFET 161 is off Thus the gate signal G10 is kept lowered at low level by the current source 163, and thus the output transistor 110 enters the fully on state (see from time point t132 to time point t135).
When from this state the input voltage VIN rises sharply until VIN>Vtarget+ION×RON, the amplifier 131 tends to lower the gate signal G1 to increase the conductivity of the PMOSFET 161, thereby to raise the gate signal G10 to turn off the output transistor 110. However, the gate signal G10, now fallen fully down to low level, is difficult to raise in a way to immediately follow the sharp change in the input voltage VIN. As a result, with the output transistor 110 left in the fully on state, the input voltage VIN is output as it is, causing an overshoot in the output voltage VOUT (see from time point t135 to time point t137).
As described above, the input transient response characteristics observed in a heavy-load region (
Incidentally, the simplest solution to the inconvenience mentioned above is to raise the offset voltage Voffset. However, an offset voltage Voffset raised on a constant basis causes, in response to a fall in the input voltage VIN, a large fall in the output voltage VOUT irrespective of load heaviness, possibly leading to degraded characteristics.
Proposed below will be various embodiments that provide a solution to the inconvenience mentioned above.
The current detector 170 senses the output current IOUT that passes through the output transistor 110, and feeds a sense current commensurate with its current value (e.g., a sense current corresponding to 1/m of the output current IOUT, or a mirror current of such a sense current; more detail will be given later) to the offset adder 150.
The offset adder 150 is a circuit block that shifts the output voltage VOUT to the high-potential side by the offset voltage Voffset, and additionally has a function of variably controlling the offset voltage Voffset in accordance with a control signal from the current detector 170. The offset voltage Voffset is higher the higher the output current IOUT, and is lower the lower the output current IOUT.
First, the output behavior shown in
Next, the output behavior shown in
However, in a heavy-load region (IOUT>Voffset/RON), the amplifier 132 no longer operates effectively. Accordingly, as the input voltage VIN falls, the output transistor 110 may enter the fully on state, and thus the output voltage VOUT may suffer an overshoot. Raising the offset voltage Voffset may widen the load range in which the amplifier 132 operates effectively, but as mentioned previously, that is done in a trade-off for a larger fall in output under a light load.
Next, the output behavior shown in
Accordingly, when the input voltage VIN falls, the output feedback control by the amplifier 132 works effectively irrespective of the load condition. As a result, it is possible to prevent the output transistor 110 from entering the fully on state over a wide load region, and hence to suppress an overshoot in the output voltage VOUT over a wide load region and thereby enhance the input transient response characteristics of the linear power supply 1.
Moreover, the offset voltage Voffset is set to be minimal in accordance with the output current IOUT; thus, in particular under no load (IOUT=0 A) or in a light-load region (IOUT<Voffset/RON), it is possible to prevent an unnecessary fall in the output voltage VOUT.
With the linear power supply 101 of this embodiment, through the above-described operation of the amplifier 132, even when the input voltage VIN falls, the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT can be kept equal to the offset voltage Voffset. Thus the output transistor 110 does not enter the fully on state, and the gate signal G10 is kept at an adequate voltage value. Certainly, as the load is increasingly heavy, the gate signal G10 falls to pass an increasingly high output current IOUT; even then the gate signal G10 is not lowered down to the ground level.
On the other hand, when differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT falls down to the offset voltage Voffset, through the operation of the amplifier 132, output feedback control is applied such that the input voltage VIN and the offset output voltage (=VOUT+Voffset) are imaginarily short-circuited together. Specifically, the conductivity of the PMOSFET 162 is changed such that the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT does not become higher than the offset voltage Voffset (see, in
As a result, the gate signal G10 for the output transistor 110 now changes so as to follow the input voltage VIN while keeping a predetermined potential difference with reference to the input voltage VIN. That is, the gate signal G10 is no longer pegged at low level, and thus the output transistor 110 does not enter the fully on state.
Preventing in this way the output transistor 110 from entering the fully on state in response to a fall in the input voltage VIN makes it possible, even if thereafter the input voltage VIN rises sharply, to raise the gate signal G10 in a way to immediately follow the sharp change. It is thus possible to minimize an overshoot in the output voltage VOUT.
Moreover, with the linear power supply 101 of this embodiment, in accordance with the output current IOUT, the offset voltage Voffset is variably controlled. This helps keep the degree of the lowering of the output voltage VOUT (i.e., the offset voltage Voffset) the smaller the lighter the load (the lower the output current IOUT). It is thus possible to keep an adequate output voltage VOUT.
More specifically, the offset adder 150a feeds the input voltage VIN, after shifting it to the low-potential side by the offset voltage Voffset, to the non-inverting input terminal (+) of the amplifier 132. Moreover, as in the ninth embodiment (
The amplifier 132 generates the gate signal G2 by amplifying the difference between the offset input voltage (=VIN−Voffset), which is fed to the non-inverting input terminal (+) of the amplifier 132, and the output voltage VOUT, which is fed to the inverting input terminal (−) of the amplifier 132.
Accordingly, when the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT falls down to the offset voltage Voffset, through the operation of the amplifier 132, output feedback control is applied such that the offset input voltage (=VIN−Voffset) and the output voltage VOUT are imaginarily short-circuited together. As a result, the gate signal G10 for the output transistor 110 now changes so as to follow the input voltage VIN while keeping a predetermined potential difference with respect to the input voltage VIN. That is, the gate signal G10 is no longer pegged at low level, and thus the output transistor 110 does not enter the fully on state.
In this way, the offset voltage Voffset may, instead of being added to the output voltage VOUT, be subtracted from the input voltage VIN.
The voltage divider 120a includes resistors 123 and 124 (with resistance values R3 and R4) connected in series between the application terminal for the input voltage VIN and the grounded terminal, and outputs from the connection node between those resistors a divided input voltage VIN2 (=VIN×[R4/(R3+R4)]) commensurate with the input voltage VIN.
Here, appropriately selecting the resistors 121 to 124 such that R1:R2=R3:R4 provides a configuration equivalent to one where the amplifier 132 is differentially fed with the input voltage VIN and the output voltage VOUT, and it is thus possible to achieve effects similar to those achieved with the ninth embodiment (
The voltage fed to the inverting input terminal (−) of the amplifier 132 is not limited to the feedback voltage VFB but may instead be any voltage that varies in a way to behave like the output voltage VOUT. For example, the output voltage VOUT can be divided in a voltage division ratio different from that in the voltage divider 120 so that the divided output voltage may be fed to the inverting input terminal (−) of the amplifier 132.
Their interconnection is as follows. The respective emitters of the transistors 165 and 166 are connected to the input terminal for the input voltage VIN. The respective collectors of the transistors 165 and 166 are connected to the gate of the output transistor 110. The respective bases of the transistors 165 and 166 are connected to the output terminals of the amplifiers 131 and 132 respectively.
In this way, the PMOSFETs 161 and 162 may be replaced with pnp-type bipolar transistors 165 and 166. In this configuration, the gate signals G1 and G2 can be understood as base signals.
As shown in parentheses in
Their interconnections are as follows. The first terminal of the current source 169 is connected to the input terminal for the input voltage VIN. The second terminal of the current source 169 and the drain of the NMOSFET 168 are connected to the gate of the output transistor 110. The source of the NMOSFET 168 is connected to the drain of the NMOSFET 167. The source of the NMOSFET 167 is connected to the grounded terminal. The respective gates of the NMOSFETs 167 and 168 are connected to the output terminals of the amplifiers 131 and 132 respectively.
When the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT is higher than the offset voltage Voffset, the NMOSFET 168 is in the fully on state, and the amplifier 131 performs ordinary output feedback control. On the other hand, when the differential voltage (=VIN−VOUT) between the input voltage VIN and the output voltage VOUT falls down to the offset voltage Voffset, the amplifier 131 is in the fully on state, and thus the amplifier 132 performs output feedback control. That is, output feedback control is applied such that the input voltage VIN and the offset output voltage (=VOUT+Voffset) are imaginarily short-circuited together.
In this way, in the gate driver 160, instead of the source current that is fed to the gate of the output transistor 110 (i.e., a current for turning off the output transistor 110), the sink current that is drawn from the gate of the output transistor 110 (i.e., a current for turning on the output transistor 110) may be controlled.
In that case, as shown in
As shown in a balloon in
The source of the PMOSFET 172 is connected to the drain of the PMOSFET 171. The source of the PMOSFET 173 is connected to the drain of the output transistor 110 (i.e., the application terminal for the output voltage VOUT). The respective gates of the PMOSFETs 172 and 173 are both connected to the drain of the PMOSFET 173. The drain of the PMOSFET 173 is connected to the first terminal of the current source 174. The second terminal of the current source 174 is connected to the grounded terminal.
In this way, by making equal the output node voltages (i.e., drain voltages) of the PMOSFET 171 and the output transistor 110, it is possible to make equal the drain-source voltage of the PMOSFET 171 and the drain-source voltage of the output transistor 110. It is thus possible to accurately generate a sense current I71 commensurate with the output current IOUT (hence the control signal for the offset adder 150).
While the sense current I71 may be output as the control signal for the offset adder 150,
Their interconnections are as follows. The drain of the NMOSFET 176 is connected to the drain of the PMOSFET 171 (i.e., an output terminal for the sense current I71). The respective gates of the NMOSFETs 175 and 176 are connected to the drain of the NMOSFET 176. The respective sources of the NMOSFETs 175 and 176 are connected to the grounded terminal. The drain of the NMOSFET 175 is, as an output terminal for the control current I75, connected the offset adder 150.
In this way, as the control signal for the offset adder 150, a control current I75 (i.e., a mirror current) commensurate with the sense current I71 may be used.
Their interconnections are as follows. The non-inverting input terminal (+) of the amplifier 178 and the first terminal of the resistor 179 are connected to the drain of the PMOSFET 171. The inverting input terminal (−) of the amplifier 178 and the first terminal of the resistor 17A are connected to the source of the NMOSFET 177. The respective second terminals of the resistors 179 and 17A are connected to the grounded terminal. The output terminal of the amplifier 178 is connected to the gate of the NMOSFET 177. The drain of the NMOSFET 177 is, as an output terminal for a control current I77, connected to the offset adder 150.
The amplifier 178 controls the gate of the NMOSFET 177 such that the non-inverting input terminal (+) and the inverting input terminal (−) of the amplifier 178 are imaginarily short-circuited together. Accordingly the control current I77 has a value (=(Rx/Ry)×171) in accordance with the current value of the sense current I71 and the resistance values Rx and Ry of the resistors 179 and 17A respectively.
In this way, the means for generating a control signal (control current) commensurate with the sense current I71 is not limited to a current mirror.
With the linear power supply 101 of this embodiment, by, for example, varying the resistance value of at least one of the resistors 179 and 17A, it is possible to freely adjust the variable gain for the offset voltage Voffset.
The ninth to fifteenth embodiments that have been described above can be implemented in any combination unless inconsistent. For example, in the twelfth, thirteenth, fourteenth, or fifteenth embodiments (
To follow is an overview of the various embodiments disclosed herein.
According to one aspect of what is disclosed herein, a linear power supply includes:
an output transistor configured to be connected between an input terminal for an input voltage and an output terminal for an output voltage; a driver configured to drive the output transistor such that a feedback voltage commensurate with the output voltage remains equal to a reference voltage; a current detector configured to sense an output current passing through the output transistor; and a voltage adjuster configured to adjust the reference voltage or the feedback voltage such that the differential voltage between a first voltage commensurate with the input voltage and a second voltage commensurate with the output voltage or the reference voltage does not fall below an offset voltage commensurate with the output current. (A first configuration.) The first voltage may be the input voltage itself, or a division voltage of the input voltage. The second voltage may be the output voltage itself, or a division voltage of the output voltage (i.e., the feedback voltage), or the reference voltage itself, or a division voltage of the reference voltage.
In the linear power supply of the first configuration described above, when the output current is represented by IOUT, the on-state resistance of the output transistor in the fully on state is represented by RON, and the offset voltage is represented by Voffset, the offset voltage may be variably controlled such that IOUT×RON<Voffset holds over the entire load range. (A second configuration.)
In the linear power supply of the first or second configuration described above, the offset voltage may be set at a voltage value lower than the minimum input-output voltage difference defined for the linear power supply. (A third configuration.)
In the linear power supply of any of the first to third configurations described above, the voltage adjuster may be configured to keep the reference voltage at a steady-state value when the differential voltage is higher than the offset voltage and to lower the reference voltage from the steady-state value when the differential voltage falls down to the offset voltage, thereby to prevent the differential voltage from falling further. (A fourth configuration.)
In the linear power supply of any of the first to third configurations described above, the voltage adjuster may configured to deliver the feedback voltage as it is to the driver when the differential voltage is higher than the offset voltage and to deliver the feedback voltage after raising it to the driver when the differential voltage falls down to the offset voltage, thereby to prevent the differential voltage from falling further. (A fifth configuration.)
In the linear power supply of any of the first to fifth configurations described above, the voltage adjuster may include: an offset adder configured to offset the second voltage by shifting it to the high-potential side by the offset voltage; a differential amplifier configured to be differentially fed with the first voltage and the offset second voltage; and a variable voltage source configured to adjust the reference voltage or the feedback voltage based on the output signal of the differential amplifier. (A sixth configuration.)
In the linear power supply of any of the first to fifth configurations described above, the voltage adjuster may include: an offset adder configured to offset the first voltage by shifting it to the low-potential side by the offset voltage; a differential amplifier configured to be differentially fed with the second voltage and the offset first voltage; and a variable voltage source configured to adjust the reference voltage or the feedback voltage based on the output signal of the differential amplifier. (A seventh configuration.)
In the linear power supply of the sixth or seventh configuration described above, the variable voltage source may include a transistor of which the conductivity is controlled based on the output signal of the differential amplifier, and may be configured to adjust the reference voltage or the feedback voltage in accordance with the current passing through the transistor. (An eighth configuration.)
The linear power supply of any of the first to eighth configurations described above may further include: a first resistor and a second resistor that are configured to be connected in series between an application terminal for the output voltage and a grounded terminal and that are configured to output the feedback voltage from the connection node between the first and second resistors; and a third resistor and a fourth resistor that are configured to be connected in series between an application terminal for the input voltage and the grounded terminal and that are configured to output the first voltage from the connection node between the third and fourth resistors. Here, when the resistance value of the first resistor is represented by R1, the resistance value of the second resistor is represented by R2, the resistance value of the third resistor is represented by R3, and the resistance value of the fourth resistor is represented by R4, R1:R2=R3:R4 may hold. (A ninth configuration.)
The linear power supply of the seventh configuration described above may further include: a first resistor and a second resistor that are configured to be connected in series between an application terminal for the output voltage and a grounded terminal and that are configured to output the feedback voltage from the connection node between the first and second resistors; a third resistor and a fourth resistor that are configured to be connected in series between an application terminal for the input voltage and the grounded terminal and that are configured to output the first voltage from the connection node between the third and fourth resistors; and a fifth resistor connected between the application terminal for the input voltage and the first resistor. Here, when the resistance value of the first resistor is represented by R1, the resistance value of the second resistor is represented by R2, the resistance value of the third resistor is represented by R3, and the resistance value of the fourth resistor is represented by R4, R1:R2=R3:R4 may holds. Moreover, the current detector may be configured to draw a current commensurate with the output current from an output terminal for the first voltage toward the grounded terminal. (A tenth configuration.)
According to one aspect of what is disclosed herein, a linear power supply includes: an output transistor configured to be connected between an input terminal for an input voltage and an output terminal for an output voltage; a first amplifier configured to generate a first driving signal by amplifying the difference between the output voltage or a voltage commensurate with it and a predetermined reference voltage; a second amplifier configured to generate a second driving signal by amplifying the difference between the input voltage or a voltage commensurate with it and the output voltage or a voltage commensurate with it; a driver configured to drive the output transistor in accordance with the first and second driving signal; a current detector configured to generate a control signal by sensing an output current passing through the output transistor; and an offset adder configured to feed the second amplifier with an offset voltage commensurate with the control signal. (An eleventh configuration.)
In the linear power supply of the eleventh configuration described above, when the output current is represented by IOUT, the on-state resistance of the output transistor in the fully on state is represented by RON, and the offset voltage is represented by Voffset, the offset voltage may be variably controlled such that IOUT×RON<Voffset holds over the entire load range. (A twelfth configuration.)
In the linear power supply of the eleventh or twelfth configuration described above, the offset voltage may be set at a voltage value lower than the minimum input-output voltage difference defined for the linear power supply. (A thirteenth configuration.)
In the linear power supply of any of the eleventh to thirteenth configurations described above, the offset adder may configured to feed the output voltage or a voltage commensurate with it, after shifting it, to the high-potential side by the offset voltage, to the second amplifier. (A fourteenth configuration.)
In the linear power supply of any of the eleventh to thirteenth configurations described above, the offset adder maybe configured to feed the input voltage or a voltage commensurate with it, after shifting it, to the low-potential side by the offset voltage, to the second amplifier. (A fifteenth configuration.)
The linear power supply of any of the eleventh to fifteenth configurations described above may further include: a first resistor and a second resistor that are configured to be connected in series between the output terminal for the output voltage and a grounded terminal and that are configured to output a divided output voltage from the connection node between the first and second resistors to the second amplifier; and a third resistor and a fourth resistor that are configured to be connected in series between the input terminal for the input voltage and the grounded terminal and that are configured to output a divided output voltage from the connection node between the third and fourth resistors to the second amplifier. Here, when the resistance values of the first to fourth resistors are represented by R1, R2, R3, and R4 respectively, R1:R2=R3:R4 may hold. (A sixteenth configuration.)
In the linear power supply of any of the eleventh to sixteenth configurations described above, the driver may include a first transistor and a second transistor that are connected in parallel between the input terminal for the input voltage and the control terminal of the output transistor and that are controlled by the first and second driving signal respectively. (A seventeenth configuration.)
In the linear power supply of any of the eleventh to sixteenth configurations described above, the driver may include a first transistor and a second transistor that are connected in parallel between the control terminal of the output transistor and a grounded terminal and that are controlled by the first and second driving signal respectively. (A eighteenth configuration.)
In the linear power supply of any of the eleventh to eighteenth configurations described above, the current detector may include a sense transistor configured to generate a sense current commensurate with the output current, and may be configured to feed, as the control signal, the sense current or a current signal commensurate with it to the offset adder. (A nineteenth configuration.)
In the linear power supply of the nineteenth configuration described above, the current detector may further include a biasing means for making equal the output node voltages of the sense transistor and the output terminal. (A twentieth configuration.)
The electronic appliance X11 is an engine control unit which performs control with respect to an engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, automatic cruise control, etc.).
The electronic appliance X12 is a lamp control unit which controls the lighting and extinguishing of HIDs (high-intensity discharged lamps) and DRLs (daytime running lamps).
The electronic appliance X13 is a transmission control unit which performs control with respect to a transmission.
The electronic appliance X14 is a behavior control unit which performs control with respect to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS (electric power steering) control, electronic suspension control, etc.).
The electronic appliance X15 is a security control unit which drives and controls door locks, burglar alarms, and the like.
The electronic appliance X16 comprises electronic appliances incorporated in the vehicle X as standard or manufacturer-fitted equipment at the stage of factory shipment, such as wipers, power side mirrors, power windows, dampers (shock absorbers), a power sun roof, and power seats.
The electronic appliance X17 comprises electronic appliances fitted to the vehicle X optionally as user-fitted equipment, such as A/V [audio/visual] equipment, a car navigation system, and an ETC [electronic toll control system].
The electronic appliance X18 comprises electronic appliances provided with high-withstand-voltage motors, such as a vehicle-mounted blower, an oil pump, a water pump, and a battery cooling fan.
Any of the linear power supply circuits 1 and 101 described previously can be incorporated in any of the electronic appliances X11 to X18.
The various technical features disclosed herein may be implemented in any other manners than in the embodiments described above, and allow for any modifications made within the spirit of their technical ingenuity. That is, the embodiments described above should be considered to be in every aspect illustrative and not restrictive, and the technical scope of the present invention should be understood to be defined not by the description of the embodiments described above but by the appended claims and to encompass any modifications made in a sense and scope equivalent to the claims.
The invention disclosed herein finds applications in vehicle-related appliances, marine vessel-related appliances, office appliances, portable appliances, smartphones, and the like.
1 linear power supply
2 load
10 output transistor (PMOSFET)
20, 20a voltage divider
21, 22, 23, 24, 25 resistor
30 driver
40 reference voltage adjuster
41, 41a offset adder
42 differential amplifier
43 variable voltage source
43
a NMOSFET
43
b, 43c resistor
43
d PMOSFET
50 current detector
51 PMOSFET
52, 53 PMOSFET
54 current source
55, 56 NMOSFET
60 constant voltage source
70 feedback voltage adjuster
71
71
a offset adder
72 differential amplifier
73 variable voltage source
73
a PMOSFET
101 linear power supply
102 load
110 output transistor (PMOSFET)
120, 120a voltage divider
121, 122, 123, 124 resistor
130, 131, 132 amplifier
140 reference voltage generator
150, 150a offset adder
160 gate driver
161, 162 PMOSFET
163 current source
164 resistor
165, 166 pnp-type bipolar transistor
167, 168 NMOSFET
169 current source
170 current detector
171, 172, 173 PMOSFET
174 current source
175, 176, 177 NMOSFET
178 amplifier
179, 17A resistor
X vehicle
X11-X18 electronic appliance
| Number | Date | Country | Kind |
|---|---|---|---|
| JP2018-228336 | Dec 2018 | JP | national |
| JP2019-057059 | Mar 2019 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2019/045817 | 11/22/2019 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2020/116208 | 6/11/2020 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20110248688 | Iacob | Oct 2011 | A1 |
| 20120013317 | Morino | Jan 2012 | A1 |
| 20160299518 | Iwata et al. | Oct 2016 | A1 |
| 20180307259 | Ogura | Oct 2018 | A1 |
| 20190050011 | Fujimoto | Feb 2019 | A1 |
| 20190079552 | Yasusaka | Mar 2019 | A1 |
| 20190360448 | Kita | Nov 2019 | A1 |
| Number | Date | Country |
|---|---|---|
| 2004-062625 | Feb 2004 | JP |
| 2012-022450 | Feb 2012 | JP |
| 2016-200989 | Dec 2016 | JP |
| 2018-112963 | Jul 2018 | JP |
| Entry |
|---|
| PCT International Search Report in International Appln. No. PCT/JP2019/045817, dated Dec. 17, 2019. 2 pages (with English Translation). |
| Number | Date | Country | |
|---|---|---|---|
| 20220011796 A1 | Jan 2022 | US |
