Patent Application
20070241730
The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the semiconductor industry utilized various methods and structures for forming linear voltage regulator circuits. One particular implementation of a linear voltage regulator circuit was referred to as a low drop-out (LDO) regulator. Such LDO regulators generally dropped a very small voltage across the regulator and provided a well regulated voltage to a load that was external to the LDO regulator. Under most conditions, the amount of current required by the load varied during the operation of the load. These variations affected the frequency stability of the system. As the load current varied, the impedance provided by the load also varied. These load impedance variations often caused unstable operation of the closed loop system formed by the LDO regulator and the load.
Accordingly, it is desirable have a method of forming a regulator with an internal compensation that improves the stability provided by the regulator.
For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-Channel devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action.
Error amplifier 23 receives a reference signal from a reference input 21 of regulator 20 and also receives the voltage sense signal from node 31. Amplifier 23 forms an error signal on an output of amplifier 23 that represents the deviation of the sense signal from the reference signal. Buffer 33 receives the error signal and forms a drive signal that controls transistor 24 to provide current 25. In the preferred embodiment, buffer 33 is formed as a differential amplifier 34 having a gain that is selected by the value of gain resistors 35 and 36. The gain of buffer 33 generally is greater than one in order to drive transistor 24 and preferably is about five. A portion of current 25 from transistor 24 flows through network 28 as current 18 to provide the voltage sense signal and the remainder flows through output 22 as a load current 17. Since the amount of current flowing through network 28 is very small relative to the value of current 17, the value of current 25 flowing through transistor 24 is substantially equal to the value of current 17, thus, the value of sense current 26 is substantially proportional to the value of load current 17.
The various capacitances and resistances of regulator 20 and system 10 form poles and zeroes that affect the stability of regulator 20 and system 10. Transistor 24 has a large gate-to-source parasitic capacitance that forms a parasitic pole of regulator 20. Buffer 33 usually has a high input impedance and a low output impedance that isolates the parasitic capacitance of transistor 24 from the output impedance of amplifier 23. The low output impedance of buffer 33 places the parasitic pole at a high-frequency that is outside the active frequency range of system 10. Compensation capacitor 44 forms a dominant pole of regulator 20 and system 10. The frequency of the dominant pole of capacitor 44 is controlled by the output resistance of amplifier 23 times the effective value of capacitor 44. Because capacitor 44 is connected in parallel with buffer 33 and transistor 24 in a miller configuration, the effective capacitance of capacitor 44 is the physical value of capacitor 44 times the gain provided by buffer 33 and transistor 24. The miller configuration makes the effective value of capacitor 44 large thereby placing the dominant pole at a low frequency. A load pole is formed by the capacitance of load 11 illustrated by capacitance 12. The frequency of the load pole is determined by capacitance 12 and the load resistance illustrated by resistor 13. Since the value of load current 17 varies during the operation of load 11, the effective value of resistor 13 also varies with the variations in current 17. Thus, the frequency of the load pole also varies with variations in current 17. As will be seen further hereinafter, circuit 40 is connected in a miller configuration in parallel with buffer 33 and transistor 24 so that the variable resistance of transistor 45 is connected in series with capacitor 44 and the series combination thereof is connected in parallel with the gains of buffer 33 and transistor 24.
In order to assist and providing this functionality, amplifiers 23, 34, and 47 are connected to receive power between input 15 and return 16. An inverting input of amplifier 23 is connected to input 21 and a non-inverting input of amplifier 23 is connected to node 31. The output of amplifier 23 is commonly connected to a non-inverting input of amplifier 34, a non-inverting input of amplifier 47, and a source of transistor 45. An inverting input of amplifier 34 is commonly connected to a first terminal of resistor 35 and a first terminal of resistor 36. A second terminal of resistor 36 is connected to return 16. A second terminal of resistor 35 is commonly connected to an output of amplifier 34 and a gate of transistor 24. A source of transistor 24 is connected to input 15. The drain of transistor 24 is connected to output 22 and to a first terminal of capacitor 44. The sense drain of transistor 24 is commonly connected to a gate and a drain of transistor 48 and to a gate of transistor 45. The source of transistor 48 is commonly connected to an output and an inverting input of amplifier 47. A drain of transistor 45 is connected to a second terminal of capacitor 44. A first terminal of resistor 29 is connected to output 22 and a second terminal is commonly connected to node 31 and a first terminal of resistor 30. A second terminal of resistor 30 is connected to return 16.
In view of all of the above, it is evident that a novel device and method is disclosed. Included, among other features, is forming linear regulator having a variable miller compensation circuit that is in series with an output amplifier of the regulator, such as amplifier 34. Configuring the variable miller compensation circuit in parallel with the output amplifier increases the effective capacitance thereby placing the resulting pole at a very low frequency that has very little variation. Configuring the variable miller circuit to include a resistance that varies proportionally to a load current forms the resulting zero with a frequency that varies with the load current. Varying the frequency with the load current keeps the zero close to the load pole and improves the stability of the system that uses the linear regulator.
While the subject matter of the invention is described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, although regulator 20 is illustrated as a stand-alone circuit, it will be appreciated by those skilled in the art that regulator 20 may be formed on a semiconductor die as one portion of an integrated circuits having various other components that may also be formed on the semiconductor die. Additionally, the control elements of the variable miller compensation circuit, such as amplifier 47 and transistor 48, can be implemented by other circuit elements that are coupled to vary the resistance of transistor 45 as long as the variable resistance and the capacitance are coupled in a miller configuration. Also, the subject matter of the invention has been described for particular P-channel transistors, the method is directly applicable to other MOS transistors, as well as to BiCMOS, metal semiconductor FETs (MESFETs), HFETs, and other transistor structures. Additionally, the word “connected” is used throughout for clarity of the description, however, it is intended to have the same meaning as the word “coupled”. Accordingly, “connected” should be interpreted as including either a direct connection or an indirect connection.
