Linear regulator circuit

Abstract

A linear regulator circuit for suppressing power supply noise that propagates to an output voltage. An LDO circuit functioning as the linear regulator circuit is provided with an output transistor including a source for receiving input voltage, a drain for outputting the output voltage, and a control terminal. An error amplifier powered by the input voltage generates a control voltage for controlling the output transistor based on a potential difference between a feedback voltage, which corresponds to the output voltage, and a reference voltage. A first capacitor and a resistor are connected in series between the source of the output transistor and an output terminal of the error amplifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:

FIG. 1 is a schematic circuit diagram of an LDO circuit in the prior art;

FIG. 2 is a schematic circuit diagram of the error amplifier shown in FIG. 1;

FIG. 3 is a schematic circuit diagram of another LDO circuit in the prior art;

FIG. 4 is a schematic circuit diagram of the error amplifier and the reverse phase amplifier of FIG. 3;

FIG. 5 is a schematic circuit diagram of an LDO circuit according to a first embodiment of the present invention;

FIG. 6 is a schematic circuit diagram of the error amplifier and the buffer circuit shown in FIG. 5;

FIG. 7 is a schematic circuit diagram of a simulation circuit for analyzing the operation of the LDO circuit shown in FIGS. 5 and 6;

FIG. 8 is a graph showing the PSRR characteristic and the gain of the LDO circuit shown in FIG. 5, the graph showing the results when simulating the operation of the LDO circuit with the simulation circuit of FIG. 7;

FIG. 9 is a graph showing a phase margin of the LDO circuit of FIG. 5, the graph showing the results when simulating the operation of the LDO circuit with the simulation circuit of FIG. 7;

FIG. 10 is a schematic circuit diagram of an LDO circuit according to a second embodiment of the present invention; and

FIG. 11 is a schematic circuit diagram of the error amplifier shown in FIG. 10.

Claims

1. A linear regulator circuit for generating an output voltage from an input voltage, the linear regulator circuit comprising: an output transistor including a first terminal for receiving the input voltage, a second terminal for outputting the output voltage, and a control terminal;an error amplifier powered by the input voltage and including a first input terminal for receiving the output voltage, a second terminal for receiving a reference voltage, and an output terminal, wherein the error amplifier generates a control voltage for controlling the output transistor based on a voltage difference between the output voltage and the reference voltage and supplies the control voltage to the output terminal; anda first capacitor and a resistor connected in series between the first terminal of the output transistor and the output terminal of the error amplifier.

2. The linear regulator circuit according to claim 1, further comprising: a buffer circuit, connected between the output terminal of the error amplifier and the control terminal of the output transistor, for receiving the control voltage from the error amplifier and supplying the control voltage to the control terminal of the output transistor.

3. The linear regulator circuit according to claim 1, wherein the error amplifier directly supplies the control voltage to the control terminal of the output transistor.

4. The linear regulator circuit according to claim 1, wherein the first capacitor is directly connected to the first terminal of the output transistor.

5. The linear regulator circuit according to claim 1, further comprising: a second capacitor connected to the second terminal of the output transistor, wherein the output transistor has a predetermined conductance, and a frequency band set by the first capacitor and the resistor is higher than a frequency band set by the conductance of the output transistor and the second capacitor.

6. The linear regulator circuit according to claim 1, wherein the output transistor is configured by an MOS transistor, and the MOS transistor includes a source functioning as the first terminal, a drain functioning as the second terminal, and a gate functioning as the control terminal.

7. The linear regulator circuit according to claim 1, further comprising: a third capacitor, connected between the error amplifier and the second terminal of the output transistor, for suppressing fluctuation in the output voltage.

8. The linear regulator circuit according to claim 7, wherein the value of the resistor is determined based on the first capacitor and the third capacitor.