Linear regulator enhancement technique

Abstract

A linear regulator circuit to regulate an output voltage includes a first current path to conduct a first current, a feedback path to provide feedback to maintain the output voltage at a constant voltage, and a transistor positioned in the first current path to provide the output voltage.

Description

FIELD OF THE INVENTION

The present invention relates to a voltage regulator such as a linear voltage regulator and the associated circuitry.

BACKGROUND OF THE INVENTION

A DC-to-DC voltage regulators typically are used to convert a DC input voltage to either a high or a low DC output voltage. One type of voltage regulator, called a linear regulator, is often chosen due to its simple design.

Referring to FIG. 1 , a linear regulator may use a transistor 106 to conduct current from an input voltage source 116 (providing a voltage called unfiltered supply voltage) to a load 102 that is coupled to an output terminal 120 of the regulator 100 . To regulate an output voltage (called V OUT ), the regulator 100 may include an error amplifier 114 that amplifies the difference between a reference voltage obtained from reference voltage source 116 and a signal (called V F ) that is proportional to the output voltage. Due to negative feedback, an error voltage that is formed by the amplifier 114 functions to control the transistor 106 in such a manner as to keep the V OUT voltage within prescribed limits. The reference voltage V REF may be provided by, for example, a low power voltage reference circuit 116 . Other features of regulator 100 may include an RC filter formed by resistor 110 and capacitor 112 . This low-pass filter filters high-frequency noise through capacitor 112 .

When the regulator 100 powers up, the voltages and currents of regulator 100 fluctuate until the voltages and currents reach steady state, or quiescent, bias levels. Unfortunately, these fluctuations may produce power surges that cause the V IN and V OUT voltages to vary outside of specified tolerances. For example, the V IN and V OUT voltages may be supplied by voltage rails of a computer system power supply and may not be able to vary beyond a predetermined percentage (for example, five percent) of the predetermined voltage level, which may be five volts.

To minimize the effects that regulator 100 imposes on the input voltage source during power-up, a limitation may be placed on the slew rate of the regulator 100 . In particular, the slew rate is the maximum rate at which the regulator 100 can change the V OUT voltage. By limiting the slew rate, voltage and current fluctuations in the V OUT voltage are dampened when the regulator 100 powers up. Unfortunately, designs that limit the slew rate for purposes of regulating the power-up state of the regulator 100 may cause the regulator 100 to respond poorly to transient load conditions during normal operation of the regulator 100 . Thus, there is a continuing need for a regulator having a sufficient slew rate to accommodate the state of the regulator. Additionally, it is necessary to improve the existing power supply rejection ratio (PSRR) without adding undue complexity to the design of the linear regulator.

As illustrated in FIG. 1 , the unfiltered supply voltage is typically at 3.3 volts, and the load circuit 102 requires voltages ranging from 1.1 volts to 1.8 volts. There are many topologies for linear regulators. In FIG. 1 , the buffer feedback circuit comes directly from the operational amplifier. Feedback might be taken from the source or emitter of a MOS transistor or a bipolar junction transistor (BJT), as the case may be. The reference circuit 116 could employ an auto-calibration loop; however, the reference voltage might be supplied from a band gap voltage reference circuit. There are many mechanisms that can cause degradation in the PSRR. One of these is the output impedance of transistor 106 . As the unfiltered supply voltage modulates, part of that modulation will transfer from the drain of transistor 106 to the source of the transistor 106 . Additionally, higher frequencies result in increased PSRR. This results from the capacitive parasitic paths found in transistor 106 . Thus, with high-frequency modulation from the unfiltered supply voltage, capacitive coupling can occur from the drain-gate capacitance of transistor 106 , and this high-frequency modulation can be coupled to the load through the gate-source capacitance of transistor 106 .

SUMMARY OF THE INVENTION

The present invention significantly improves the PSRR. More particularly, the present invention improves the PSRR due to voltage modulation that is transferred from the drain of a transistor to the source of the transistor where that transistor is used to connect the voltage supply to the load. Additionally, the present invention improves PSRR due to high-frequency modulation of the unfiltered supply voltage that is coupled through the drain-to-gate capacitance of the transistor used to couple the voltage to the load. This high-frequency modulation is then coupled to the load.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a linear regulator;

FIG. 2 illustrates a linear regulator of the present invention;

FIG. 3 illustrates another embodiment of a linear regulator in accordance with the invention;

FIG. 4 illustrates yet another linear regulator in accordance with the present invention; and

FIG. 5 illustrates simulation results.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The circuit 210 , as illustrated in FIG. 2 , of the present invention is transferable to any linear regulator where the load operates at a voltage lower than the raw supply voltage by some level or margin that allows for the voltage drop of the pass device, such as transistor 106 in the present embodiment. The circuit 210 includes resistor 202 , resistor 204 , capacitor 208 , and transistor 206 . The present invention adds an additional current path between the supply voltage and ground. This is illustrated by the current path of current I 2 . The resistor 202 is connected between the supply voltage and the drain of NFET 106 . Additionally, NFET 206 at its source is connected to one end of resistor 202 and to the drain of NFET 106 . The source of NFET 206 is connected to ground. The gate of NFET 206 is connected to resistor 204 and to capacitor 208 . The other end of resistor 204 is connected to the source of transistor 106 as well as the output terminal. The gate of transistor 206 is connected to a relatively fixed voltage potential. Alternatively, the gate of transistor 206 could be connected to ground. As the drain of transistor 106 raises in voltage, the current through transistor 206 is increased. The present invention includes two current sources. The first current path is through the drain-to-source of transistor 106 while the second current path is through the source-to-drain of transistor 206 . The current through the first current path is represented by I 1 , and the current through the second current path is I 2 . Thus, as the drain of transistor 106 increases in voltage, the current I 2 in the second current path through transistor 206 increases. Since the current I 2 of the second current path through transistor 206 has increased, the voltage across resistor 202 increases and, consequently, the voltage at the drain of transistor 106 reduces. This reduces the current. The connection from the source of transistor 106 to the gate of transistor 206 introduces a high-frequency path which, unfiltered, would result in unstable operation of transistor 206 . Consequently, a low-pass filter of resistor 204 and capacitor 208 has been added between the source of transistor 106 and the gate of transistor 206 , more particularly, a resistor 204 and capacitor 208 . As a consequence, any high-frequency modulating at the source of NFET 106 is shunted through resistor 204 and through capacitor 208 to ground.

Equation 1 is a derivation of the small signal model of FIG. 2 in order to study PSRR. $$ V5out = ( Ro2 * Rload ) * V ⁢ sup ⁢   ⁢ ply + ( Ro1 * Rload * ( Ro2 + Rs + gm2 * Rs * Ro2 ) ) * Vgate1 ( Ro1 * Rload * ( Ro2 + Rs + gm2 * Rs * Ro2 ) * ( gm1 + 1 Rload + 1 Ro1 ) ) + ⁢ Ro2 * Rs - gm2 * Rs * Rload * Ro2

For purposes of this analysis, the gate of transistor 106 is assumed to be coupled to an ideal voltage source. This assumption decouples the nonideal effects of the operational amplifier.

Table 1 illustrates the values used to determine V OUT , the voltage of the load.

	Gm1	=	0.0158
	Ro1	=	10500.0
	Gm2	=	0.0111
	Ro2	=	7000.0
	Rload	=	1500.0
	Rs	=	250.0

V OUT is the voltage of the load; Ro1 is the output impedance of transistor 106 with the transistor 106 having a transconductance equal to Gm1. Ro2 is the output impedance of transistor 206 with the transconductance of transistor 206 being Gm2. Rload is an approximation of the load, and Vsup ply is the unregulated supply voltage. Substituting these values into the equation, it can be seen that the voltage pertubations as seen by the load should be down by a factor of 0.00151, which is approximately −56 dB PSRR at DC.

Equation 2 illustrates V OUT using the same values for Rload, Gm1 and Ro1. $$ Vout = Rload * V ⁢ sup ⁢   ⁢ ply gm1 * Rload * Ro1 + Ro1 + Rload

From this equation, the value of PSRR is 0.00575 (−44.8 dB). Therefore, one can see a significant improvement on the order of approximately 11 dB.

FIG. 3 illustrates results of the present invention. Here, the resistance of resistor 202 is set at 250 ohms. The value of resistor 204 is 100 kilo ohms. Capacitor 208 is 1 PF. Resistor 110 is set at 100 kilo ohms with capacitor 112 set at 10 PF. Additionally, the linear regulator includes two additional current paths, namely a third current path, illustrated by I 3 , and a fourth current path, illulstrated by I 4 . The third current path has current I 3 flowing through it while the fourth current path has current I 4 flowing through it. A current generator 304 provides a constant current, for example 50 microamps, through the third current path. The current mirror 302 mirrors this current through to the fourth current path. Thus, I 4 is 50 microamps. The resistor 306 is set at 20K.

Turning now to FIG. 4 , this figure illustrates a similar circuit, again with a third current path and a fourth current path, again represented by current I 3 and I 4 , respectively. A comparator 404 compares the voltage between the third and fourth current paths, and an output from the comparator 404 is connected to the gate of transistor 406 .

FIG. 5 illustrates the results curve 502 illustrates the PSRR without the advantages of the circuits of the present invention. Curve 504 illustrates an approximately 12 dB gain in the center of the curve with respect to curve 502 . However, this circuit of curve 504 fails to include resistor 204 and resistor 208 and has a direct connection between the source of transistor 106 and the gate of transistor 206 . Thus, at higher frequencies, the response degrades as a result of the modulating noise affecting the operation of transistor 206 . Curve 506 illustrates the effect of the circuit of the present invention with resistor 204 and capacitor 208 employed. As expected, the degradation of the curve at higher frequencies does not occur since the high-frequency modulation of the voltage at the gate of transistor 206 does not occur. A bipolar transistor could be substituted for transistor 206 .

Claims

1. A linear regulator circuit to regulate an output voltage, comprising:a first current path to conduct a first current comprising a first transistor connected to a source voltage through a first resistor and to the output voltage; a second current path to provide feedback to maintain said output voltage at a constant voltage, wherein said second current path includes a second transistor with a first terminal connected to the first transistor and the first resistor, a second terminal connected to a reference voltage, and a gate/base connected to the output voltage through a second resistor.

2. A linear regulator circuit as in claim 1, wherein said first transistor is a FET.

3. A linear regulator circuit as in claim 1, wherein said first transistor is a NFET.

4. A linear regulator circuit as in claim 1, wherein said first transistor is bipolar.

5. A linear regulator circuit as in claim 1, wherein said second transistor is a FET.

6. A linear regulator circuit as in claim 1, wherein said second transistor is bipolar.