Patent Application
20240152168
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-179450, filed on Nov. 9, 2022, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a linear regulator.
A linear regulator, which generates an output voltage from an input voltage, is provided with an output transistor between an input terminal, which receives the input voltage, and an output terminal, which applies the output voltage, and performs feedback control to control a gate voltage of the output transistor based on a feedback voltage corresponding to the output voltage. It is possible to stabilize the output voltage at a desired target voltage by the feedback control.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure.
Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments.
Examples of embodiments of the present disclosure will be specifically described below with reference to the drawings. In each referenced figure, the same parts are designated by like reference numerals, and the overlapping explanation regarding the same parts will be omitted in principle. In this specification, for the purpose of simplifying the description, by indicating symbols or reference numerals that refer to information, signals, physical quantities, functional parts, circuits, elements, components, and the like, the names of information, signals, physical quantities, functional parts, circuits, elements, components, and the like corresponding to the symbols or reference numerals may be omitted or abbreviated.
First, some terms used in the description of the embodiments of the present disclosure will be explained. The term “ground” refers to a reference conductive portion having a reference potential of 0 V (zero volts), or refers to the potential of 0 V itself. The reference conductive portion may be formed using a conductor such as metal or the like. The potential of 0 V is sometimes referred to as a ground potential. In the embodiments of the present disclosure, voltages shown without any particular reference represent potentials as seen from the ground. The term “level” refers to the level of a potential. For any signal or voltage of interest, a high level has a higher potential than a low level.
Regarding any transistor configured as a FET (field effect transistor) including a MOSFET, the term “on-state” refers to a state in which the drain and source of the transistor are electrically connected to each other, and the term “off-state” refers to a state in which the drain and source of the transistor are not electrically connected to each other (cutoff state). The same applies to transistors that are not classified as FETs. The MOSFET is regarded as an enhancement type MOSFET unless otherwise specified. MOSFET is an abbreviation for “metal-oxide-semiconductor field-effect transistor.” Further, unless otherwise specified, the back gate of any MOSFET may be considered to be short-circuited to the source.
Hereinafter, the on-state and off-state of any transistor may be simply expressed as on and off. Connections between multiple parts that form a circuit, such as arbitrary circuit elements, wirings, nodes, and the like, may be regarded as electrical connections, unless otherwise specified.
For any two voltages V1 and V2 to be compared, “V1>V2” represents that the voltage V1 is higher than the voltage V2, and “V1<V2” represents that the voltage V1 is lower than the voltage V2. The same applies to other formulae that include physical quantities other than a voltage.
The input voltage Vin may vary depending on a system in which the semiconductor device 900 is installed. In order to stabilize the output voltage Vout at the target voltage Vtg against the variation in the input voltage Vin, it is necessary to control the gate voltage Vg according to the variation in the input voltage Vin. However, if the gate voltage Vg is lowered excessively in response to a decrease in the input voltage Vin, it will take a long time for the gate control circuit 902 to raise the gate voltage Vg by a necessary amount when the input voltage Vin returns. That is, a responsiveness of the output voltage Vout to the variation in the input voltage Vin becomes low.
Taking this into consideration, the gate control circuit 902 controls the gate voltage Vg so as to become equal to or higher than a lower limit voltage (e.g., 2 V) which is higher than 0 V. In other words, the gate control circuit 902 does not lower the gate voltage Vg below the lower limit voltage. This makes it possible to improve the responsiveness of the output voltage Vout to the variation in the input voltage Vin.
However, in a configuration such as the reference configuration in which the decrease in the gate voltage Vg is limited, when the input voltage Vin decreases to the target voltage Vtg or less, the output voltage Vout becomes significantly lower than the target voltage Vtg depending on the output current lout.
Under the condition of “Vin≤Vtg,” even if the output current Tout increases, the gate voltage Vg will not fall below the lower limit voltage (e.g., 2.0 V). Therefore, the output voltage Vout will decrease as the output current Tout increases. However, it is desirable that a differential voltage (Vin−Vout) or (Vin−Vtg) when “Vin≤Vtg” is as small as possible.
A first embodiment of the present disclosure will be described.
The input voltage VIN and the output voltage VOUT are positive DC voltages. The semiconductor device 1 performs feedback control to stabilize the output voltage VOUT at a predetermined target voltage VTG. However, the stabilization of the output voltage VOUT at the target voltage VTG is achieved under the condition that establishes “VIN>VTG.” Basically, the input voltage VIN is higher than the output voltage VOUT and the target voltage VTG. However, due to a decrease in an output of a voltage source which supplies the input voltage VIN to the semiconductor device 1, and the like, the input voltage VIN may sometimes be lower than or equal to the output voltage VOUT and the target voltage VTG. The voltage source, which supplies the input voltage VIN to the semiconductor device 1, may be, for example, a battery mounted on a vehicle such as an automobile or the like. An output voltage of the battery mounted on the vehicle may drop significantly, albeit temporarily.
The input voltage VIN from the voltage source is received by the input terminal IN. The voltage applied to the output terminal OUT is the output voltage VOUT. The ground terminal GND is connected to the ground and has a ground potential. The ground terminal GND is connected to a ground wiring WRGND provided in the semiconductor device 1. Therefore, the ground wiring WRGND has a ground potential. Each circuit and each element in the semiconductor device 1, which are connected to the ground, specifically means that they are connected to the ground wiring WRGND.
An output capacitor COUT and a load LD are provided outside the semiconductor device 1. A first end of the output capacitor COUT is connected to the output terminal OUT, and a second end of the output capacitor COUT is connected to the ground. The load LD is any load which is driven based on the output voltage VOUT, and is provided between the output terminal OUT and the ground. A current, which flows from the output terminal OUT toward the output capacitor COUT and the load LD, is referred to as an output current IOUT.
The semiconductor device 1 is provided with an output transistor M1, a feedback circuit 10, a main amplifier 20, and a driver 30 as main components. A full-on circuit 40 provided as an example of an additional circuit in the semiconductor device 1 will be described later. The output transistor M1 is a P-channel MOSFET. A source of the output transistor M1 is connected to the input terminal IN to receive the input voltage VIN. A drain of the output transistor M1 is connected to the output terminal OUT. A drain current of the output transistor M1 is a current, which flows from the input terminal IN to the output terminal OUT through the channel of the output transistor M1, and corresponds to the above-mentioned output current IOUT.
The feedback circuit 10 is connected to the output terminal OUT. The feedback circuit 10 may be any circuit as long as it generates a feedback voltage VFB according to the output voltage VOUT. However, it is assumed that the feedback voltage VFB has a voltage value proportional to the output voltage VOUT. The output voltage VOUT itself may be the feedback voltage VFB . In the configuration of
The feedback circuit 10 may be provided outside the semiconductor device 1. In this case, a feedback terminal may be provided as an external terminal of the semiconductor device 1, and the connection node between the voltage dividing resistors R1 and R2 may be connected to the feedback terminal. As a result, the feedback voltage VFB is applied to the feedback terminal, so that it is possible to supply the feedback voltage VFB to the circuit that should receive the feedback voltage VFB.
The main amplifier 20 is connected to the ground wiring WRGND, and is driven based on an internal power supply voltage VREG, which will be described later, with the ground potential as a reference. The main amplifier 20 includes an inverting input terminal, a non-inverting input terminal, and an output terminal. In the main amplifier 20, a predetermined reference voltage VREF1 is inputted to the inverting input terminal, and the feedback voltage VFB is inputted to the non-inverting input terminal.
The main amplifier 20 outputs a signal SAMP based on the reference voltage VREF1 and the feedback voltage VFB from its own output terminal when a signal SEN, which will be described later, has a value of “1” and a low voltage abnormality is not detected. In the following description, unless otherwise specified, it is assumed that the signal SEN has a value of “1” and that the low voltage abnormality is not detected. The main amplifier 20 increases the potential of the signal SAMP which establishes “VREF1<VFB,” and lowers the potential of the signal SAMP which “VREF1>VFB.” The signal SAMP is supplied to the driver 30.
The driver 30 is driven based on the input voltage VIN with the ground potential as a reference. The driver 30 controls the gate voltage of the output transistor M1 based on the signal SAMP when a signal STSD, which will be described later, has a value of “0.” In the following, unless otherwise specified, it is assumed that the signal STSD has a value of “0.” The gate voltage of the output transistor M1 is hereinafter indicated by the symbol “VG.” A wiring to which the gate of the output transistor M1 is connected is referred to as a gate wiring WRG. A connection to the gate wiring WRG and a connection to the gate of the output transistor M1 are equivalent to each other.
The driver 30 is connected to the gate wiring WRG. The driver 30 increases the gate voltage VG by outputting charges (positive charges) toward the gate wiring WRG in accordance with the signal SAMP, or lowers the gate voltage VG by pulling out charges (positive charges) from the gate wiring WRG in accordance with the signal SAMP. At this time, the driver 30 operates to lower the gate voltage VG as the potential of the signal SAMP becomes low, and to increase the gate voltage VG as the potential of the signal SAMP becomes high.
The decrease in the gate voltage VG has an effect of increasing the output voltage VOUT through an increase in the drain current of the output transistor M1, and the increase in the gate voltage VG has an effect of decreasing the output voltage VOUT through a decrease in the drain current of the output transistor M1. Therefore, the main amplifier 20 and the driver 30 perform feedback control to stabilize the output voltage VOUT at the target voltage VTG. The feedback control is achieved by controlling the gate voltage VG based on the feedback voltage VFB. A gate control circuit (in other words, a feedback control circuit), which performs the feedback control, is composed of the main amplifier 20 and the driver 30. The feedback control is a control for matching the feedback voltage VFB with the reference voltage VREF1 (in other words, a control for reducing a difference between the feedback voltage VFB and the reference voltage VREF1). The target voltage VTG is determined by the reference voltage VREF1 and the resistance value ratio between the voltage dividing resistors R1 and R2.
When the signal SEN has a value of “0” or when a low voltage abnormality is detected, the operation of the main amplifier 20 is stopped and the potential of the signal SAMP increases to the potential of the input voltage VIN. At this time, the driver 30 maximizes the gate voltage VG (up to the input voltage VIN), thereby ensuring an off-state of the output transistor M1. Furthermore, when the signal STSD has a value of “1,” the driver 30 maximizes the gate voltage VG (up to the input voltage VIN) regardless of the signal SAMP, thereby ensuring the off-state of the output transistor M1.
The semiconductor device 1 further includes an enable state detection circuit 81, an internal power supply circuit 82, a reference voltage generation circuit 83, a low voltage protection circuit 84, an overheating protection circuit 85, and an output discharge circuit 86. All of the circuits 81 to 86 are connected to the ground wiring WRGND and are operated based on the ground potential.
The enable state detection circuit 81 is driven based on the input voltage VIN. The enable state detection circuit 81 is connected to an enable terminal EN to generate and output signals SEN and SENB based on the voltage applied to the enable terminal EN. The signals SEN and SENB are binary signals each having a value of “0” or “1.” When the signal SEN has a value of “1,” the signal SENB has a value of “0,” and when the signal SEN has a value of “0,” the signal SENB has a value of “1.” A current can flow through the output transistor M1 only when the signal SEN has a value of “1.”
The internal power supply circuit 82 generates an internal power supply voltage VREG having a predetermined positive DC voltage value based on the input voltage VIN.
When the signal SEN has a value of “1,” the reference voltage generation circuit 83 generates the reference voltage VREF1 based on the internal power supply voltage VREG, and further generates the reference voltage VREF2 based on the reference voltage VREF1. The reference voltage VREF1 is supplied to the main amplifier 20. The reference voltage VREF2 is supplied to the full-on circuit 40. Each of the reference voltages VREF1 and VREF2 has a predetermined positive DC voltage value. However, the reference voltage VREF2 is lower than the reference voltage VREF1. The reference voltage generation circuit 83 generates a voltage, which is kA times higher than the reference voltage VREF1, as the reference voltage VREF2. That is, “VREF2=VREF1×kA.” kA referred to here is less than 1 and has a positive value close to 1. Here, it is assumed that “kA=0.97.” When the signal SEN has a value of “0,” the operation of the reference voltage generation circuit 83 is stopped, so that the reference voltages VREF1 and VREF2 are not generated.
It may be considered that the internal power supply circuit 82 and the reference voltage generation circuit 83 constitute a voltage generation circuit. The voltage generation circuit constituted by the internal power supply circuit 82 and the reference voltage generation circuit 83 generate the reference voltage VREF1 by generating an internal power supply voltage VREG based on the input voltage VIN, and generate the reference voltage VREF2 based on the reference voltage VREF1 In the present disclosure, the voltage generation circuit may directly generate the reference voltage VREF1 from the input voltage VIN.
The low voltage protection circuit 84 is driven based on the internal power supply voltage VREG. The low voltage protection circuit 84 detects whether there is a low voltage abnormality in which the input voltage VIN is less than a predetermined low voltage determination voltage. When a low voltage abnormality is detected, the operation of the main amplifier 20 is stopped and the off-state of the output transistor M1 is ensured.
The overheating protection circuit 85 is driven based on the internal power supply voltage VREG. The overheating protection circuit 85 monitors a temperature of the semiconductor chip in the semiconductor device 1 and detects whether there is an overheating abnormality in which the temperature of the semiconductor chip exceeds a predetermined protection setting temperature. The overheating protection circuit 85 outputs a signal STSD having a value of “1” when the temperature of the semiconductor chip is equal to or higher than a protection set temperature, and otherwise outputs a signal STSD having a value of “0.” In the following, it is assumed that no overheating abnormality is detected (that is, the value of the signal STSD is “0”) unless otherwise specified.
The output discharge circuit 86 includes a discharge switching element connected between the output terminal OUT and the ground. The signals SENB and STSD are inputted to the output discharge circuit 86. When the signal SENB or STSD has a value of “1,” the output discharge circuit 86 turns on the discharge switching element to short-circuit the output terminal OUT and the ground, thereby quickly reducing the output voltage VOUT to 0 V or maintain the output voltage VOUT at 0 V. When the signals SENB and STSD have a value of “0,” the discharge switching element in the output discharge circuit 86 is kept in an off-state, and no current is generated between the output terminal OUT and the ground through the output discharge circuit 86.
Similar to the reference configuration, the driver 30 controls the gate voltage VG so as to become equal to or higher than a lower limit voltage VLL (e.g., 2 V) which is higher than 0 V. In other words, when the output voltage VOUT is maintained below the target voltage VTG due to “VIN<VTG,” the driver 30 can reduce the gate voltage VG to the lower limit voltage VLL, but does not perform any operation to lower the gate voltage VG to below the lower limit voltage VLL.
The current supply circuit 31H is provided between the wiring to which the input voltage VIN is applied and the node NDG, and generates a current IH flowing from the wiring to which the input voltage VIN is applied to the node NDG. The current supply circuit 31L is provided between the node NDG and the ground wiring WRGND, and generates a current IL flowing from the node NDG to the ground wiring WRGND.
The current driver 31 sets and changes the currents IH and IL based on the signal SAMP from the main amplifier 20. A method of setting the currents IH and IL will be explained starting from a basic state where “VOUT=VTG” and “IH=IL.”
When the potential of the signal SAMP decreases due to a decrease in the output voltage VOUT from the basic state, in response to the decrease in the potential of the signal SAMP, the current driver 31 decreases the current IH and increases the current IL, or increases the current IL without changing the current IH. As a result, it becomes that “IH<IL,” and the charges corresponding to the differential current (IL−IH) are drawn from the gate wiring WRG to the current driver 31, thereby lowering the gate voltage VG. The decrease in the gate voltage VG increases the drain current of the transistor M1, and the increase in the drain current of the transistor M1 has an effect of increasing the output voltage VOUT (however, the output voltage VOUT does not necessarily increase actually).
On the other hand, when the potential of the signal SAMP increases due to an increase in the output voltage VOUT from the basic state, in response to the increase in the potential of the signal SAMP, the current driver 31 decreases the current IL and increases the current IH, or increases the current IH without changing the current IL. As a result, it becomes that “IH>IL,” and the charges corresponding to the differential current (IH−IL) are supplied from the current driver 31 to the gate wiring WRG, thereby increasing the gate voltage VG. The increase in the gate voltage VG decreases the drain current of the transistor M1, and the decrease in the drain current of the transistor M1 has an effect of decreasing the output voltage VOUT (however, the output voltage VOUT does not necessarily decrease actually).
In the current driver 31, magnitudes of the currents IH and IL are set depending on not only the signal SAMP but also the gate voltage VG. Specifically, the current driver 31 can increase the gate voltage VG to the input voltage VIN by continuing an established state that “IH>IL.” When the gate voltage VG is increased to the input voltage VIN due to the establishment of “IH>IL,” then, it becomes that “IH=IL” no matter how high the potential of the signal SAMP is. Therefore, the gate voltage VG does not increase over the input voltage VIN. On the other hand, the current driver 31 can lower the gate voltage VG to the lower limit voltage VLL by continuing an established state that “IH<IL.” When the gate voltage VG drops to the lower limit voltage VLL due to the establishment of “IH<IL,” then, it becomes that “IH=IL” no matter how low the potential of the signal SAMP is. Therefore, the gate voltage VG does not become lower than the lower limit voltage VLL based on the operation of the driver 30 (current driver 31).
In this way, a control range of the gate voltage VG controlled by the driver 30 (current driver 31) is equal to or larger than the lower limit voltage VLL and equal to or less than the input voltage VIN. By setting a lower limit (>0) to the control range of the gate voltage VG, it is possible to improve the responsiveness of the output voltage VOUT to the variation in the input voltage VIN, as in the reference configuration.
However, as described above in respect of the reference configuration, when the input voltage VIN drops below the target voltage VTG, if the drop in the gate voltage VG is stopped at the lower limit voltage VLL, the differential voltage (VIN−VOUT) or (VIN−VTG) may become too large.
Taking this into consideration, the full-on circuit 40 is provided in the semiconductor device 1 according to the first embodiment. The full-on circuit 40 performs full-on driving of the output transistor M1 in a situation where the input voltage VIN becomes equal to or lower than the target voltage VTG and the output voltage VOUT becomes lower than the target voltage VTG by a predetermined value or more. The full-on driving of the output transistor M1 refers to an operation in which the gate voltage VG is lowered to substantially 0 V (set to a voltage lower than at least the lower limit voltage VLL).
When the output voltage VOUT drops below a predetermined determination voltage VDET lower than the target voltage VTG, the full-on circuit 40 lowers the gate voltage VG to below the lower limit voltage VLL prior to the operation of the driver 30. The determination voltage VDET referred to here is kA times higher than the output voltage VOUT. kA is the ratio of the reference voltage VREF2 to the reference voltage VREF1. As described above, “kA=0.97.”
Specifically, the full-on circuit 40 includes an active circuit 41 and a transistor 42. The active circuit 41 is an amplifier or a comparator and includes an inverting input terminal, a non-inverting input terminal, and an output terminal. The transistor 42 is an N-channel MOSFET. The inverting input terminal of the active circuit 41 is connected to the connection node between the voltage dividing resistors R1 and R2 to receive the feedback voltage VFB. The reference voltage VREF2 is inputted to the non-inverting input terminal of the active circuit 41. The output terminal of the active circuit 41 is connected to the gate of the transistor 42. The drain of the transistor 42 is connected to the gate wiring WRG (therefore, connected to the gate of the output transistor M1), and the source of the transistor 42 is connected to the ground wiring WRGND (therefore, connected to the ground).
The active circuit 41 is driven based on the internal power supply voltage VREG with the ground potential as a reference. The active circuit 41 compares the feedback voltage VFB inputted thereto with the reference voltage VREF2, and outputs a signal S41 based on the comparison result from its own output terminal. The output signal S41 of the active circuit 41 is supplied to the gate of the transistor 42. Therefore, the active circuit 41 controls the gate voltage of the transistor 42, thereby controlling a state (on-state or off-state) of the transistor 42. When the signal SEN has a value of “0,” when the signal STSD has a value of “1,” or when a low voltage abnormality is detected, the active circuit 41 stops the operation. When the active circuit 41 stops the operation, the gate voltage of the transistor 42 becomes 0 V, and the transistor 42 is fixed in an off-state.
When the feedback voltage VFB is higher than the reference voltage VREF2, the active circuit 41 lowers the voltage of the signal S41 to below the gate threshold voltage of the transistor 42 so that the transistor 42 comes into an off-state. When the feedback voltage VFB is lower than the reference voltage VREF2, the active circuit 41 increases the potential of the signal S41 so that a significant drain current flows through the transistor 42. That is, the active circuit 41 lowers the gate voltage VG to below the lower limit voltage VLL by generating a current flowing from the gate of the output transistor M1 to the ground through the transistor 42.
A case where the active circuit 41 is a comparator is considered. At this time, the active circuit 41 is called a comparator 41. The comparator 41 turns on or off the transistor 42 as a switch based on the feedback voltage VFB and the reference voltage VREF2.
That is, when “VFB<VREF2,” the comparator 41 turns on the transistor 42 by applying a signal S41 of a high level to the gate of the transistor 42. When the transistor 42 is turned on, the gate of the output transistor M1 and the ground are short-circuited through the transistor 42. Due to the short-circuiting, the gate voltage VG drops to substantially 0 V. The signal S41 of a high level has a potential sufficiently higher than a gate threshold voltage of the transistor 42, specifically a potential of the internal power supply voltage VREG. When the gate voltage VG is lower than the lower limit voltage VLL, the current driver 31 comes into a state in which currents IHand IL, which establish “IH>IL,” are generated regardless of the signal SAMP. Therefore, when the transistor 42 is controlled to be turned on by the comparator 41, a differential current (IH−IL) flows through the transistor 42.
Conversely, when “VFB>VREF2,” the comparator 41 turns off the transistor 42 by applying a signal S41 of a low level, which is sufficiently lower than the gate threshold voltage of the transistor 42, to the gate of the transistor 42. When the transistor 42 is turned off, a current flowing through the transistor 42 is not generated between the gate of the output transistor M1 and the ground. The signal S41 of a low level has a potential sufficiently lower than the gate threshold voltage of the transistor 42, specifically, a ground potential. When the feedback voltage VFB inputted to the comparator 41 and the reference voltage VREF2 are equal to each other, the signal S41 becomes a high level or a low level.
After the gate voltage VG becomes lower than the lower limit voltage VLL due to the current (drain current) flowing through the transistor 42, if the transistor 42 is turned off by the establishment of “VFB>VREF2,” the current driver 31 generates currents IH and IL that establish “IH>IL.” Therefore, the gate voltage VG rises toward the lower limit voltage VLL based on the differential current (IH−IL) (this holds true even if the active circuit 41 is an amplifier). Thereafter, based on the signal SAMP at the time when the gate voltage VG reaches the lower limit voltage VLL, the gate voltage VG increases over the lower limit voltage VLL, or the increase in the gate voltage VG stops at the lower limit voltage VLL.
In reality, it is desirable that the comparator 41 has hysteresis characteristics. The comparator 41 having hysteresis characteristics will be referred to as a hysteresis comparator 41. The operation related to the hysteresis comparator 41 will be described below.
If the establishment state of “VFB>VREF2” is shifted to the establishment state of “VFB<VREF2” starting from the time when the output signal S41 of the hysteresis comparator 41 is at a low level (therefore, the time when the transistor 42 is in an off-state), the hysteresis comparator 41 switches the output signal S41 from a low level to a high level, thereby switching the transistor 42 from an off-state to an on-state. Thereafter, the hysteresis comparator 41 maintains the output signal S41 at a high level until “VFB≥VREF2+ΔHYS” is established. If “VFB≥VREF2+ΔHYS” is established, the hysteresis comparator 41 returns the output signal S41 to a low level, thereby returning the transistor 42 from the on-state to the off-state. The voltage (VREF2+ΔHYS) is higher than the reference voltage V REF2 and lower than the reference voltage VREF1. For example, “VREF2=VREF1×0.97” and “VREF2+ΔHYS=VREF1×0.98.”
A case where the active circuit 41 is an amplifier is considered. In this case, the active circuit 41 is referred to as an amplifier 41. The operation of the full-on circuit 40 when the active circuit 41 is an amplifier is basically the same as the operation of the full-on circuit 40 when the active circuit 41 is a comparator.
That is, the amplifier 41 controls the gate voltage of the transistor 42 through the output of the signal S41 based on the feedback voltage VFB and the reference voltage VREF2. If “VFB<VREF2,” the amplifier 41 turns on the transistor 42 by raising the potential of the signal S41 to become higher than the gate threshold voltage of the transistor 42, thereby causing the transistor 42 to generate a drain current. Since the drain current of the transistor 42 flows from the gate wiring WRG toward the ground, the gate voltage VG is decreased by the drain current of the transistor 42. Depending on the magnitude of the drain current of the transistor 42, the gate voltage VG drops substantially to 0 V. As described above, when the gate voltage VG is lower than the lower limit voltage VLL, the current driver 31 comes into a state in which currents IH and IL, which establish “IH>IL,” are generated regardless of the signal SAMP. Therefore, when the transistor 42 is controlled to be turned on by the amplifier 41, a differential current (IH−IL) flows through the transistor 42.
Conversely, when “VFB>VREF2,” the amplifier 41 lowers the potential of the signal S41 to below the gate threshold voltage of the transistor 42, thereby turning off the transistor 42. When the transistor 42 is turned off, a current flowing between the gate of the output transistor M1 and the ground through the transistor 42 is not generated.
When the active circuit 41 is an amplifier, the potential of the signal S41 may be feedback-controlled near the gate threshold voltage of the transistor 42. This will be described with reference to
A behavior when the output current IOUT is increased in the case of
In the case of
In
When the value of the output current IOUT increases to the current value IB, the gate voltage VG drops to 0 V. After the value of the output current IOUT exceeds the current value IB, the full-on circuit 40 including the amplifier 41 maintains the gate voltage VG at 0 V.
In
In addition, the full-on circuit 40 monitors the feedback voltage VFB corresponding to the output voltage VOUT, and does not operate at all before “VIN≤VTG ” due to the drop in the input voltage VIN. Therefore, the full-on circuit 40 does not affect the normal regulation operation.
For example, when configuring an LDO which can output an output current IOUT of 1 A (ampere) as a specification, if full-on driving is not used, it is necessary to use an output transistor M1 having a relatively large size so that the output current IOUT of 1 A can be outputted even without full-on driving. On the other hand, by making the full-on driving available as in the present embodiment, an output current IOUT of 1 A can be outputted even if an output transistor M1 having a relatively small size is used. In other words, according to the present embodiment, it is possible to reduce the size of the output transistor (901 or M1) as compared to the reference configuration. The reduction in the size of the output transistor brings about a reduction in the gate capacitance of the output transistor. Therefore, it is expected to improve the responsiveness.
Further, the reference voltage VREF2 referenced by the full-on circuit 40 is generated based on the reference voltage VREF1 used for the original regulation operation. Therefore, when the reference voltage VREF1 deviates from the design value, the reference voltage VREF2 also deviates from the design value in conjunction therewith, and “VREF2=VREF1×kA” is maintained. Therefore, even if the reference voltage VREF1 varies, the full-on circuit 40 can operate as expected.
The circuit current of the driver 30 becomes large in a state in which “VIN≤VTG ” is established as compared to a state in which the input voltage VIN is sufficiently higher than the target voltage VTG. For this reason, for example, a configuration for detecting an increase in the circuit current of the driver 30 may be provided in the semiconductor device 1. When an increase in the circuit current of the driver 30 is detected (when the circuit current of the driver 30 is equal to or larger than a predetermined value), the circuit current (bias current) of the active circuit 41 may be increased as compared to a case where such is not the case. By increasing the circuit current of the active circuit 41, it is possible to improve the response speed of the active circuit 41 and to stabilize the frequency characteristics. When the active circuit 41 does not need to operate, the circuit current of the active circuit 41 is kept low, thereby suppressing unnecessary power consumption.
A second embodiment of the present disclosure will be described.
The overcurrent protection circuit 87 operates meaningfully only when a signal SEN is inputted to the overcurrent protection circuit 87 and the signal SEN has a value of “1.” The overcurrent protection circuit 87 is connected to the wiring to which the input voltage VIN is applied (i.e., the source of the output transistor M1) and the wiring to which the output voltage VOUT is applied (i.e., the drain of the output transistor M1), and is configured to detect whether or not the output transistor M1 is in an overcurrent state.
When it is detected that the output transistor M1 is in an overcurrent state, the overcurrent protection circuit 87 outputs a signal SOCP having a value of “1” and performs an overcurrent protection operation. An initial value of the signal SOCP is “0.” When the signal SOCP has a value of “0,” the overcurrent protection operation is not executed. The signal SOCP of “1” indicates that the output transistor M1 is in an overcurrent state, and the signal SOCP of “0” does not indicate that the output transistor M1 is in an overcurrent state. After starting the overcurrent protection operation, when it is detected that the overcurrent state is resolved, the overcurrent protection circuit 87 stops the overcurrent protection operation and changes the value of the signal SOCP from “1” to “.”
The overcurrent protection circuit 87 determines that the output transistor M1 is in an overcurrent state when the value of the output current IOUT exceeds a predetermined overcurrent determination value VALOCP. Reference is made to
After time t1, a factor which increases the output current IOUT is generated to thereby increase the output current IOUT, and at time t2, the value of the output current IOUT exceeds the overcurrent determination value IOCP. When it is detected at time t2 that the value of the output current IOUT exceeds the overcurrent determination value IOCP based on the voltage across the shunt resistor 87b, the overcurrent protection circuit 87 changes the value of the signal SOCP from “0” to “1” and starts an overcurrent protection operation.
In the overcurrent protection operation, the overcurrent protection circuit 87 controls the driver 30 so that the value of the output current IOUT is limited to the overcurrent determination value IOCP or less by referencing the voltage between both ends of the shunt resistor 87b.
During the execution period of the overcurrent protection operation, the control of the driver 30 by the overcurrent protection circuit 87 is given priority over the signal SAMP. Therefore, during the execution period of the overcurrent protection operation, under the control of the overcurrent protection circuit 87, the driver 30 controls the gate voltage VG so that the value of the output current IOUT is limited to the overcurrent determination value IOCP or less even if “VFB<VREF1.” Compared to the gate voltage VG immediately before time t2, the gate voltage VG increases during the execution period of the overcurrent protection operation, thereby limiting the value of the output current IOUT to the overcurrent determination value IOCP or less. Thereafter, although not particularly shown in the figure, when the increase factor of the output current IOUT is resolved and the value of the output current IOUT falls below the resolution determination value that is smaller than the overcurrent determination value IOCP, the overcurrent protection circuit 87 stops the overcurrent protection operation and changes the value of the signal SOCP from “1” to “0.”
In this way, the overcurrent protection operation performed when the overcurrent state of the output transistor M1 is detected acts to increase the gate voltage VG. On the other hand, during the execution period of the overcurrent protection operation, the value of the output current IOUT is limited to the overcurrent determination value IOCP or less even if “VFB<VREF1.” Therefore, during the execution period of the overcurrent protection operation, the output current IOUT required to maintain the output voltage VOUT at the target voltage VTG may not be outputted, and the output voltage VOUT may fall significantly below the target voltage VTG.
If the full-on circuit 40 were to operate based on such a decrease in the output voltage VOUT, the operation of the full-on circuit 40 would compete with the overcurrent protection operation. Therefore, in the semiconductor device 1A, as shown in
The active circuit 41 can operate when the signal SOCP has a value of “0.” More specifically, when the signal SEN has a value of “1,” the signals SOCP and STSD have a value of “0,” and no low voltage abnormality is detected, the active circuit 41 operates. As in the first embodiment, the active circuit 41 controls the gate voltage of the transistor 42 based on the result of comparison between the reference voltage VREF2 and the feedback voltage VFB.
The embodiments of the present disclosure may be appropriately modified in various ways within the scope of the technical idea defined in the claims. The above-described embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of respective components in the present disclosure are not limited to those described in the above embodiments. The specific numerical values shown in the above-mentioned explanatory text are merely examples, and it goes without saying that they may be changed to various numerical values.
The types of channels of the FETs (field effect transistors) shown in each embodiment are merely examples. Without detracting from the above-mentioned purpose, the channel type of any FET may be changed between a P-channel and an N-channel.
Any of the transistors mentioned above may be any type of transistor as long as no problem occurs. For example, any transistors mentioned above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, unless a problem occurs. Any transistor includes a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.
Supplementary notes will be provided regarding the present disclosure, in which specific configuration examples are shown in the above-described embodiments.
A linear regulator (1 or 1A) according to one aspect of the present disclosure includes: an input terminal (IN) configured to receive an input voltage (VIN); an output terminal (OUT) configured to be applied with an output voltage (VOUT); an output transistor (M1) connected between the input terminal and the output terminal, and constituted by a P-channel MOSFET; a gate control circuit (20 or 30) configured to control a gate voltage (VG) of the output transistor to stabilize the output voltage at a target voltage (VTG) based on a feedback voltage (VFB) corresponding to the output voltage; and an additional circuit (40), wherein a control range of the gate voltage controlled by the gate control circuit is equal to or higher than a predetermined lower limit voltage (VLL), and wherein the additional circuit is configured to lower the gate voltage to below the lower limit voltage when the output voltage falls below a determination voltage lower than the target voltage (first configuration).
This makes it possible to reduce the difference between the output voltage and the target voltage that may occur when the input voltage drops.
In the linear regulator of the first configuration, the gate control circuit controls the gate voltage based on a comparison result of the feedback voltage and a predetermined first reference voltage (VREF1), wherein the additional circuit compares the feedback voltage with a predetermined second reference voltage (VREF2) lower than the first reference voltage and lowers the gate voltage to below the lower limit voltage when the feedback voltage is lower than the second reference voltage (second configuration).
In the linear regulator of the second configuration, the additional circuit includes an additional transistor (42) provided between a gate of the output transistor and a ground, and an active circuit (41) configured to control a state of the additional transistor based on the feedback voltage and the second reference voltage, wherein the active circuit controls the additional transistor to be in an off-state when the feedback voltage is higher than the second reference voltage, and lowers the gate voltage to below the lower limit voltage by generating a current flowing from the gate of the output transistor to the ground through the additional transistor when the feedback voltage is lower than the second reference voltage (third configuration).
In the linear regulator of the third configuration, the active circuit is a comparator or an amplifier, and is configured to control a state of the additional transistor by controlling a voltage of a control electrode of the additional transistor based on the feedback voltage and the second reference voltage (fourth configuration).
The linear regulator of the fourth configuration further includes: a voltage generation circuit (82 or 83) configured to generate the first reference voltage based on the input voltage and generate the second reference voltage based on the first reference voltage (fifth configuration).
This makes it possible to suppress the influence of variation in the first reference voltage.
The linear regulator of the fifth configuration further includes: an overcurrent protection circuit (87) configured to detect that the value of the output current flowing through the output transistor exceeds a predetermined overcurrent determination value, wherein when the overcurrent protection circuit detects that the value of the output current exceeds the overcurrent determination value, the gate control circuit controls the gate voltage so as to limit the value of the output current to the overcurrent determination value or less, and the additional circuit stops an operation that causes a decrease in the gate voltage regardless of the output voltage (sixth configuration).
This makes it possible to avoid conflict between the overcurrent protection operation and the operation of the additional circuit.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-179450 | Nov 2022 | JP | national |
