This invention generally relates to voltage regulation, and more particularly, to a linear voltage regulating circuit with undershoot minimization and a method thereof.
A regulator, coupled between a voltage supply source and a load device, is used to provide a sufficiently constant output current to maintain the drive of a load device. When the load device undergoes a rapid load current transition, where current draw or load impedance alternates between a heavy load and light load, a typical regulator can have several shortcomings.
Due to loop bandwidth limitations in the load transient response of a transition from a heavy load to light load, the voltage regulator 100 is unable to turn off the pass transistor MPX in time. A large current from the MPX therefore results, and acts to immediately charge the load capacitor CL to increase the output voltage VOUT. This forces the voltage regulator 100 to enter a voltage overload condition. Upon stabilization of the voltage overload condition through the regulator loop, the output voltage VOUT should still be high enough to turn off the pass transistor MPX. However, the charge from the voltage overload stored in capacitor CL will undergo an exponential decay through the feedback network established by resistors R1 and R2. During the time interval between the removal of the output current load, and the appropriate response of the amplifier A1, the output voltage remains unregulated. Meanwhile, if the load device consumes the output current, such as in a case of load current ILOAD transitioning between a light load and heavy load, the output current will only be supplied from the load capacitor CL. This consequently decreases the output voltage VOUT.
When the output voltage VOUT is lower than the desired voltage level, the regulator loop can be activated to restore the output voltage VOUT to the desired level. However, due to loop bandwidth limitations, the output voltage VOUT will supply an undershot voltage to the load device before the pass transistor MPX can be turned on. Moreover, in turning on the pass transistor MPX that is initially turned off, the large gate capacitance of the pass transistor MPX will consume a large amount current. This acts to further worsen the undershot output voltage VOUT. An undershoot output voltage VOUT can therefore seriously hinder the operation of a load device.
U.S. Pat. No. 5,894,227 teaches a voltage regulator utilizing a comparator C1 to compare the gate voltage of the pass transistor and a reference voltage VTRIP in order to control a discharge transistor MPD. However, due to variations in fabrication processes, the reference voltage VTRIP may be set too high. This affects the operation of the discharge transistor MPD, and degrades the overall voltage regulation efficiency under a light load.
Other related art voltage regulators, such as that described in U.S. Pat. No. 5,966,004 and U.S. Pat. No. 6,201,375, utilize a regulator loop with an offset voltage to turn on the discharge transistor when the output voltage is higher than a reference voltage. Although the regulator loop may quickly discharge an initial output voltage, this voltage regulator still suffers from the same problem as described above. When the output voltage becomes lower than the reference voltage, the discharge path is identical to that mentioned in U.S. Pat. No 5,894,227. Since the discharge path still comprises a resistor network, recovery from an unregulated voltage condition may not be any faster due to the regulator loop.
Therefore, it is an objective of the present invention to provide a linear voltage regulating circuit with undershoot minimization and a method thereof. This circuit is intended to quickly restore the output voltage from an overshoot condition, and to provide proper voltage regulation under normal operation.
According to an embodiment of the present invention, a voltage regulating circuit for providing a regulated output voltage is disclosed. The voltage regulating circuit comprises a linear voltage regulator having a first output producing the linear output voltage and a second output producing a pass voltage, a converting circuit for converting the pass voltage into a first current and a second current passing through a first converting node and a second converting node respectively, a capacitive device coupled to the first converting node, a first current mirror module comprising a first current mirror path coupled to the first converting node and a second current mirror path coupled to the second converting node, and a second current mirror module comprising a first current mirror path coupled to the second converting node and a second current mirror path coupled to the first output. The capacitive device is capable of maintaining the first current mirror module for a charging/discharging period to allow the output voltage to recover from an overshoot condition. The output will be restored into a regulated condition when a load device experiences a transition from a heavy load to light load.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
The converting circuit 220 comprises a plurality of transistors M11, M12, M13, M14, where transistor M11 is a PMOS transistor and transistors M12, M13 and M14 are NMOS transistors. As shown in
A load device is coupled to the output of the linear regulator 210 and powered by the regulated output voltage Vout and its accompanying output current. For simplicity, the load device is represented by an equivalent RC circuit, comprising a resistor RL and a capacitor Cout coupled in parallel.
Under a load transient response of the linear regulator 210, when the transition from a heavy load to a light load occurs, the large output current that passes through the load device will suddenly decreases to become the small or zero output current. The current flowing through MP is forced to flow to the capacitor Cout, thus increasing Vout. Subsequently, Vf also increases. However, due to the slew rate of the error amplifier 212, the pass voltage Vp does not increase quickly enough in response to the increased feedback voltage Vf. Therefore, after a single loop delay, the error amplifier 212 produces a pass voltage Vp high enough to turn off the pass transistor MP. It should be noted that the output voltage Vout is charged to an overshoot output voltage immediately because of the loop delay time. As the pass transistor MP is turned off, transistors M11, M12, M13, and M14 are turned off accordingly. The diode-connected transistor M15 and transistor M16 in the first current mirror module 240, however, remain on and generate the third current I13 due to the capacitive device (i.e. the capacitor C1). Since transistor M13 is turned off, the current passing through the transistor M15 is forced to charge the capacitor C1 via the current path built between the gate and drain of the transistor M15.
According to the present invention, the value of capacitor C1 is large enough to maintain the first current mirror module 240 being activated for a charging period. Because transistor M14 is turned off, the voltage level at the second converting node N12 is no longer pulled down to the ground voltage, and the second current mirror module 250 is activated to induce a discharge current I14 in response to the received second current I12. The discharge current I14 then discharges the capacitor Cout and regulates the output voltage Vout. In this embodiment, the discharge current I14 is designed to be a percentage of the output current provided to the load device and is in proportion to the output current provided to the load device operating under a heavy load condition. This is because the larger the output current in heavy load condition, the higher the peak of the output voltage Vout when the transition from heavy load to light load occurs. Therefore, since the discharge current I14 depends upon the output current in heavy load condition, the linear voltage regulating circuit 200 can quickly recover from the undershoot condition to the under regulation condition. Please note that the capacitance of capacitor C1 should be properly designed such that the second current mirror module 250 remains on until the output voltage Vout has recovered from the overshoot status to the under regulation condition. After the charging period expires, transistors M15 and M16 are turned off because the gate voltage is pulled to approach Vin. Since there is no current flowing into the transistor M17, discharge current I14 is not induced and the linear voltage regulating circuit 200 enters into a steady light load condition.
The capacitive device, implemented by capacitor C2, has one of its ends coupled to the first converting node N21, and the other end coupled to a first reference voltage Vin. In addition, capacitor C2 has large value capacitance. The first current mirror module 340, which mirrors the first current I21 to generate a third current I23, comprises two transistors M23 and M24, where the transistor M23 is diode-connected to make capacitor C2 coupled to the first converting node N21. The current mirror ratio of the first current mirror module 340 is properly implemented such that the third current I23 is smaller than the second current I22. This results in the voltage level at the second converting node N22 being pulled up to approximately that of the first reference voltage Vin due to the second current I22, and transistors M25-M28 in the second current mirror module 350 being turned off accordingly. In other words, as the pass transistor MP is turned on due to the pass voltage Vp, the second current mirror module 350 is disabled without mirroring any current.
Similar to the previous exemplary embodiment, the load device coupled to the output of the linear regulator 310 is represented by an equivalent RC circuit including a resistor RL and a capacitor Cout coupled in parallel.
In the load transient response of the linear regulator 310, when the transition from a heavy load to light load occurs, a large output current passing through the load device suddenly decreases to become a small or zero output current. The current flowing through MP is forced to flow to the capacitor Cout, thus increasing Vout. Subsequently, Vf also increases. However, due to the slew rate of the error amplifier 312, the pass voltage Vp does not increase quickly enough to respond to the increased feedback voltage Vf. Therefore, after a single loop delay period, the error amplifier 312 will produce a pass voltage Vp high enough to turn off the pass transistor MP. It should be noted that the output voltage Vout is immediately charged to an overshoot output voltage because of the loop delay period. As the pass transistor MP is turned off, transistors M21 and M22 are also accordingly turned off. The diode-connected transistor M23 and transistor M24 in the first current mirror module 340 however still remain on, and generate a third current I23 to the capacitive device (i.e. the capacitor C2). Since transistor M21 is turned off, the current passing through transistor M23 is forced to discharge into capacitor C2. According to the present invention, the capacitance of capacitor C2 is large enough to maintain the first current mirror module 340 being on for the discharging period. Because transistor M22 is turned off, the voltage level at the second converting node N22 is no longer pulled up to the first reference voltage Vin, and the second current mirror module 350 is activated to induce a discharge current I24 in response to the received second current I23. The discharge current I24 then discharges the capacitor Cout, and regulates the output voltage Vout. Similar to the design of the above embodiment, the discharge current I24 is also configured to be proportional to the output current provided to the load device operating under a heavy load condition. As a result, the linear voltage regulating circuit 300 can quickly recover from the undershoot condition into the under regulation condition. Additionally, the capacitance of the capacitor C2 should be properly designed such that the second current mirror module 350 remains on until the output voltage Vout has recovered from the overshoot status to the under regulation condition. After the discharging period expires, the transistors M23 and M24 are turned off because the gate voltage is pulled down to approach the ground voltage. Since there is no current flowing into the transistor M25, discharge current I24 is not induced and the linear voltage regulating circuit 300 enters a steady light load condition.
The capacitive devices in the embodiments shown in
In the load transient response of the linear regulator 210 of the linear voltage regulating circuit 400, during the transition from heavy load to light load, the boosted pass voltage Vp acts to turn off transistor M41. As described above, transistors M15 and M16 still remain on. In addition, transistors M42 and M43 are turned on to form a current mirror, where the current passing through transistor M43 is K times as great as the current passing through transistor M42. Since these two current mirror paths share the same current source, (i.e. the drain current outputted from the transistor M15) the equivalent capacitive load viewed by the transistor M15 is substantially equal to (1+K)*C3. In this embodiment, K is defined to be significantly greater than one. The equivalent capacitive load viewed by transistor M15 therefore is substantially equal to K*C3. Please note that capacitor C3 has a small capacitance such that the chip area for implementing the capacitive device 430 is small. Accordingly, the gate voltage of transistors M15 and M16 is slowly increased because of the large capacitance load of value K*C3. Therefore, the capacitive device 430 is capable of maintaining the first current mirror module 240 being turned on during a charging period to allow the output voltage Vout to recover from the overshoot condition into the under regulation condition. After the output voltage Vout is restored to the under regulation condition, transistor M41, which is a long-channel transistor, is turned on and its drain current becomes equal to the drain current of transistor M42. As a result, no further current is provided to charge the capacitor C3.
In the load transient response of the linear regulator 310 of the linear voltage regulating circuit 500, when the transition from a heavy load to a light load occurs, the boosted pass voltage Vp turns off transistors M21 and M22. As described above, transistors M23 and M24 still remain on. As a result, the gate voltage of transistor M51 is pulled down to approach ground voltage, causing transistor M51 to turn off. However, transistors M52 and M53 are turned on to form a current mirror, where the current passing through the transistor M53 is K times the current passing through the transistor M52. Since these two current mirror paths share the same current source, (i.e. the drain current outputted from the transistor M23) the equivalent capacitive load viewed by transistor M23 is substantially equal to (1+K)*C4. In this embodiment, K is defined to be significantly greater than one. The equivalent capacitive load viewed by the transistor M15 therefore simplifies to approximate K*C4. Please note that capacitor C4 has a small capacitance such that the chip area for implementing the capacitive device 530 is small. Accordingly, the gate voltage of transistors M23 and M24 is slowly decreased because due to the large capacitance K*C4. Therefore, the capacitive device 530 is capable of maintaining the first current mirror module 340 to remain on for the discharging period, allowing the output voltage Vout to recover from the overshoot condition into the under regulation condition. After the output voltage Vout enters the under regulation condition, transistor M51, which is a long-channel transistor, is turned on and its source current becomes equal to the source current of transistor M52. As a result, no current is provided to discharge capacitor C4.
Please note that the circuit configurations of the above embodiments shown in
A method for providing a regulated output voltage is further disclosed, as shown in
Briefly summarized, the present disclosure provides a capacitive device that is capable of maintaining a first current mirror module remaining on for a charging/discharging period, and a method thereof. This allows the output voltage to recover from an overshoot condition, and enter an under regulation condition when the load device has a transition from a heavy load to a light load.
Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
5672959 | Der | Sep 1997 | A |
5894227 | Acuff | Apr 1999 | A |
5966004 | Kadanka | Oct 1999 | A |
6201375 | Larson | Mar 2001 | B1 |
6359427 | Edwards et al. | Mar 2002 | B1 |
6369554 | Aram | Apr 2002 | B1 |
7402987 | Lopata | Jul 2008 | B2 |
Number | Date | Country | |
---|---|---|---|
20080265853 A1 | Oct 2008 | US |