Patent Application
20130222052
1. Technical Field
Embodiments of the present disclosure relate generally to voltage regulators, and more specifically to a linear voltage regulator design for generating sub-reference output voltages.
2. Related Art
Linear voltage regulators generally refer to voltage regulators that receive an unregulated power source as input and provide a regulated output voltage, the regulation being achieved by controlling, using feedback techniques, the ON-resistance of a pass-device (such as a pass transistor) operated in its linear or saturation region of operation, depending on the type of the pass-device (e.g., whether a bipolar junction transistor or MOS transistor). A desired value of the regulated output voltage is typically set by comparing a fraction of the output voltage with a reference voltage, and adjusting the ON-resistance of the pass-device based on the difference of the output voltage and the reference voltage.
It is often desirable to use a linear voltage regulator to provide a sub-reference output voltage, i.e., an output voltage less than the reference voltage used in the regulator. Some prior techniques for generating such sub-reference output voltages are associated with drawbacks such as larger area for implementation, greater noise associated with the regulated output voltage, etc.
This Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
A linear voltage regulator comprises a voltage reference, a pass transistor, a voltage divider network, a first amplifier and a second amplifier. The voltage reference is designed to generate a reference voltage. The pass transistor is coupled between an external power source and an output terminal of the voltage regulator, an output of the voltage regulator being provided at the output terminal. The voltage divider network coupled between the output terminal and a constant reference potential. The first amplifier compares the reference voltage and a voltage at a first node in the voltage divider network and controls an impedance of the pass transistor. The second amplifier compares an output voltage of the output and a voltage at a second node in the voltage divider network, and injects a current into the first node, the current being proportional to a difference of the output voltage and the voltage at the second node.
Several embodiments of the present disclosure are described below with reference to examples for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the embodiments. One skilled in the relevant art, however, will readily recognize that the techniques can be practiced without one or more of the specific details, or with other methods, etc.
Example embodiments will be described with reference to the accompanying drawings briefly described below.
The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
Various embodiments are described below with several examples for illustration.
1. Linear Voltage Regulator
Voltage reference 110, which may be implemented as a band-gap reference, generates a reference voltage on path 112, which is connected to the inverting input (−) of OPAMP 120. Resistors 140 and 150 implement a voltage divider network, and the voltage at node 145 is fed back to the non-inverting input (+) of OPAMP 120. Output 123 of OPAMP 120 controls the ON-resistance of pass transistor 130 to maintain output voltage 149 at a desired constant voltage (regulated voltage). The connection of node 145 back to OPAMP 120 implements a closed-loop feedback for regulating output voltage 149. Terminal 101 receives an unregulated voltage from a power source such as, for example, a battery (not shown).
One drawback with the conventional implementation shown in
Vo=VBG*(1+R140/R150) Equation 1
It may be observed from Equation 1, that the minimum value of Vo obtainable is VBG. One prior technique for obtaining an output voltage less than VBG is to scale down VBG using a resistive divider, and connecting the scaled-down voltage to the inverting (−) terminal of OPAMP 120. However, such an approach may be associated at least with power dissipation in the resistive divider (used to obtain the scaled-down VBG), higher noise in the output voltage due to the resistive divider, and increased implementation area (to accommodate the resistive divider). Further, such an approach may also be associated with start-up issues such as longer time post start-up (e.g., power-ON) for output voltage Vo to settle within an acceptable margin of its steady-state value.
2. Generating Sub-Reference Output Voltages
Low-dropout regulator (LDO) 200 is shown containing voltage reference 210, OPAMPs 220 (first amplifier) and 270 (second amplifier), pass-transistor 230, and resistors 240 (R1), 250 (R2) and 260 (R3). Output capacitor 280 is also shown connected to the output terminal 290 of LDO 200, and is provided to improve the regulation provided by LDO 200. Terminal 291 represents the output terminal of voltage regulator 200, and generates an output voltage Vout. Although not shown, one or more units (e.g., voltage reference 210, OPAMP s 220 and 270) may be powered directly by node 201. The series combination of resistors R1, R2 and R3 operates as a voltage divider network.
Voltage reference 110, OPAMP 220, pass-transistor 230, and resistors R2 and R3 correspond respectively to voltage reference 110, OPAMP 120, pass-transistor 130, and resistors 140 and 150 of
OPAMP 220 operates in closed-loop negative feedback configuration to maintain the voltage at node 245 equal to Vbg generated by voltage reference 210.
OPAMP 270 is implemented as a transconductance amplifier, and generates an output current that is proportional to the difference in the voltages at the non-inverting (+) and inverting (−) input terminals of OPAMP 270. The non-inverting (+) input of OPAMP 270 is connected to output terminal 291. The inverting (−) input of OPAMP 270 is connected to node 256. The voltage (VSUB−BG−TAP) at node 256 (second node) is always less than the voltage (VFB) at node 245 (first node), and thus also less than Vbg. With corresponding changes in the connections components of
OPAMP 270 operates to maintain output voltage Vout at the same magnitude as the magnitude of the voltage VSUB−BG−TAP at node 256 by controlling the currents I1 and I2 respectively flowing through the resistor R1, and the series combination of resistors R2 and R3. Since VSUB−BG−TAP is at a lower voltage than FB, regulated output voltage Vout is also lower than Vbg, and equals the voltage VSUB−BG−TAP. OPAMP 270 ‘pushes’ current into the feedback node (245) of OPAMP 220, thereby causing current to flow in the reverse direction (i.e., from node 245 to node 291) in resistor R1. As a result, output voltage Vout is reduced below the reference voltage Vbg. By suitable selection of the ratio of R2 and R3, desired sub-reference values of Vout can be obtained.
The operation of LDO 200 to generate a sub-reference output voltage Vout may be viewed as occurring as follows:
At steady-state, the following equalities are satisfied:
VFB=Vbg,
Vout=VSUB−BG−TAP,
VSUB−BG−TAP=VFB*R3/(R2+R3),
Thus, Vout=Vbg*R3/(R2+R3),
The expressions for currents I1 and I2 are provided below:
I1=(VFB−Vout)/R1=Vbg*(R2/(R1*(R2+R3)))
I2=VFB/(R2+R3)=VBG/(R2+R3)
Several advantages of the technique of
LDO 200, implemented as described above, can be incorporated in a device or system, as described next.
3. Example System
Antenna 301 may receive various signals transmitted on a wireless medium. The received signals may be provided to analog processor 320 on path 302 for further processing. Analog processor 320 may perform tasks such as amplification (or attenuation as desired), filtering, frequency conversion, etc., on the received signals and provides the resulting processed signal on path 325.
ADC 350 converts the analog signal received on path 325 to corresponding digital values, which are provided on path 359 for further processing. Processing unit 390 receives the data values on path 359, and processes the data values to provide various user applications. LDO 200 provides a regulated voltage (with battery 310 being the power source) for the operation of each of analog processor 320, ADC 350, and processing unit 390. LDO 200 may be implemented as described in detail above.
While in the illustrations of
Further, while in
While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.
