1. Field of the Invention
The present invention relates to a linear voltage regulator and, more particularly, to a linear voltage regulator capable of effectively controlling an output voltage even while an input voltage source makes a transient.
2. Description of the Prior Art
Unfortunately, when the input voltage source Vin makes a transient, the regulating transistor 11 changes dramatically in operation, causing the output voltage Vout to be out of regulation and to oscillate for a long period of time. Referring to
Similarly, it is assumed that the input voltage source Vin makes a falling transient at time T2, and therefore the potential difference Vsg correspondingly makes a falling transient. The sudden fall in the potential difference Vsg rapidly suppresses the conductance of the regulating transistor 11, and at some time even completely turns off the regulating transistor 11 to cease the channel current lq. In this case, the output capacitor Cout must be discharged in order to compensate the unsatisfied requirement of the load current, and therefore the output voltage Vout decreases. Although through the feedback control provided by the error amplifying circuit 13, the output voltage Vout is eventually settled at the desired regulation value, as shown at time T3, the huge overshoot and extensive oscillation of the output voltage Vout fail to meet the requirement of most application specifications.
An object of the present invention is to provide a linear voltage regulator capable of preventing the operation state of the regulating transistor from dramatically changing while an input voltage source makes a transient, thereby improving the regulation control over the output voltage.
A linear voltage regulator according to the present invention includes a regulating transistor, a feedback circuit, an error amplifying circuit, an event detecting circuit, an enable controlling circuit, and a voltage clamping circuit. The regulating transistor has a control electrode, a first channel electrode, and a second channel electrode. The first channel electrode is connected to an input voltage source. The second channel electrode provides an output voltage. The feedback circuit generates a feedback signal representative of the output voltage. Based on comparison between the feedback signal and a predetermined reference voltage, the error amplifying circuit generates an error signal for controlling the control electrode. The event detecting circuit is coupled to the input voltage source and generates an event signal indicative of a transient event of the input voltage source. The enable controlling circuit generates an enable signal in response to the event signal. In response to the enable signal, the voltage clamping circuit clamps a potential difference between the first channel electrode and the control electrode.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The above-mentioned and other objects, features, and advantages of the present invention will become apparent with reference to the following descriptions and accompanying drawings, wherein:
The preferred embodiments according to the present invention will be described in detail with reference to the drawings.
In order to reduce the impact on regulating transistor 21 applied by the transient of the input voltage source Vin, the linear voltage regulator 20 according to the present invention is provided with an event detecting circuit 25, an enable controlling circuit 26, and a voltage clamping circuit 27. The event detecting circuit 25 generates an event signal DT for indicating the occurrence of the transient event of the input voltage source Vin. In response to the event signal DT, the enable controlling circuit 26 generates a first enable signal S1 and a second enable signal S2 for determining an effective operation time of the voltage clamping circuit 27. Since the transient of the input voltage Vin directly affects the potential difference Vsg between the source and gate electrodes of the regulating transistor 21, the voltage clamp circuit 27 restrains the potential difference Vsg under a predetermined clamp voltage in order to prevent the regulating transistor 21 from dramatically changing in operation.
More specifically, the event detecting circuit 25 may be formed by a capacitor Cs, a discharge current source 11, and a charge current source 12. The capacitor Cs has a first terminal connected to the input voltage source Vin and a second terminal connected to the discharge current source 11 through a current mirror M and a resistor R. The charge current source 12 is connected in parallel with the capacitor Cs. While the input voltage source Vin makes a transient, the voltage at the second terminal of the capacitor Cs correspondingly rises up along with the voltage at first terminal of the capacitor Cs because the potential difference across the capacitor Cs cannot be changed abruptly. Therefore, the desired event signal DT can be retrieved from the second terminal of the capacitor Cs. After the rising transient, the voltage at the second terminal of the capacitor Cs is gradually decreased by the discharge current source 11 for returning to the basic stable value BV. After the falling transient, the voltage at the second terminal of the capacitor Cs is gradually increased by the charge current source 12 for returning to the basic stable value BV. In one embodiment, the current provided by the discharge current source 11 is designed to be twice larger than the charge current source 12.
The enable controlling circuit 26 has a first comparator 26a and a second comparator 26b. Based on comparison between the event signal DT and a predetermined first trigger voltage Vt1, the first comparator 26a generates the first enable signal S1. Based on comparison between the event signal DT and a predetermined second trigger voltage Vt2, the second comparator 26b generates the second enable signal S2. The first trigger voltage Vt1 is designed to be higher than the basic stable value BV while the second trigger voltage Vt2 is designed to be lower than the basic stable value BV. Therefore, the first comparator 26a is triggered to generate the first enable signal S1 while the input voltage source Vin makes a rising transient, and the second comparator 26b is triggered to generate the second enable signal S2 while the input voltage source Vin makes a falling transient.
The voltage clamping circuit 27 has a high-side clamp unit 27a and a low-side clamp unit 27b. The first enable signal S1 determines an effective operation time of the high-side clamp unit 27a, and the second enable signal S2 determines an effective operation time of the low-side clamp unit 27b.
Similarly assumed that the input voltage source Vin makes a falling transient at time T2 such that the event signal DT of the event detecting circuit 25 suddenly dives down below the second trigger voltage Vt2 at the same time, the second comparator 26b of the enable controlling circuit 26 is triggered. After the falling transient, the event signal DT gradually increases and eventually returns to the basic stable value BV, especially at time T3 the event signal DT becoming higher than the first trigger voltage Vt2. Therefore, the second enable signal S2 generated by the second comparator 26b is a pulse signal for enabling the low-side clamp unit 27b from time T2 to time T3. The period from time T2 to time T3 is considered the effective operation time of the low-side clamp unit 27b, during which the regulating transistor 21 is prevented from being driven into saturation, thereby significantly improving the responses of the transistor current lq and the output voltage Vout.
Although the embodiment described above concurrently employs the first and second comparators 26a and 26b and the high-side and low-side clamp units 27a and 27b for improving the responses of the output voltage Vout to both of the rising and falling transients, the present invention is not limited to this and may be applied to a case where only the improvement in one direction, either rising or falling, is necessary. More specifically, if it is the response to the rising transient that needs to be improved, only are the first comparator 26a and the high-side clamp unit 27a necessary to be employed. On the other hand, if it is the response to the falling transient that needs to be improved, only are the second comparator 26b and the low-side clamp unit 27b necessary to be employed.
While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
5561391 | Wellnitz et al. | Oct 1996 | A |
6246555 | Tham | Jun 2001 | B1 |
6320363 | Oglesbee et al. | Nov 2001 | B1 |
6388433 | Marty | May 2002 | B2 |
6445167 | Marty | Sep 2002 | B1 |
6501253 | Marty | Dec 2002 | B2 |
6580257 | Marty | Jun 2003 | B2 |
6804102 | Hamon et al. | Oct 2004 | B2 |
6838916 | Premont et al. | Jan 2005 | B2 |
Number | Date | Country | |
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20070053115 A1 | Mar 2007 | US |