Linear voltage subtractor/adder circuit and MOS differential amplifier circuit therefor

Abstract

A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

Description

FIELD OF THE INVENTION

[0001] The present invention relates generally to a MOS differential amplifier circuit, and more particularly to a voltage subtractor/adder circuit formed on a semiconductor integrated circuit device and a MOS differential amplifier circuit which realizes such voltage subtractor/adder circuit and which has linear transconductance.

BACKGROUND OF THE INVENTION

[0002] FIG. 17 shows a conventional voltage subtractor/adder circuit described in a publication (IEEE Journal of Solid-State Circuits, Vol. CAS-32, No. 11, pp.1097-1104, November 1985). The circuit of FIG. 17 comprises two sets of MOS differential pairs. One of the MOS differential pairs comprises MOS transistors M1 and M2, and the other of the MOS differential pairs comprises MOS transistors M3 and M4. Each of the MOS differential pairs is driven by a tail current Iss.

[0003] In the voltage subtractor/adder circuit shown in FIG. 17, voltages V1 and V2 are applied to the gates of the transistors M1 and M4, respectively, of the two sets of MOS differential pairs. Both the transistors M2 and M3 are diode-coupled and are driven by a common constant current source (Iss).

[0004] Here, with respect to the two sets of MOS differential pairs, tail current values of respective MOS differential pairs and a current value of a constant current source which drives the diode-coupled transistors M2 and M3 are all the same. Therefore, the following formulas are obtained.

I D1 +I D2 =Iss   (1)

I D3 +I D4 =Iss   (2)

I D2 +I D3 =Iss   (3)

[0005] where, ID1, ID2, ID3 and ID4 designates drain currents of the transistors M1, M2, M3 and M4, respectively. Therefore, the following relations are also obtained.

I D1 =I D3   (4)

I D2 =I D4   (5)

[0006] That is, since the currents flowing through the transistors M1 and M2 are equal to the currents flowing through the transistors M3 and M4, respectively, the differential input voltages of the two sets of MOS differential pairs become equal to each other. Therefore, assuming that a common gate potential of the diode-coupled transistors M2 and M3 is V0, the following relation exists.

V 1 −V 0 =V 0 −V 2   (6)

[0007] That is, the following formula is obtained. 1$\begin{array}{cc}{V}_0=\frac{V_1+V_2}{2}& \left(7\right)\end{array}$

[0008] From this formula, it can be seen that the circuit shown in FIG. 17 functions as a voltage adder circuit. In this case, the differential input voltage of each of the MOS differential pairs becomes as follows: 2$\begin{array}{cc}{V}_1-V_0=V_0-V_2=\frac{V_1-V_2}{2}& \left(8\right)\end{array}$

[0009] Next, drain currents ID1 and ID4 of the transistors M1 and M4, respectively, of the MOS differential pairs will be derived.

[0010] Neglecting the body effect and the channel length modulation, and assuming that the relationship between a drain current and a gate-source voltage of a MOS transistor operating in saturation region follows the square-law, the drain current of a MOS transistor can be represented as follows:

I D =β(VGS−VTH)2 (VGS≧VTH)  (9a)

I D =0 (VGS≦VTH)  (9b)

[0011] Here, β=μ(COX/2)(W/L) is a transconductance parameter, μ is an effective mobility of carrier, COX is capacitance of a gate oxide film per unit area, W is a gate width, L is a gate length, and VTH is the threshold voltage of a MOS transistor.

[0012] Assuming that the MOS transistors are matched well, the drain currents of the transistors M1 and M4 become as follows: 3$\begin{array}{cc}\{\begin{array}{c}{I}_{\mathrm{D1}}=\frac{1}{2}\left\{I_{\mathrm{SS}}+\beta \frac{V_i}{2}\sqrt{\frac{2I_{\mathrm{SS}}}{\beta }-\frac{V_i^2}{4}}\right\}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le 2\sqrt{\frac{I_{\mathrm{SS}}}{\beta }}\right)\\ I_{\mathrm{D1}}=\frac{1}{2}{I}_{\mathrm{SS}}\mathrm{sgn}\left(V_i\right)\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\ge 2\sqrt{\frac{I_{\mathrm{SS}}}{\beta }}\right)\left(\text{10b}\right)\end{array}& \left(\text{10a}\right)\\ \{\begin{array}{c}{I}_{\mathrm{D4}}=\frac{1}{2}\left\{I_{\mathrm{SS}}+\beta \frac{V_i}{2}\sqrt{\frac{2I_{\mathrm{SS}}}{\beta }-\frac{V_i^2}{4}}\right\}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le 2\sqrt{\frac{I_{\mathrm{SS}}}{\beta }}\right)\\ I_{\mathrm{D4}}=\frac{1}{2}{I}_{\mathrm{SS}}\mathrm{sgn}\left(V_i\right)\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\ge 2\sqrt{\frac{I_{\mathrm{SS}}}{\beta }}\right)\left(\text{11b}\right)\end{array}& \left(\text{11a}\right)\end{array}$

[0013] where,

Vi=V 1 −V 2   (12)

[0014] Therefore, the circuit shown in FIG. 17 also functions as a voltage subtractor circuit. That is, the circuit shown in FIG. 17 is a voltage subtractor/adder circuit.

[0015] An explanation will now be made on a MOS differential amplifier circuit which has linear transconductance. FIG. 18 shows a general structure of this type of MOS differential amplifier circuit which is disclosed in Japanese patent laid-open publication No. 7-127887. The circuit of FIG. 18 comprises a MOS differential pair having MOS transistors M1 and M2 which are driven by a tail current Iss (=I0+βVi2/2).

[0016] Assuming that the MOS transistors are matched well, a differential output current ΔID=ID1−ID2 of the MOS differential pair comprising the transistors M1 and M2 becomes as follows: 4$\&AutoLeftMatch;\{\begin{array}{cc}\Delta I_D=\beta V_i\sqrt{\frac{2I_{\mathrm{SS}}}{\beta }-V_i^2}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{\beta }}\right)& \left(\text{13a}\right)\\ \Delta I_D=I_{\mathrm{SS}}\mathrm{sgn}\left(V_i\right)\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\ge \sqrt{\frac{I_{\mathrm{SS}}}{\beta }}\right)& \left(\text{13b}\right)\end{array}$

[0017] Therefore, when the value within {square root}{square root over ( )} in the formula (13a) is a constant value, the differential output current ΔID of the MOS differential pair becomes linear. That is, the condition of the tail current in an adaptive-biasing differential pair becomes as follows: 5$\begin{array}{cc}{I}_{\mathrm{SS}}=I_0+\frac{1}{2}\beta V_i^2& \left(14\right)\end{array}$

[0018] Therefore, by driving a MOS differential pair by using a tail current which has a square-law characteristic of an input voltage, it is possible to completely compensate transconductance of the MOS differential pair. The method of driving a MOS differential pair by using a current which varies dynamically such that the transconductance becomes linear is called an adaptive-biasing method. Also, the differential pair which has a linear transconductance obtained in this way is called an adaptive-biasing differential pair.

[0019] FIG. 19 shows an example of a concrete circuit of an adaptive-biasing differential pair in which a tail current is supplied thereto by using quadri-tail cell as a squaring circuit.

[0020] An output current IL of an output of the quadri-tail cell shown in FIG. 19 can be obtained as follows: 6$\begin{array}{cc}{I}_L=I_{\mathrm{D3}}+I_{\mathrm{D4}}& \left(15\right)\\ \{\begin{array}{c}{I}_L=\frac{I_0}{4}-\frac{\beta V_i^2}{4}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{2I_0}{3\beta }}\right)\\ I_L=\frac{2}{3}-I_0\frac{\beta V_i^2+2\beta \&LeftBracketingBar;V_i\&RightBracketingBar;\sqrt{2\left(\frac{6I_0}{\beta }-V_i^2\right)}}{18}\left(\text{15b}\right)\\ \left(\sqrt{\frac{2I_0}{3\beta }}\le \&LeftBracketingBar;V_i\&RightBracketingBar;\le 2\sqrt{\frac{I_0}{\beta }}\right)\\ I_L=0\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\ge 2\sqrt{\frac{I_0}{\beta }}\right))\left(\text{15c}\right)\end{array}& \left(\text{15a}\right)\end{array}$

[0021] Therefore, it is possible to obtain a square-law current.

[0022] In order to adaptively bias a MOS differential pair by driving the MOS differential pair by using the output current of the quadri-tail cell, it is possible to set the tail current as determined by the following formula:

Iss =2I0−2IL  (16)

[0023] By setting the tail current in accordance with the above formula, transconductance becomes a constant value gm={square root}{(2I0)/β}, in a range of an input voltage |Vi|≦{square root}{square root over ( )}{(2I0)/(3β)}.

[0024] A differential output current ΔI (=ID1−ID2) of an adaptive-biasing differential pair which uses the quadri-tail cell becomes as follows: 7$\&AutoLeftMatch;\begin{array}{cc}\{\begin{array}{c}\Delta I=\sqrt{\frac{2I_0}{\beta }}{V}_i\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{2I_0}{3\beta }}\right)\\ \Delta I=\frac{\beta V_i}{3}\sqrt{12\frac{I_0}{\beta }-7V_i^2+4\&LeftBracketingBar;V_i\&RightBracketingBar;\sqrt{2\left(\frac{6I_0}{\beta }-V_i^2\right)}}\left(\text{17b}\right)\\ \left(\sqrt{\frac{2I_0}{3\beta }}\leqq \&LeftBracketingBar;V_i\&RightBracketingBar;\leqq \sqrt{\left(1+\frac{1}{\sqrt{2}}\right)\frac{I_0}{\beta }}\right)\\ \Delta I=\frac{\beta V_i^2+6I_0+2\beta \&LeftBracketingBar;V_i\&RightBracketingBar;\sqrt{2\left(\frac{6I_0}{\beta }-V_i^2\right)}}{9}\left(\text{17c}\right)\\ \left(\sqrt{\left(1+\frac{1}{\sqrt{2}}\right)\frac{I_0}{\beta }}\leqq \&LeftBracketingBar;V_i\&RightBracketingBar;\leqq 2\sqrt{\frac{I_0}{\beta }}\right)\\ \Delta I=2I_0\mathrm{sgn}\left(V_i\right)\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\ge \sqrt{\frac{I_0}{\beta }}\right)\left(\text{17d}\right)\end{array}& \left(\text{17a}\right)\end{array}$

[0025] Transconductance can be obtained by differentiating the formulas (17a) through (17d) by an input voltage Vi. 8$\&AutoLeftMatch;\begin{array}{cc}\{\begin{array}{c}\frac{d\left(\Delta I\right)}{d{V}_i}=\sqrt{\frac{2I_0}{\beta }}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{2I_0}{3\beta }}\right)\\ \frac{d\left(\Delta I\right)}{d{V}_i}=\frac{\beta }{3}\sqrt{12\frac{I_0}{\beta }-7V_i^2+4\&LeftBracketingBar;V_i\&RightBracketingBar;\sqrt{2\left(\frac{6I_0}{\beta }-V_i^2\right)}}+\\ \frac{\beta }{3}{V}_i\left\{-7V_i+2\mathrm{sgn}\left(V_i\right)\sqrt{2\left(\frac{6I_0}{\beta }-V_i^2\right)}-\frac{4\beta \&LeftBracketingBar;V_i\&RightBracketingBar;V_i}{\sqrt{2\left(\frac{6I_0}{\beta }-V_i^2\right)}}\right\}\\ \frac{1}{\sqrt{\frac{12I_0}{\beta }-7V_i^2+4\&LeftBracketingBar;V_i\&RightBracketingBar;\sqrt{2\left(\frac{6I_0}{\beta }-V_i^2\right)}}}\left(\text{18b}\right)\\ \left(\sqrt{\frac{2I_0}{3\beta }\le \&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\left(1+\frac{1}{\sqrt{2}}\right)\frac{I_0}{\beta }}}\right)\\ \frac{d\left(\Delta I\right)}{d{V}_i}=\frac{2\beta }{9}\{V_i+\mathrm{sgn}\left(V_i\right)\sqrt{2\left(\frac{6I_0}{\beta }-V_i^2\right)}-\left(\text{18c}\right)\\ \frac{4\beta \&LeftBracketingBar;V_i\&RightBracketingBar;V_i}{\sqrt{2\left(\frac{6I_0}{\beta }-V_i^2\right)}}\}\\ \frac{d\left(\Delta I\right)}{d{V}_i}=0\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\ge 2\sqrt{\frac{I_0}{\beta }}\right)\left(\text{18d}\right)\end{array}& \left(\text{18a}\right)\end{array}$

[0026] As can be seen from the above formulas, the transconductance of an adaptive-biasing differential pair becomes a constant value gm={square root}{square root over ( )}{(2I0)/β}, that is, the transconductance of an adaptive-biasing differential pair shows a flat characteristic, in a range of an input voltage |Vi|≦{square root}{square root over ( )}{(2I0)/(3β)}.

[0027] Although the above-mentioned voltage adder circuit has both the subtraction function and addition function, the subtraction function is inferior in linearity to the addition function.

[0028] Also, in a linear transconductance amplifier for realizing both the subtraction function and addition function, an input voltage range in which the linear transconductance amplifier operates linearly depends on an input voltage range within which the squaring circuit for supplying the tail current has a square-law characteristic. However, it is difficult to realize a squaring circuit which has an input voltage range within which the squaring circuit shows a square-law characteristic throughout the whole operating input voltage range of the MOS differential pair. Therefore, conventionally, it was impossible to realize a linear transconductance amplifier having a wide linear input voltage range.

[0029] In the field of analog signal processing, a circuit for performing subtraction and/or addition is an essential function block. Especially, the requirement for realizing a MOS differential amplifier circuit having linear subtraction and addition function has become stronger.

[0030] Also, such MOS differential amplifier circuit having linear subtraction and addition function can be realized by using a differential amplifier circuit having linear transconductance. Therefore, such differential amplifier circuit having linear transconductance is also an essential function block in the field of analog signal processing. Especially, the requirement for realizing a MOS differential amplifier circuit having linear transconductance has become stronger.

SUMMARY OF THE INVENTION

[0031] Therefore, it is an object of the present invention to provide a MOS differential amplifier circuit which has linear subtraction and addition function over a wide input voltage range.

[0032] It is another object of the present invention to provide a MOS differential amplifier circuit which has linear subtraction and addition function and which is easily implemented in an LSI device.

[0033] It is still another object of the present invention to provide a MOS differential amplifier circuit which has subtraction and addition function and which has simple circuit structure.

[0034] It is still another object of the present invention to provide a MOS differential amplifier circuit which has linear transconductance over a wide input voltage range.

[0035] It is still another object of the present invention to provide a MOS differential amplifier circuit which has linear transconductance and which is easily implemented in an LSI device.

[0036] It is still another object of the present invention to obviate the disadvantages of the conventional MOS differential amplifier circuits.

[0037] According to an aspect of the present invention, there is provided a voltage subtractor/adder circuit comprising: a differential pair having first and second MOS transistors, gate electrodes of said first and second MOS transistors forming input terminals for receiving an input differential voltage, drain electrodes of said first and second MOS transistors forming output terminals for outputting a subtraction output signal, and source electrodes of said first and second MOS transistors being commonly coupled to form an output terminal for addition output voltage; and wherein the sum of currents flowing through said first and second MOS transistors increases in proportion to the square of said input differential voltage.

[0038] In this case, it is preferable that the voltage subtractor/adder circuit further comprises a level shifter for level-shifting the addition output voltage from the source electrodes which are commonly coupled.

[0039] According to another aspect of the present invention, there is provided a voltage subtractor/adder circuit comprising: a differential pair having first and second MOS transistors, gate electrodes of the first and second MOS transistors forming input terminals for receiving an input differential voltage, drain electrodes of the first and second MOS transistors forming output terminals for outputting a subtraction output signal, and source electrodes of the first and second MOS transistors being commonly coupled to form an output terminal for addition output voltage; and a constant current source which drives the differential pair.

[0040] In this case, it is preferable that the voltage subtractor/adder circuit further comprises a level shifter for level-shifting the addition output voltage from the source electrodes which are commonly coupled.

[0041] According to still another aspect of the present invention, there is provided a MOS differential amplifier circuit comprising: a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of the first and second MOS transistors being commonly coupled and being driven by a current source; and wherein current value of the current source being controlled such that a difference voltage between a common mode voltage and a common source voltage of the first and second MOS transistors becomes a constant value.

[0042] In this case, it is also preferable that the MOS differential amplifier circuit further comprises a level shifter for level-shifting the common source volage of the first and second MOS transistors.

[0043] According to still another aspect of the present invention, there is provided a MOS differential amplifier circuit comprising: a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of the first and second MOS transistors being commonly coupled and being driven by a constant current source; and wherein a current is injected into the constant current source such that a difference voltage between a common mode voltage and a common source voltage of the first and second MOS transistors becomes a constant voltage.

[0044] According to still another aspect of the present invention, there is provided a MOS differential amplifier circuit comprising: a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of the first and second MOS transistors being commonly coupled and being driven by a constant current source; and third and fourth MOS transistors which are load transistors of the first and second MOS transistors, respectively, and whose gates receive the sum of a predetermined constant voltage and a voltage obtained by subtracting a common source voltage of the first and second MOS transistors from a common mode voltage.

[0045] According to still another aspect of the present invention, there is provided a complementary MOS differential amplifier circuit comprising: a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of the first and second MOS transistors being commonly coupled and being driven by a first constant current source; a MOS quadri-tail cell having third, fourth, fifth and sixth MOS transistors which have different conductivity type from that of the first and second MOS transistors, source electrodes of the third, fourth, fifth and sixth MOS transistors being commonly coupled and being driven by a second constant current source; wherein gate electrodes of the fifth and sixth MOS transistors being coupled to a common source electrode of the first and second MOS transistors, drain electrodes of the fifth and third MOS transistors being commonly coupled and forming one output terminal, drain electrodes of the sixth and fourth MOS transistors being commonly coupled and forming the other output terminal, and gate electrodes of the first and second MOS transistors and gate electrodes of the third and fourth MOS transistors receiving input voltages.

[0046] In this case, it is preferable that the complementary MOS differential amplifier circuit further comprises level shifters for level-shifting the input voltages before being applied to the gate electrodes of the first and second MOS transistors and the gate electrodes of the third and fourth MOS transistors.

[0047] It is also preferable that the ratio of the current value of the first constant current source and transconductance parameter of the first and second MOS transistors is approximately half of the ratio of the current value of the second constant current source and transconductance parameter of the third, foruth, fifth and sixth MOS transistors.

[0048] It is further preferable that the complementary MOS differential amplifier circuit comprises first and second MOS differential amplifier circuits each of which is the complementary MOS differential amplifier circuit as set forth above, wherein corresponding MOS transistors of the first and second MOS differential amplifier circuits have mutually different conductivity types and wherein the first and second MOS differential amplifier circuits are coupled parallel to form a differential input pair.

[0049] It is also advantageous that transconductance of the MOS differential amplifier circuit is adjustable by controlling current values of at least one of the first and second constant current sources.

[0050] Constitution of the present invention is again described briefly in other words. The linear voltage subtractor/adder circuit according to the present invention has a structure in which gate electrodes of first and second transistors constitute a pair of input terminals or an input terminal pair, and drains of the first and second transistors constitute a pair of subtraction output terminals or a subtraction output terminal pair. Source electrodes of the first and second transistors are commonly coupled and constitute an addition output terminal. The sum of currents flowing through the first and second transistors increases in proportion to a differential input voltage.

[0051] Also, a simplified voltage subtractor/adder circuit according to the present invention has a structure in which gate electrodes of first and second transistors constitute a pair of input terminals or an input terminal pair, and drains of the first and second transistors constitute a pair of subtraction output terminals or a subtraction output terminal pair. Source electrodes of the first and second transistors are commonly coupled to constitute an addition output terminal and are driven by a constant current source.

[0052] In a CMOS differential amplifier circuit having linear transconductance according to the present invention, an input pair is composed of a MOS differential pair in which source electrodes of first and second transistors are commonly coupled and are driven by a current source. The current value of the current source is controlled such that a difference voltage between the common mode voltage and the common source voltage of the first and second transistors becomes a constant voltage.

[0053] In other constitution, an input pair is composed of a MOS differential pair in which source electrodes of first and second transistors are commonly coupled and are driven by a constant current source, and a current is sourced into the constant current source such that a difference voltage between the common mode voltage and the common source voltage of the first and second transistors becomes a constant voltage.

[0054] Further, a MOS differential amplifier circuit having linear transconductance according to the present invention comprises a MOS differential pair and a MOS quadri-tail cell coupled parallel with the MOS differential pair. Transistors constituting the MOS differential pair have different conductivity type from that of transistors constituting the MOS quadri-tail cell.

[0055] Operation of the present invention will now be described. Non-linearity of a MOS differential pair is caused by an increase in the common source voltage according to an increase in an input voltage. Therefore, in the MOS differential pair, it is possible to obtain a drive current which is proportional to the square of an input voltage, by controlling a tail current such that the difference between the common source voltage and the input common mode voltage becomes constant. Thereby, the tail current driving the MOS differential pair becomes a current which is proportional to the square of an input voltage. Thus, it is possible to equivalently obtain an adaptive-biasing differential pair and to realize a CMOS differential amplifier circuit having linear transconductance. By such structure of the present invention, the difference between the common source voltage and the input common mode voltage becomes constant, so that a voltage addition function can be obtained. Also, the differential output current is proportional to the differential input voltage, so that a voltage subtraction function can be obtained. As a result thereof, it is possible to realize a linear voltage subtractor/adder circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0056] These and other features, and advantages, of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals designate identical or corresponding parts throughout the figures, and in which:

[0057] FIG. 1 is a circuit diagram showing a general structure of a voltage subtractor/adder circuit according to an embodiment of the present invention;

[0058] FIG. 2 is a circuit diagram showing a general structure of a voltage subtractor/adder circuit, which includes a level shifter, according to another embodiment of the present invention;

[0059] FIG. 3 is a circuit diagram showing a structure of a voltage subtractor/adder circuit according to still another embodiment of the present invention;

[0060] FIG. 4 is a graph showing characteristics of output voltages of a MOS differential pair having load transistors shown in FIG. 3;

[0061] FIG. 5 is a graph showing characteristics of output currents of a quadri-tail cell shown in FIG. 3;

[0062] FIG. 6 is a circuit diagram showing a structure of a voltage subtractor/adder circuit, which includes a level shifter, according to still another embodiment of the present invention;

[0063] FIG. 7 is a circuit diagram showing a structure of a voltage subtractor/adder circuit, which includes a level shifter, according to still another embodiment of the present invention;

[0064] FIG. 8 is a circuit diagram showing a structure of a MOS differential amplifier circuit according to an embodiment of the present invention;

[0065] FIG. 9 is a circuit diagram showing an example of an adder circuit for producing an input common mode voltage;

[0066] FIG. 10 is a circuit diagram showing a structure of a MOS differential amplifier circuit according to another embodiment of the present invention;

[0067] FIG. 11 is a circuit diagram showing a structure of a MOS differential amplifier circuit according to still another embodiment of the present invention;

[0068] FIG. 12 is a circuit diagram showing a structure of a MOS differential amplifier circuit according to still another embodiment of the present invention;

[0069] FIG. 13 is a circuit diagram showing a structure of a MOS differential amplifier circuit according to still another embodiment of the present invention;

[0070] FIG. 14 is a circuit diagram showing a structure of a MOS differential amplifier circuit according to still another embodiment of the present invention;

[0071] FIG. 15 is a circuit diagram showing a structure of a MOS differential amplifier circuit according to still another embodiment of the present invention;

[0072] FIG. 16 is a circuit diagram showing a structure of a MOS differential amplifier circuit according to still another embodiment of the present invention;

[0073] FIG. 17 is a circuit diagram showing a structure of a conventional voltage subtractor/adder circuit;

[0074] FIG. 18 is a circuit diagram showing a general structure of an adaptive-biasing differential pair; and

[0075] FIG. 19 is a circuit diagram showing a conventional MOS differential amplifier circuit comprising a MOS differential pair and a quadri-tail cell.

DESCRIPTION OF A PREFERRED EMBODIMENT

[0076] FIG. 1 is a circuit diagram showing a general structure of a voltage subtractor/adder circuit having linear subtraction and addition function according to the present invention.

[0077] The circuit of FIG. 1 has a MOS differential pair which comprises transistors M1 and M2 driven by a tail current Iss (=I0+βVi2/2). Assuming the transistors M1 and M2 are well matched with each other, the differential output current ΔID (=ID1−ID2) of the MOS differential pair comprising the transistors M1 and M2 is represented as follows: 9$\&AutoLeftMatch;\begin{array}{cc}\{\begin{array}{c}\Delta I_D=\beta V_i\sqrt{\frac{2I_{\mathrm{SS}}}{\beta }-V_i^2}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{\beta }}\right)\\ \Delta I_D=I_{\mathrm{SS}}\mathrm{sgn}\left(V_i\right)\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\ge \sqrt{\frac{I_{\mathrm{SS}}}{\beta }}\right)\left(\text{19b}\right)\end{array}& \left(\text{19a}\right)\end{array}$

[0078] Therefore, the condition the differential output current ΔID of the MOS differential pair becomes linear is that the value within {square root}{square root over ( )} in the formula (19a) is a constant value. That is, in order for the MOS differential pair to become an adaptive-biasing differential pair, the condition of the tail current should be as follows: 10$\begin{array}{cc}{I}_{\mathrm{SS}}=I_0+\frac{1}{2}\beta V_i^2\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{2I_0}{\beta }}\right)& \left(20\right)\end{array}$

[0079] The above formula (20) differs from the formula (14) in that, in the formula (20), an input voltage range is limited within the specified range. However, when the transconductance of the MOS differential pair is to be compensated, it is natural that such compensation is not effective outside the operational input voltage range of the MOS differential pair.

[0080] Therefore, it is possible to completely compensate the transconductance of the MOS differential pair by driving the MOS differential pair with a tail current having a square-law characteristic of an input voltage. In this case, the differential output current ΔID (=ID1−ID2) is obtained as follows: 11$\begin{array}{cc}\Delta I_D=\sqrt{2\beta I_0{V}_i}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{2I_0}{\beta }}\right)& \left(21\right)\end{array}$

[0081] Therefore, by converting the differential output current ΔID into a corresponding voltage, it is possible to obtain a linear subtraction output.

[0082] On the other hand, the common source voltage Vs can be obtained by solving the following formulas. 12$\begin{array}{cc}{I}_{\mathrm{D1}}={\beta \left(\frac{V_1+V_2}{2}+\frac{V_i}{2}-V_S-V_{\mathrm{TH}}\right)}^2& \left(22\right)\\ I_{\mathrm{D2}}={\beta \left(\frac{V_1+V_2}{2}-\frac{V_i}{2}-V_S-V_{\mathrm{TH}}\right)}^2& \left(23\right)\\ I_{\mathrm{D1}}+I_{\mathrm{D2}}=I_{\mathrm{SS}}=I_0+\frac{1}{2}\beta V_i^2& \left(24\right)\end{array}$

[0083] By solving the formulas (22) through (24), it is possible to obtain the following formula. 13$\begin{array}{cc}{V}_S=\frac{V_1+V_2}{2}-\sqrt{\frac{I_o}{\beta }}-V_{\mathrm{TH}}& \left(25\right)\end{array}$

[0084] This formula shows that, from the common source voltage Vs, it is possible to obtain an addition voltage of input signals.

[0085] The common source voltage Vs includes a constant offset voltage −{square root}{square root over ( )}(I0/β)−VTH. Therefore, as shown in FIG. 2, it is possible to remove the offset voltage by level-shifting the common source voltage Vs to obtain an addition voltage (V1+V2)/2.

[0086] FIG. 3 is a circuit diagram showing an example of a practical circuit for realizing a voltage subtraction and addition circuit shown in FIG. 2.

[0087] The circuit of FIG. 3 has a MOS differential pair which comprises transistors M1 and M2 each having a transistor size ratio (that is, gate width W/gate length L) with respect to a unit transistor is K1 and which is driven by a constant current Iss (=I0/2). The circuit of FIG. 3 also has a triple-tail cell in which source electrodes of unit transistors M5 and M6 and of a transistor M7 having a transistor size ratio K3 with respect to a unit transistor are commonly coupled and which is driven by a constant current I0. The circuit of FIG. 3 further has a transistor M8 for supplying a bias voltage of the transistor M7, and a constant current source Iss/2 (=I0/4) for driving the transistor M8. From the circuit analysis described below, it is possible to obtain a relation Iss=I0/2. Also, the transistor M7 can be divided into two pieces and can be represented as M7A and M7B.

[0088] Assuming that the transistors are well matched, output currents of the MOS differential pair comprising the transistors M1 and M2 each of which has a transistor size ratio of K1 with respect to a unit transistor are represented as follows: 14$\begin{array}{cc}{I}_{\mathrm{D1}}=\frac{1}{2}\left\{I_0+K_1\beta V_i\sqrt{\frac{2I_{\mathrm{SS}}}{K_1\beta }-V_i^2}\right\}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{K_1\beta }}\right)& \left(\text{26a}\right)\\ I_{\mathrm{D2}}=\frac{1}{2}\left\{I_0-K_1\beta V_i\sqrt{\frac{2I_{\mathrm{SS}}}{K_1\beta }-V_i^2}\right\}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{K_1\beta }}\right)& \left(\text{26b}\right)\end{array}$

[0089] Also, the output currents of the MOS differential pair are compressed to their square-roots and converted into corresponding voltages, by the transistors M3 and M4 each of which has a transistor size ratio K2 with respect to the unit transistor as a load transistor. Here, a differential output voltage of the MOS differential pair becomes linear based on the following formula. 15$\begin{array}{cc}b\left(\sqrt{a+\sqrt{2x}\sqrt{1-\frac{x^2}{2}}}-\sqrt{a-\sqrt{2x}\sqrt{1-\frac{x^2}{2}}}\right)=b\sqrt{2x}& \left(\text{27a}\right)\end{array}$

[0090] where,

a =1, b={square root}{square root over ( )}(Iss/2), x=Vi/{square root}{square root over ( )}(Iss/(K1β))  (27b)

[0091] Therefore, the following relation is obtained: 16$\begin{array}{cc}\sqrt{I_{\mathrm{D1}}}-\sqrt{I_{\mathrm{D2}}}=\sqrt{K_1\beta }{V}_i\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{K_1\beta }}\right)& \left(28\right)\end{array}$

[0092] That is, a term {square root}{square root over ( )}ID1−{square root}{square root over ( )}ID2 becomes linear. Thus, the MOS differential pair has a linear term:

{square root}{square root over (K1β)}Vi(={square root}{square root over (ID1)}−{square root}{square root over (ID2)})  (29a)

[0093] and a non-linear term: 17$\begin{array}{cc}\sqrt{I_{\mathrm{D1}}}+\sqrt{I_{\mathrm{D2}}}=\sqrt{K_1\beta }\sqrt{\frac{2I_{\mathrm{SS}}}{K_1\beta }-V_i^2}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{K_1\beta }}\right)& \left(\text{29b}\right)\end{array}$

[0094] The differential output current of the MOS differential pair is represented as follows: 18$\begin{array}{cc}\begin{array}{c}\Delta I_D=I_{\mathrm{D1}}-I_{\mathrm{D2}}=\left(\sqrt{I_{\mathrm{D1}}}-\sqrt{I_{\mathrm{D2}}}\right)\left(\sqrt{I_{\mathrm{D1}}}+\sqrt{I_{\mathrm{D2}}}\right)\\ =K_1\beta V_i\sqrt{\frac{2I_{\mathrm{SS}}}{K_1\beta }-V_i^2}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{K_1\beta }}\right)\end{array}& \left(30\right)\end{array}$

[0095] The non-linear term of the above formula, i.e.,

{square root}{square root over (K1β)}{square root}{square root over (2ISS/(K1β)−Vi2)}(={square root}{square root over (ID1)}+{square root}{square root over (ID2)})  (30a)

[0096] is caused by a common source voltage of the MOS differential pair. The common source voltage VS1 is represented as follows: 19$\begin{array}{cc}{V}_{\mathrm{S1}}=V_{\mathrm{CM1}}-V_{\mathrm{TH}}-\frac{1}{2}\sqrt{\frac{2I_{\mathrm{SS}}}{K_1\beta }-V_i^2}& \left(31\right)\end{array}$

[0097] In this formula, VCM1 designates a common mode voltage of input voltages. Non-linearity behavior of the MOS differential pair is caused by the variations in the common source voltage depending on the input voltages. Therefore, if the common source voltage of the MOS differential pair is kept constant, the MOS differential pair operates linearly.

[0098] Output voltages of respective transistors which constitute the MOS differential pair and each of which is coupled to a load transistor are represented as follows: 20$\begin{array}{cc}{V}_{\mathrm{O1}}=V_B-V_{\mathrm{TH}}-\sqrt{\frac{I_{\mathrm{D1}}}{K_2\beta }}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{K_1\beta }}\right)& \left(32\right)\\ V_{\mathrm{O2}}=V_B-V_{\mathrm{TH}}-\sqrt{\frac{I_{\mathrm{D2}}}{K_2\beta }}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{K_1\beta }}\right)& \left(33\right)\end{array}$

[0099] where, VB designates a gate bias voltage of a load transistor.

[0100] Therefore, a differential output voltage becomes as follows: 21$\begin{array}{cc}{V}_{\mathrm{O1}}-V_{\mathrm{O2}}=-\sqrt{\frac{K_1}{K_2}}{V}_i\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{K_1\beta }}\right)& \left(34\right)\end{array}$

[0101] Here, if K2/K1 is larger than 1, the MOS differential pair having transistor loads becomes an attenuator having an opposite output phase, and, if K2/K1 is smaller than 1, the MOS differential pair becomes an amplifier having an opposite output phase. As shown by the formula (34), the MOS differential pair having transistor loads becomes linear with respect to the differential output voltage.

[0102] FIG. 4 is a graph showing characteristics of output voltages of the MOS differential pair having transistor loads.

[0103] The common mode voltage of the output voltages becomes as follows: 22$\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{CM2}}=\frac{V_{\mathrm{o1}}+V_{\mathrm{o2}}}{2}=V_B-V_{\mathrm{TH}}-\sqrt{\frac{I_{\mathrm{D1}}}{K_2\beta }}-\sqrt{\frac{I_{\mathrm{D2}}}{K_2\beta }}\\ =V_B-V_{\mathrm{TH}}-\frac{1}{2}\sqrt{\frac{K_1}{K_2}}\sqrt{\frac{2I_{\mathrm{SS}}}{K_1\beta }-V_i^2}\\ =V_B-V_{\mathrm{TH}}-\sqrt{\frac{K_1}{K_2}}\left(V_{\mathrm{CM1}}-V_{\mathrm{TH}}-V_{\mathrm{S1}}\right)\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_{\mathrm{SS}}}{K_1\beta }}\right)\end{array}& \left(35\right)\end{array}$

[0104] That is, the common mode voltage of the differential output voltage of the MOS differential pair having transistor loads can be represented by using the common source voltage Vs1.

[0105] Next, consideration will be made on a MOS quadri-tail cell in which source electrodes of unit transistors M5 and M6 and source electrodes of transistors M7 and M8 whose transistor size ratios with respect to the unit transistor are K3 are commonly connected and driven by a constant current source I0. Assuming that a voltage ΔV is applied between gate electrodes of the transistors M5 and M6 and that a voltage VC is applied between the common gate of the transistors M7 and M8 and the input common mode voltage (VCM3), drain currents of the transistors M5, M6, M7 and M8 are represented as follows:

I D5 =β{V CM3 +(½)ΔV−VS2−VTH}2  (36)

I D6 =β{V CM3 −(½)ΔV−VS2−VTH}2  (37)

I D7 =I D8 =K 3 β(VCM3+VC−VS2−VTH)2  (38)

[0106] where, VS2 designates a common source voltage of the MOS quadri-tail cell.

[0107] Also, from the condition of the tail current, the following formula is obtained.

I D5 +I D6 +I D7 +I D8 =I 0   (39)

[0108] By substituting formulas (36) through (38) for the formula (39), it is possible to obtain a term (VCM3−VS2−VTH) as follows: 23$\begin{array}{cc}{V}_{\mathrm{CM3}}-V_{\mathrm{S2}}-V_{\mathrm{TH}}=\frac{-K_3{V}_c+\sqrt{\left(K_3+1\right)\frac{I_0}{2\beta }-\frac{K_3+1}{4}{\left(\Delta V\right)}^2-K_3{V}_c^2}}{K_3+1}& \left(40\right)\end{array}$

[0109] The differential output current ΔI of the MOS quadri-tail cell can be obtained as described in “Appendix 2” of a paper “MOS Linear and Square-Law Transconductance Amplifiers Consisting of a Source-Coupled Pair with Load Transistors and a Quadritail Cell Using Only N-Channel MOS Unit Transistors” (CAS98-41), Institute of Electronics, Information and Communication Engineers, Technical Report of Research Committee of Circuit and System, pp.17-24, July 1998. As described in this paper, the differential output current ΔI=ID5−ID6=2β(ΔV) (VCM3−VS2−VTH) can be represented as follows:

ΔI=ID5−ID6=2β(ΔV) (VCM3−VS2−VTH) 24 $$ Δ ⁢   ⁢ I = I D5 - I D6 = 2 ⁢ β ⁡ ( Δ ⁢   ⁢ V ) ⁢ ( V CM3 - V S2 - V TH ) = - 2 ⁢ K 3 ⁢ β ⁡ ( Δ ⁢   ⁢ V ) ⁢ V c + 2 ⁢ β ⁡ ( Δ ⁢   ⁢ V ) ( K 3 + 1 ) ⁢ I 0 2 ⁢ β - K 3 + 1 4 ⁢ ( Δ ⁢   ⁢ V ) 2 - K 3 ⁢ V c 2 K 3 + 1 ⁢ ( &LeftBracketingBar; Δ ⁢   ⁢ V &RightBracketingBar; ≤   ⁢ min ⁢ { 2 ⁢ I 0 β - 4 ⁢ V c 2 , - K 3 ⁢ V c + 2 ⁢ ( K 3 + 1 ) ⁢ I 0 β - 2 ⁢ K 3 ⁢ V c 2 K 3 + 2 } ) ( 41 )

[0110] From the formula (41), the condition that the MOS quadri-tail cell operates linearly becomes as follows: 25$\begin{array}{cc}-K_3{V}_c+\sqrt{\left(K_3+1\right)\frac{I_0}{2\beta }-\frac{K_3+1}{4}{\left(\Delta V\right)}^2-K_3{V}_c^2}=c\left(\mathrm{cons}\tan t\right)& \left(42\right)\end{array}$

[0111] Here, the differential output current becomes as follows: 26$\begin{array}{cc}\Delta I=\frac{2c\beta }{K_3+1}\left(\Delta V\right)& \left(43\right)\end{array}$

[0112] Also, the control voltage VC can be obtained from the following relation. 27$\begin{array}{cc}{V}_c=\frac{-K_{3}c+\sqrt{{K_3\left(K_3+1\right)}^2\frac{I_0}{2\beta }-\frac{{K_3\left(K_3+1\right)}^2}{4}{\left(\Delta V\right)}^2-K_3{c}^2}}{K_3\left(K_3+1\right)}& \left(44\right)\end{array}$

[0113] For example, when C2=(K3+1)2I0(4β), the control voltage VC becomes as follows: 28$\begin{array}{cc}{V}_c=-\frac{1}{2}\sqrt{\frac{I_0}{\beta }}+\sqrt{\frac{I_0}{K_3\beta }-\frac{1}{K_3}{\left(\Delta V\right)}^2}& \left(45\right)\end{array}$

[0114] As shown in FIG. 3, by cascade-coupling the MOS differential pair having transistor loads and the MOS quadri-tail cell, it is possible to realize a linear transconductance amplifier. The gate voltages of the transistors M5, M6 and M7 become VO1, VO2 and (VCM2+VC), respectively. If the value (VCM2+VC) becomes a constant value, it is possible to greatly simplify the structure of a gate bias circuit for producing the control voltage VC. Here, ΔV=VO1−VO2, and VCM3=VCM2. The value of (VCM2+VC) is represented as follows: 29$\begin{array}{cc}{V}_{\mathrm{CM2}}+V_C=V_B-V_{\mathrm{TH}}-\frac{1}{2}\sqrt{\frac{K_1}{K_2}}\sqrt{\frac{2I_{\mathrm{SS}}}{K_1\beta }-V_i^2}+\frac{-K_{3}c+\sqrt{{K_3\left(K_3+1\right)}^2\frac{I_0}{2\beta }-\frac{{K_3\left(K_3+1\right)}^2}{4}{\left(\Delta V\right)}^2-K_3{c}^2}}{K_3\left(K_3+1\right)}=d\left(\mathrm{constant}\right)& \left(46\right)\end{array}$

[0115] Therefore, the requirement for linear operation of the circuit of FIG. 3 is that term or terms which are functions of the input voltage Vi become zero, and the following relation is obtained. 30$\begin{array}{cc}{V}_{\mathrm{CM2}}+V_C=V_B-V_{\mathrm{TH}}-\frac{c}{K_3+1}=d\left(\mathrm{constant}\right)& \left(47\right)\end{array}$

[0116] From the condition that the formula (46) and the formula (47) become equal to each other, the following relations are obtained.

K 3 =1  (48)

[0117] 31 $$ I 0 β = I SS K 2 ⁢ β + c 2 2 ( 49 )

[0118] Also, when Vi=0 in the formula (46), the formula (47) is satisfied even when VC=0, and the following relations can be obtained. 32$\begin{array}{cc}d=V_B-V_{\mathrm{TH}}-\sqrt{\frac{I_{\mathrm{SS}}}{2K_2\beta }}& \left(50\right)\\ c=4\sqrt{\frac{I_{\mathrm{SS}}}{2K_2\beta }}=2\sqrt{\frac{2I_{\mathrm{SS}}}{K_2\beta }}& \left(51\right)\end{array}$

[0119] By substituting the formula (51) for the formula (49), the following relation is obtained. 33$\begin{array}{cc}{I}_0=2\frac{I_{\mathrm{SS}}}{K_2}& \left(52\right)\end{array}$

[0120] FIG. 5 shows drain currents of respective transistors constituting the quadri-tail cell obtained in this way. In FIG. 5, ΔV=VO1−VO2.

[0121] Both the drain currents ID5 and ID6 the transistors M5 and M6 are currents which satisfy the square-law. Therefore, the differential output current becomes linear, and the circuit of FIG. 3 constitutes a MOS linear transconductance amplifier. Also, both the sum of the drain currents ID5 and ID7 and the sum of the drain currents ID6 and ID8 show straight lines. Therefore, the respective drain currents are obtained by the following formulas. 34$\begin{array}{cc}{I}_{\mathrm{D5}}=\frac{\beta }{4}{\left(\Delta V-\sqrt{\frac{I_0}{\beta }}\right)}^2\left(\&LeftBracketingBar;\Delta V\&RightBracketingBar;\le \sqrt{\frac{I_0}{2\beta }}\right)& \left(53\right)\\ I_{\mathrm{D6}}=\frac{\beta }{4}{\left(\Delta V+\sqrt{\frac{I_0}{\beta }}\right)}^2\left(\&LeftBracketingBar;\Delta V\&RightBracketingBar;\le \sqrt{\frac{I_0}{2\beta }}\right)& \left(54\right)\\ I_{\mathrm{D7}}=I_{\mathrm{D8}}=\frac{1}{4}\left\{I_0+{\beta \left(\Delta V\right)}^2\right\}\left(\&LeftBracketingBar;\Delta V\&RightBracketingBar;\le \sqrt{\frac{I_0}{2\beta }}\right)& \left(55\right)\end{array}$

[0122] Thus, an effective tail current of the two transistors constituting the differential pair of the quadri-tail cell becomes as follows: 35$\begin{array}{cc}{I}_{\mathrm{D5}}+I_{\mathrm{D6}}=\frac{1}{2}\left\{I_0+{\beta \left(\Delta V\right)}^2\right\}\left(\&LeftBracketingBar;\Delta V\&RightBracketingBar;\le \sqrt{\frac{I_0}{2\beta }}\right)& \left(56\right)\end{array}$

[0123] The circuit structure can be most simplified when K1=1, K2=1, K3=1 and Iss=I0. In such case, the value of the constant c becomes as follows: 36$\begin{array}{cc}c=2\sqrt{\frac{I_0}{\beta }}& \left(57\right)\end{array}$

[0124] Also, in this case, the following relations are obtained. 37$\begin{array}{cc}d=V_{\mathrm{CM2}}+V_C=V_B-V_{\mathrm{TH}}-2\sqrt{\frac{I_0}{\beta }}& \left(58\right)\\ V_C=\frac{1}{2}\left\{-\sqrt{\frac{I_0}{\beta }}+\sqrt{\frac{I_0}{\beta }-{\left(\Delta V\right)}^2}\right\}& \left(59\right)\end{array}$

[0125] The differential output current of the linear transconductance amplifier shown in FIG. 3 is represented as follows: 38$\begin{array}{cc}\Delta I=I_{\mathrm{D5}}-I_{\mathrm{D6}}=-\sqrt{\beta I_0}{V}_i\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_0}{2\beta }}\right)& \left(60\right)\end{array}$

[0126] An operation range of such linear transconductance amplifier shown by the relation |Vi|≦{square root}{square root over ( )}{I0/(2β)} becomes equal to the operation range of the MOS differential pair having transistor loads.

[0127] Transconductance of such linear transconductance amplifier becomes as follows: 39$\begin{array}{cc}\frac{d\left(\Delta V\right)}{d{V}_i}=-\sqrt{\beta I_0}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_0}{2\beta }}\right)& \left(61\right)\end{array}$

[0128] The common source voltage VS2 can be obtained by using the formula (39) as follows: 40$\begin{array}{cc}{V}_{\mathrm{S2}}=\frac{V_1+V_2}{2}-V_{\mathrm{TH}}-\frac{1}{2}\sqrt{\frac{I_0}{\beta }}& \left(62\right)\end{array}$

[0129] Therefore, an added voltage or a sum of the input voltages can be obtained. As shown by the formula (62), the common source voltage VS2 includes an offset voltage −VTH−(½){square root}{square root over ( )}(I0/β) which is a constant voltage. FIG. 6 shows a circuit in which such offset voltage can be removed to obtain the added voltage (V1+V2)/2. In the circuit of FIG. 6, the common source voltage VS2 is level-shifted by a unit transistor which is diode-coupled and which is driven by a constant current source I0.

[0130] The above-mentioned voltage subtractor/adder circuit can produce linear subtraction and addition outputs. However, in some cases, it is also preferable to provide a voltage subtractor/adder circuit which has more simple structure and smaller circuit scale although linearity performance may be slightly deteriorated. FIG. 7 shows a simplified voltage subtractor/adder circuit as another embodiment of the present invention.

[0131] The circuit of FIG. 7 comprises a level-shifting circuit or a level shifter including a MOS transistor M3, and a MOS differential pair including MOS transistors M1 and M2. As a voltage subtractor circuit, the circuit of FIG. 7 provides an output voltage having linearity corresponding to that of the usual MOS differential pair, as shown by the formula (19). Also, as a voltage adder circuit, the circuit of FIG. 7 provides an output voltage having linearity equivalent to that of the usual MOS differential pair as can be seen from the formula (31) and as shown by the curve of VCM2 in FIG. 4. The output voltage of the voltage adder circuit becomes as follows: 41$\begin{array}{cc}{V}_0=\frac{V_1+V_2}{2}+\frac{1}{2}\sqrt{\frac{I_0}{\beta }}-\frac{1}{2}\sqrt{\frac{I_0}{\beta }-V_i^2}& \left(63\right)\end{array}$

[0132] From the formula (63), when the differential input voltage |Vi| is relatively small, this formula can be approximated to the following: 42$\begin{array}{cc}{V}_0\approx \frac{V_1+V_2}{2}& \left(64\right)\end{array}$

[0133] Also, as can be seen from the formula (63) and as shown by the curve of VCM2 in FIG. 4, the output voltage of the voltage adder circuit becomes large as the differential input voltage |Vi| becomes large.

[0134] Next, an explanation will be made on a method of constituting a MOS differential pair which has linear transconductance and which can be used for realizing a voltage adder circuit and/or a voltage subtractor circuit. FIG. 8 shows a MOS differential amplifier circuit including such MOS differential pair.

[0135] In the circuit of FIG. 8, assuming that a transconductance parameter of each of the transistors M1 and M2 is β, a common source voltage Vs' of the MOS differential pair is represented as follows: 43$\begin{array}{cc}\begin{array}{cc}{V}_S^{\prime }=V_{\mathrm{CM}}-V_{\mathrm{TH}}-\frac{1}{2}\sqrt{\frac{2I_0}{\beta }-V_i^2}& \left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_0}{\beta }}\right)\end{array}& \left(65\right)\end{array}$

[0136] where, VCM is a common mode voltage of input voltages, and represented by the following formula: 44$\begin{array}{cc}{V}_{\mathrm{CM}}=\frac{V_1+V_2}{2}& \left(66\right)\end{array}$

[0137] In this formula, V1 and V2 designate gate voltages of the transistors M1 and M2, respectively.

[0138] In the formula (65), Vi designates a differential input voltage of the MOS differential pair, and Vi=V1−V2. Therefore, the common source voltage Vs' of the MOS differential pair becomes high according to an increase in the differential input voltage Vi. When the common source voltage Vs' of the MOS differential pair varies depending on the value of the differential input voltage Vi, the MOS differential pair does not operate linearly. That is, when the common source voltage Vs' becomes constant with respect to the common mode voltage VCM, the MOS differential pair operates linearly. Here, when the tail current of the MOS differential pair is increased according to an increase in the differential input voltage Vi, the gate-source voltage of each of the transistors M1 and M2 becomes large in accordance with an increase in the differential input voltage Vi. Therefore, in such case, it is possible to cancel a voltage raise in the common source voltage Vs' according to an increase in the differential input voltage Vi, and to make the common source voltage Vs' constant with respect to the common mode voltage VCM. In this manner, an operational amplifier A, transistors M3, M4 and M5 constitute a feedback loop, and function to keep the common source voltage Vs' constant with respect to the common mode voltage VCM. Therefore, the MOS differential pair shown in FIG. 8 operates linearly.

[0139] As mentioned above, by changing the tail current for driving the MOS differential pair depending on the differential input voltage Vi such that the common source voltage Vs' becomes constant with respect to the common mode voltage VCM, it is possible to realize the MOS differential pair which operates linearly.

[0140] In such case, the common source voltage Vs of the MOS differential pair is represented as follows: 45$\begin{array}{cc}{V}_S=V_{\mathrm{CM}}-V_{\mathrm{TH}}-\sqrt{\frac{I_0}{2\beta }}& \left(67\right)\end{array}$

[0141] Also, the tail current Iss driving the MOS differential pair becomes as follows: 46$\begin{array}{cc}{I}_{\mathrm{SS}}=I_{D5}=I_{D1}+I_{D2}=I_0+\frac{1}{2}\beta V_i^2& \left(68\right)\end{array}$

[0142] Therefore, it is possible to realize an adaptive-biasing differential pair and to realize a CMOS differential amplifier circuit having linear transconductance. Also, theoretically, an input voltage range for linear operation becomes infinite, if the tail current Iss is not limited.

[0143] The differential output current ΔI of the linear transconductance amplifier shown in FIG. 8 becomes as follows:

ΔI=ID5−ID6=−{square root}{square root over (βI0)}Vi  (69)

[0144] Also, the transconductance becomes as follows: 47$\begin{array}{cc}\frac{d\left(\Delta V\right)}{d{V}_i}=-\sqrt{\beta I_0}& \text{(70a)}\end{array}$

[0145] As a circuit for obtaining the common mode voltage VCM, there is known a voltage adder circuit shown in FIG. 9, for example. Also, when an input impedance is allowed to become relatively low, it is possible to obtain the common mode voltage VCM from a coupling point of two resistors coupled in series.

[0146] As shown in FIG. 10, it is also possible to use a level shifter to level-shift the common source voltage Vs. When the differential input voltage is applied within a range +/−Vi and the center of the differential input voltage +/−Vi is the common mode voltage VCM which is a constant voltage, the voltage adder circuit shown in FIG. 9 is not required.

[0147] FIG. 11 shows a MOS differential amplifier circuit according to still another embodiment of the present invention.

[0148] In an adaptive-biasing differential pair, it is required that the sum of currents flowing through the transistors M1 and M2 constituting a MOS differential pair becomes a current having the square-law characteristic as shown in the formula (68). Therefore, as shown in FIG. 11, it is possible to supply or inject a drain current ID3 of the transistor M3 into a constant current source IB. An operational amplifier A and the transistor M3 constitute a feedback loop, and function to keep the common source voltage Vs constant with respect to the common mode voltage VCM. Therefore, the sum of currents flowing through the transistors M1 and M2 becomes as follows: 48$\begin{array}{cc}\begin{array}{cc}{I}_B-I_{D3}=I_{D1}+I_{D2}=I_0+\frac{1}{2}\beta V_i^2& \left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_B}{\beta }}\right)\end{array}& \text{(70b)}\end{array}$

[0149] Thus, it is also possible to realize an adaptive-biasing differential pair by using the circuit of FIG. 11, and to realize a CMOS differential amplifier circuit having a linear transconductance. Also, an input voltage range providing linear operation of the CMOS differential amplifier circuit is limited by the performance of the constant current source IB.

[0150] With reference to the drawings, more concrete examples of the MOS differential amplifier circuit will be described. FIG. 12 shows a MOS differential amplifier circuit having transistor loads.

[0151] In FIG. 12, assume that all transistors M1, M2, M3 and M4 have the same transistor size, and that the transconductance parameter is β. In such case, the common source voltage VS1 of the MOS differential pair can be represented as follows: 49$\begin{array}{cc}\begin{array}{cc}{V}_{S1}=V_{\mathrm{LS}}+V_{\mathrm{TH}}-\frac{1}{2}\sqrt{\frac{2I_0}{\beta }-V_i^2}& \left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_0}{\beta }}\right)\end{array}& \left(71\right)\end{array}$

[0152] where, VCM1 is a common mode voltage of input voltages and represented by the following formula: 50$\begin{array}{cc}{V}_{\mathrm{CM}1}=\frac{V_1+V_2}{2}& \left(72\right)\end{array}$

[0153] In this formula, V1 and V2 are gate voltages of the transistors M1 and M2, respectively. Also, V1−V2=Vi. Therefore, in a unity gain amplifier, a voltage VB, which is obtained by subtracting the common source voltage VS1 from the common mode voltage VCM1 and by level-shifting the subtracted voltage by VLS, becomes a common gate voltage of the transistors M3 and M4. That is, VB=VCM1−VS1+VLS becomes the common gate voltage of the transistors M3 and M4 and represented as follows:

[0154] 51 $$ V B =   ⁢ V CM1 - V S1 + V LS =   ⁢ V LS + V TH + 1 2 ⁢ 2 ⁢ I 0 β - V i 2 ( 73 )

[0155] Therefore, output voltages VO1 and VO2 can be obtained as follows: 52$\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{O1}}=V_B-V_{\mathrm{TH}}=\frac{I_{\mathrm{D1}}}{\beta }\\ =V_{\mathrm{LS}}+\frac{1}{2}\sqrt{\frac{2I_0}{\beta }-V_i^2}-\sqrt{\frac{1}{2}\left(\frac{I_0}{2}+\sqrt{\frac{2I_0}{\beta }-V_i^2}\right)}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_0}{\beta }}\right)\end{array}& \left(74a\right)\end{array}$53$\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{O2}}=V_B-V_{\mathrm{TH}}=\frac{I_{\mathrm{D2}}}{\beta }\\ =V_{\mathrm{LS}}+\frac{1}{2}\sqrt{\frac{2I_0}{\beta }-V_i^2}-\sqrt{\frac{1}{2}\left(\frac{I_0}{2}-\sqrt{\frac{2I_0}{\beta }-V_i^2}\right)}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_0}{\beta }}\right)\end{array}& \left(74b\right)\end{array}$

[0156] From the identity of (27), the following relation is obtained. 54$\begin{array}{cc}\sqrt{\frac{I_0}{2}+\sqrt{\frac{2I_0}{\beta }-V_I^2}}-\sqrt{\frac{I_0}{2}-\sqrt{\frac{2I_0}{\beta }-V_i^2}}=\sqrt{2}{V}_i& \left(75a\right)\end{array}$

[0157] Also, from the identity of (29), the following relation is obtained. 55$\begin{array}{cc}\sqrt{\frac{I_0}{2}+\sqrt{\frac{2I_0}{\beta }-V_i^2}}+\sqrt{\frac{I_0}{2}-\sqrt{\frac{2I_0}{\beta }-V_i^2}}=\sqrt{2}\sqrt{\frac{2I_0}{\beta }-V_i^2}& \left(75b\right)\end{array}$

[0158] Therefore, the output voltages VO1 and VO2 can be represented as follows: 56$\begin{array}{cc}{V}_{\mathrm{O1}}=V_{\mathrm{LS}}-\frac{V_i}{2}& \left(76a\right)\\ V_{\mathrm{O2}}=V_{\mathrm{LS}}-\frac{V_i}{2}& \left(76b\right)\end{array}$

[0159] Thus, the output voltages VO1 and VO2 behave linearly about an operating point having the DC voltage VLS. Therefore, a MOS differential amplifier circuit having opposite polarities is obtained. As an example of a practical circuit for obtaining a common mode voltage of input voltages, it is possible to use the adder circuit of FIG. 9 as it is.

[0160] As another method of obtaining a voltage having opposite polarity of the common source voltage, there is described a method in which a MOS differential pair composed of P-channel transistors is used. FIG. 13 shows an example of a circuit for realizing such method.

[0161] In FIG. 13, assume that a transconductance parameter of each P-channel transistor is βP (=μP(COX/2)(W/L)), and that a transconductance parameter of each N-channel transistor is βN (=μN(COX/2)(W/L)). In this case, a common source voltage VS1P of the MOS differential pair comprising P-channel transistors is represented as follows: 57$\begin{array}{cc}{V}_{\mathrm{S1P}}=V_{\mathrm{CM1}}+\&LeftBracketingBar;V_{\mathrm{THP}}\&RightBracketingBar;+\frac{1}{2}\sqrt{\frac{2I_0}{{\beta }_P}-V_i^2}\left(\&LeftBracketingBar;V_i\&RightBracketingBar;\le \sqrt{\frac{I_0}{{\beta }_p}}\right)& \left(77\right)\end{array}$

[0162] Therefore, in a unity gain amplifier, a voltage VB, which is obtained by subtracting the common mode voltage VCM1 from the common source voltage VS1 and by level-shifting the subtracted voltage by VLS, becomes a common gate voltage of the transistors M3 and M4. That is, VB=VS1P−VCM1+VLS becomes the common gate voltage of the transistors M3 and M4 and represented as follows:

[0163] 58 $$ V B =   ⁢ V S1P - V CM1 + V LS =   ⁢ &LeftBracketingBar; V THP &RightBracketingBar; + 1 2 = &LeftBracketingBar; V THP &RightBracketingBar; + 1 2 ⁢ 2 ⁢ I 0 β P - V i 2 ( 78 )

[0164] Therefore, output voltages VO1 and VO2 can be obtained as follows: 59$\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{O1}}=V_B-V_{\mathrm{THN}}-\sqrt{\frac{I_{\mathrm{D1}}}{{\beta }_N}}\\ =V_{\mathrm{LS}}+\&LeftBracketingBar;V_{\mathrm{THN}}\&RightBracketingBar;-V_{\mathrm{THN}}+\frac{1}{2}\sqrt{\frac{2I_0}{{\beta }_P}-V_i^2}-\\ \sqrt{\frac{1}{2}\left(\frac{I_0}{2}+\sqrt{\frac{2I_0}{{\beta }_N}-V_i^2}\right)}\end{array}& \left(79a\right)\\ \begin{array}{c}{V}_{\mathrm{O2}}=V_{\mathrm{LS}}-V_{\mathrm{THN}}-\sqrt{\frac{I_{\mathrm{D2}}}{{\beta }_N}}\\ =V_{\mathrm{LS}}+\&LeftBracketingBar;V_{\mathrm{THN}}\&RightBracketingBar;-V_{\mathrm{THN}}+\frac{1}{2}\sqrt{\frac{2I_0}{{\beta }_P}-V_i^2}-\\ \sqrt{\frac{1}{2}\left(\frac{I_0}{2}+\sqrt{\frac{2I_0}{{\beta }_N}-V_i^2}\right)}\end{array}& \left(79b\right)\end{array}$

[0165] When βN=βP, the output voltages VO1 and VO2 can be represented as follows: 60$\begin{array}{cc}{V}_{\mathrm{O1}}=V_B+\&LeftBracketingBar;V_{\mathrm{THN}}\&RightBracketingBar;-V_{\mathrm{THN}}-\frac{V_i}{2}& \left(80a\right)\\ V_{\mathrm{O2}}=V_B+\&LeftBracketingBar;V_{\mathrm{THN}}\&RightBracketingBar;-V_{\mathrm{THN}}+\frac{V_i}{2}& \left(80b\right)\end{array}$

[0166] Thus, the output voltages VO1 and VO2 behave linearly about an operating point having a DC voltage VLS+|VTHP|−VTHN. Therefore, a MOS differential amplifier circuit having opposite polarities is obtained.

[0167] In each of the MOS differential amplifier circuits mentioned above, a unity gain amplifier as a subtractor is required. In order to omit the unity gain amplifier, it is possible to make current outputs of the MOS differential amplifier circuit linear. FIG. 14 shows a MOS differential amplifier circuit which does not require using the unity gain amplifier.

[0168] In the MOS differential amplifier circuit of FIG. 14, the common source voltage VS1 of a MOS differential pair composed of P-channel transistors which are driven by a constant current source 2I0 is represented as follows: 61$\begin{array}{cc}{V}_B=V_{\mathrm{CM1}}+\left|V_{\mathrm{THP}}\right|+\sqrt{\frac{4I_0}{{\beta }_P}-V_i^2}\left(\left|V_i\right|\le \sqrt{\frac{2I_0}{{\beta }_P}}\right)& \left(81\right)\end{array}$

[0169] P-channel transistors M7 and M8 and constant current sources I0 constitute source follower transistors, and function to level-shift input voltages by a voltage VF. Here, VF is represented as follows: 62$\begin{array}{cc}{V}_F=\sqrt{\frac{I_0}{{\beta }_P}}+\left|V_{\mathrm{THP}}\right|& \left(82\right)\end{array}$

[0170] In a quadri-tail cell comprising N channel transistors M3, M4, M5 and M6 which are driven by a constant current source 4I0, the input voltages V1 and V2 are level-shifted by the voltage VF and are applied to the gate electrodes of the transistors M3 and M4, respectively. The common source voltage VS1 of the transistors M1 and M2 is directly applied to the commonly coupled gates of the transistors M5 and M6. Therefore, the following formulas are obtained.

I D3 βN(V1+VF−VS2−VTHN)2  (83)

I D4 =βN(V2+VF−VS2−VTHN)2  (84)

I D5 =I D6 =β N (VS1−VS2−VTHN)2  (85)

[0171] where, ID3, ID4, ID5, ID6 and I0 satisfy the following relation:

ID3+ID4+ID5+ID6=4I0  (86)

[0172] Therefore, the differential output current ΔI becomes as follows:

ΔI =(ID3+ID5)−(ID4+ID6)−ID3−ID4=2βNVi(VCM1+VF−VS2−VTHN)  (87)

[0173] Here, by substituting the formulas (83)-(85) for the formula (86), it is possible to obtain (VCM1+VF−VS2−VTHN) as follows:

V CM1 +V F −V S2 −V THN 63 $$ V CM1 + V F - V S2 - V THN = 2 ⁢ I 0 β P -   4 ⁢ I 0 β P - V i 2 +   16 ⁢ I 0 β N -   4 ⁢ I 0 β P - V i 2 + I 0 β P ⁢   4 ⁢ I 0 β P - V i 2 4 ( 88 )

[0174] Assuming βN=βP, the formula (88) becomes as follows: 64$\begin{array}{cc}{V}_{\mathrm{CM1}}+V_F-V_{\mathrm{S2}}-V_{\mathrm{THN}}=\sqrt{\frac{I_0}{{\beta }_P}}& \left(89\right)\end{array}$

[0175] Therefore, in such case, the formula (87) becomes as shown below, and it can be seen that the MOS differential amplifier circuit of FIG. 14 operates linearly. 65$\begin{array}{cc}\begin{array}{c}\Delta I=2{\beta }_N{V}_i\sqrt{\frac{I_0}{{\beta }_P}}\\ =2\sqrt{B_N{I}_0{V}_i}\end{array}& \left(90\right)\end{array}$

[0176] Also, from the formula (90), it can be seen that transconductance of the MOS differential amplifier circuit is determined depending on the drive current I0. Therefore, by changing current values of constant current sources I0, 2I0, 4I0 simultaneously, it is possible to set the transconductance to a desired value.

[0177] Since the circuit of FIG. 14 operates in A-class, output currents I+ and I− are represented as follows: 66$\begin{array}{cc}{I}^{+}=I_{\mathrm{D3}}+I_{\mathrm{D5}}={}^{2}I_0+\sqrt{B_N{I}_0}{V}_i& \left(91\right)\\ I^{-}=I_{\mathrm{D3}}+I_{\mathrm{D5}}={}^{2}I_0-\sqrt{B_N{I}_0}{V}_i& \left(92\right)\end{array}$

[0178] Therefore, voltage outputs are obtained via load resistors RL through which the output currents shown above flow.

[0179] As shown in FIG. 15, it is also possible to use source follower transistors M7 and M8 having different conductivity type than that of the source follower transistors used in the circuit of FIG. 14. In this case, when the threshold voltage VTHN of the N-channel transistor and the threshold voltage VTHP of the P-channel transistor differ from each other, it is necessary to set a current value I1 of a constant current source such that the value of voltage shift by the source follower transistors M7 and M8 becomes equal to the value of voltage shift in the circuit of FIG. 14. Also, with respect to an effective mobility (μN) of an N-channel transistor and an effective mobility (μP) of a P-channel transistor, there is a relation μN>μP, and usually both differ from each other by approximately three times. Therefore, in order to match DC transfer characteristics of both transistors with each other, a gate ratio (W/L) of the P-channel transistor is made larger than that of the N-channel transistor depending on how smaller the effective mobility (μP) of the P-channel transistor is when compared with that of the N-channel transistor. Alternatively, it is possible to enlarge the tail current to match DC transfer characteristics of both transistors with each other. Therefore, in general, frequency characteristics of the MOS differential amplifier circuit are limited depending on frequency characteristics of such P-channel transistors.

[0180] FIG. 16 shows a circuit which uses two MOS differential amplifier circuits using transistors having different conductivity types.

[0181] In the circuit of FIG. 16, level shift circuits are constituted of transistors MN7 and MP7 which share respective common source voltages and which are driven by constant current sources. Similarly to the circuit shown above, transconductance of the MOS differential amplifier circuit is determined depending on the drive current I0. Therefore, by changing current values of constant current sources I0, 3I0, 4I0 simultaneously, it is possible to set the transconductance to a desired value.

[0182] Also, by doubling the size of each of the transistors MN7 and MP7, both the drive current of the transistors MN1, MN2 and MN7 and the drive current of the transistors MP1, MP2 and MP7 vary from 3I0 to 4I0, and both the drive current of the transistor MN7 and the drive current of the transistor MP7 vary from I0 to 2I0. The circuit of FIG. 16 has output terminals both on the side of a power supply voltage and on the side of the ground. Therefore, the circuit of FIG. 16 is preferable for use in an application in which an AB-class output circuit is to be driven by the circuit.

[0183] The present invention provides various advantageous effects.

[0184] First, according to the present invention, it is possible to realize a MOS differential amplifier circuit which has both linear voltage subtraction outputs and linear voltage addition outputs. Thereby, it is possible to realize a linear voltage subtractor/adder circuit. The reason why such circuit is realized is as follows. That is, the tail current of a MOS source-coupled differential pair is driven by using an output current of a squaring circuit which provides an output current proportional to an input voltage. Thereby, it is possible to make the common source voltage constant with respect to an input common mode voltage, and to make differential output current linear.

[0185] Second, according to the present invention, it is also possible to realize a linear voltage subtractor/adder circuit having a simplified structure and a small circuit scale if linearity requirement is not very strict.

[0186] Third, according to the present invention, it is possible to completely linearize the outputs of a MOS source-coupled differential pair. Thereby, it becomes possible to realize an ideal linear transconductance amplifier. This is because, by controlling the tail current such that the common source voltage of the MOS differential pair becomes constant with respect to the input common mode voltage, it becomes possible to realize a completely linear operation.

[0187] Fourth, according to the present invention, it is possible to expand an input voltage range within which linear transconductance is obtained. This is because, in the present invention, a tail current driving a MOS differential pair is made variable.

[0188] Fifth, according to the present invention, it is possible to completely linearize output voltages of a MOS differential pair. Thereby, it becomes possible to realize an ideal linear transconductance amplifier. The reason for this is as follows. The output currents of a MOS source-coupled differential pair are compressed to their square-roots, and outputted as a differential output. In such case, the following identity is obtained. 67$\begin{array}{cc}\sqrt{a+\sqrt{2x}\sqrt{1-\frac{x^2}{2}}}-\sqrt{a-\sqrt{2x}\sqrt{1-\frac{x^2}{2}}}=\sqrt{2x}& \left(93\right)\end{array}$

[0189] This formula shows that such differential output behaves linearly. Therefore, MOS transistors are used as loads of a MOS differential pair to provide output voltages. Also, a voltage is obtained by subtracting the common source voltage of a MOS differential pair from the input common mode voltage, and this voltage is applied to the commonly coupled gates of the MOS load transistors. Thereby, it becomes possible to realize an A-class operation, and to obtain a completely linear output voltage.

[0190] Sixth, according to the present invention, it is possible to independently adjust the transconductance of a MOS differential amplifier circuit having linear transconductance. Thereby, it becomes possible to realize a MOS differential amplifier circuit in which transconductance is tunable. This is because, in a MOS differential amplifier circuit, constant current sources are required for driving a MOS differential pair and a MOS quadri-tail cell which constitute the MOS differential amplifier circuit. By controlling the current values of the constant current sources, it becomes possible to adjust or change the transconductance.

[0191] In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative sense rather than a restrictive sense, and all such modifications are to be included within the scope of the present invention. Therefore, it is intended that this invention encompasses all of the variations and modifications as fall within the scope of the appended claims.

Claims

1. A voltage subtractor/adder circuit comprising: a differential pair having first and second MOS transistors, gate electrodes of said first and second MOS transistors forming input terminals for receiving an input differential voltage, drain electrodes of said first and second MOS transistors forming output terminals for outputting a subtraction output signal, and source electrodes of said first and second MOS transistors being commonly coupled to form an output terminal for addition output voltage; and wherein the sum of currents flowing through said first and second MOS transistors increases in proportion to the square of said input differential voltage.

2. A voltage subtractor/adder circuit as set forth in claim 1, further comprising a level shifter for level-shifting said addition output voltage from said source electrodes which are commonly coupled.

3. A voltage subtractor/adder circuit comprising: a differential pair having first and second MOS transistors, gate electrodes of said first and second MOS transistors forming input terminals for receiving an input differential voltage, drain electrodes of said first and second MOS transistors forming output terminals for outputting a subtraction output signal, and source electrodes of said first and second MOS transistors being commonly coupled to form an output terminal for addition output voltage; and a constant current source which drives said differential pair.

4. A voltage subtractor/adder circuit as set forth in claim 3, further comprising a level shifter for level-shifting said addition output voltage from said source electrodes which are commonly coupled.

5. A MOS differential amplifier circuit comprising: a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of said first and second MOS transistors being commonly coupled and being driven by a current source; and wherein current value of said current source being controlled such that a difference voltage between a common mode voltage and a common source voltage of said first and second MOS transistors becomes a constant value.

6. A MOS differential amplifier circuit as set forth in claim 5, further comprising a level shifter for level-shifting said common source volage of said first and second MOS transistors.

7. A MOS differential amplifier circuit comprising: a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of said first and second MOS transistors being commonly coupled and being driven by a constant current source; and wherein a current is injected into said constant current source such that a difference voltage between a common mode voltage and a common source voltage of said first and second MOS transistors becomes a constant voltage.

8. A MOS differential amplifier circuit comprising: a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of said first and second MOS transistors being commonly coupled and being driven by a constant current source; and third and fourth MOS transistors which are load transistors of said first and second MOS transistors, respectively, and whose gates receive the sum of a predetermined constant voltage and a voltage obtained by subtracting a common source voltage of said first and second MOS transistors from a common mode voltage.

9. A complementary MOS differential amplifier circuit comprising: a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of said first and second MOS transistors being commonly coupled and being driven by a first constant current source; a MOS quadri-tail cell having third, fourth, fifth and sixth MOS transistors which have different conductivity type from that of said first and second MOS transistors, source electrodes of said third, fourth, fifth and sixth MOS transistors being commonly coupled and being driven by a second constant current source; wherein gate electrodes of said fifth and sixth MOS transistors being coupled to a common source electrode of said first and second MOS transistors, drain electrodes of said fifth and third MOS transistors being commonly coupled and forming one output terminal, drain electrodes of said sixth and fourth MOS transistors being commonly coupled and forming the other output terminal, and gate electrodes of said first and second MOS transistors and gate electrodes of said third and fourth MOS transistors receiving input voltages.

10. A complementary MOS differential amplifier circuit as set forth in claim 9, further comprising level shifters for level-shifting said input voltages before being applied to said gate electrodes of said first and second MOS transistors and said gate electrodes of said third and fourth MOS transistors.

11. A complementary MOS differential amplifier circuit as set forth in claim 9, wherein the ratio of the current value of said first constant current source and transconductance parameter of said first and second MOS transistors is approximately half of the ratio of the current value of said second constant current source and transconductance parameter of said third, foruth, fifth and sixth MOS transistors.

12. A complementary MOS differential amplifier circuit comprising first and second MOS differential amplifier circuits each of which is the MOS differential amplifier circuit as set forth in claim 6, wherein corresponding MOS transistors of said first and second MOS differential amplifier circuits have mutually different conductivity types and wherein said first and second MOS differential amplifier circuits are coupled parallel to form a differential input pair.

13. A complementary MOS differential amplifier circuit as set forth in claim 9, wherein transconductance of said MOS differential amplifier circuit is adjustable by controlling current values of at least one of said first and second constant current sources.