BRIEF DESCRIPTION OF THE DRAWINGS
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
FIG. 1 is a block diagram illustrating a prior art complex polar modulator with direct phase and amplitude modulation;
FIG. 2 is a block diagram illustrating a single chip polar transceiver radio incorporating an all-digital local oscillator based transmitter and receiver;
FIG. 3 is a block diagram illustrating a single chip polar transmitter based on a DCO and digitally controlled power amplifier (DPA) circuits;
FIG. 4 is a diagram illustrating spectral replicas of a modulating signal and associated filtering through a zero-order hold;
FIG. 5 is a block diagram illustrating co-linearization of a DRP based transmitter and RF power amplifier;
FIG. 6 is a graph illustrating the degradation in EVM in an EDGE transmitter as a function of RF power amplifier compression;
FIG. 7 is a graph illustrating the degradation in modulated spectrum at 400 kHz offset in an EDGE transmitter as a function of RF power amplifier compression;
FIG. 8 is a block diagram illustrating the general linearization mechanism of the present invention;
FIG. 9 is a block diagram illustrating a first embodiment of the linearization mechanism of the present invention implemented in a DRP based GSM/EDGE polar transmitter;
FIG. 10A is a graph illustrating the impact of uncompensated distortions on the close-in modulation spectrum of an EDGE transmitter;
FIG. 10B is a graph illustrating the impact of using an LUT based predistortion scheme on the close-in modulation spectrum of an EDGE transmitter;
FIG. 10C is a graph illustrating the impact of using a polynomial predistortion scheme on the close-in modulation spectrum of an EDGE transmitter;
FIG. 10D is a graph illustrating the impact of using a closed loop proportional/integral (PI) compensation scheme on the close-in modulation spectrum of an EDGE transmitter;
FIG. 11 is a flow diagram illustrating the predistortion LUT update method of the present invention;
FIG. 12 is a diagram illustrating the structure of a basic EDGE burst;
FIG. 13 is a diagram illustrating the structure of an actual example EDGE burst with EDGE modulation and up/down power ramps;
FIG. 14 is a diagram illustrating the second embodiment of the linearization mechanism of the present invention implemented in a DRP based GSM/EDGE polar transmitter;
FIG. 15 is a flow diagram illustrating the predistortion calibration method of the present invention;
FIG. 16 is a diagram illustrating an example predistortion self-calibrating training sequence;
FIG. 17 is a flow diagram illustrating a first quasi-closed loop predistortion calibration method of the present invention; and
FIG. 18 is a flow diagram illustrating a second quasi-closed loop predistortion calibration method of the present invention.
Patent Application
20070190952
