Patent Application
20070156386
This invention relates to the art of computer system emulation and, more particularly, to the emulation of a Central Processing Unit and Input/Output system in which the legacy hardware design includes paging, segmentation, or an associative memory mechanism for mapping of a large virtual memory space to a smaller real or physical memory space.
Users of obsolete mainframe computers running a proprietary operating system may have a very large investment in proprietary application software and, further, may be comfortable with using the application software because it has been developed and improved over a period of years, even decades, to achieve a very high degree of reliability and efficiency.
As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the proprietary operating systems of powerful older computers such that the manufacturers of the older computers can provide new systems which allow the users to continue to use their highly-regarded proprietary software by emulating the older computer.
Accordingly, computer system manufacturers are developing such emulator systems for the users of their older systems, and the emulation process used by a given system manufacturer is itself subject to ongoing refinement and increases in efficiency and reliability.
Some historic computer systems now being emulated by software running on “commodity” processors have achieved performance which is nearly equal to that provided by legacy hardware system designs. An example of such hardware emulation is the Bull HN Information Systems (descended from General Electric Computer Department and Honeywell Information Systems) DPS9000 system which is being emulated by a software package internally called “HELIOS” running on a Bull NovaScale system which is based upon an Intel Itanium 2 Central Processor Unit. The 64-bit Itanium Intel processor is used to emulate the Bull DPS 9000 36-bit memory space and the GCOS 8 instruction set of the DPS 9000. Within the memory space of the emulator, the 36-bit word of the DPS 9000 is stored right justified (least significant bits) in the least significant 36 bits of the “host” (Itanium) 64-bit word. The upper 28 bits of the 64-bit word are typically zero for “legacy” code. Sometimes, certain specific bits in the upper 28 bits of the containing word are used as flags or for other temporary purposes, but in normal operation these bits are usually zero and in any case are always viewed by older programs in the “emulated” view of the world as being non-existent. That is, only the emulation program itself uses these bits.
In the design of the emulator system careful attention is typically devoted to ensuring exact duplication of the legacy hardware behavior so that application programs will run without change and without recompilation. Exact duplication of legacy operation is typically a requirement in order to achieve exactly equivalent results during execution.
To this end, the emulation program for the Central Processor Unit, and also any emulation of the Input/Output system typically includes the processing typically found in the legacy hardware for segmentation, paging and any associative memory processing. This mechanism is that which translates the “virtual address” seen by the application program from the user's point of view into a “real address” which is actually used to directly address the memory system hardware. In most modern computer systems the virtual program visible address space is larger than the real memory space actually available on the computer system.
When the emulation software is itself run under another operating system, such as Linux, the higher level operating system and the underlying hardware it uses itself performs its own functions of segmentation, paging or the implementation of associative memory. This results in the emulation software emulating segmentation, paging and associative memory processing of the legacy system, and then the upper level operating system which is running the emulated system also doing its own segmentation, paging and utilization of an associative memory.
The present invention is directed to removing the unnecessary manipulation of the virtual address by the emulation software system which decreases the host machine cycles required for emulation of each legacy instruction and thus potentially significantly improving the overall performance of the emulated system.
It is therefore a broad object of this invention to improve performance of an emulator system by modifying the legacy system's virtual memory system in a manner such that the legacy system's segments and the pages making up those segments are stored linearly in the host system's virtual memory space, thus allowing removal of the paging activity from the requirements of the optimized emulation system software. It is a second broad object of the invention to retain the page and segmentation based reference tables for use by un-optimized system software such that not all pieces of the system software need to be modified to utilize the optimized methods.
Briefly, these and other objects of the invention are achieved by an overall approach and mechanisms to support that approach which support a memory structure that eliminates the need for paging actions to be a part of the emulated legacy memory system. A first part of the mechanism is accomplished by placing in linear virtual memory space on the emulation host system all the segments that are a part of a program to be run. A second optional part of the mechanism is to “wire” all emulated memory system data for that program so that all memory system data is always present in the host system's virtual address space. This eliminates the need for any host system paging which may cause unpredictable delays that may be unacceptable to performance in an emulated central processing unit. This also eliminates the hazard of having the host system paging and memory management system remove pieces of the legacy system's memory space from the host system's real memory, which could cause unacceptable delays in processing for emulation of the legacy system's Input/Output system, or prevent a timely response by the emulated legacy Central Processor Unit response to time critical requests.
It is a second part of the invention to implement the linearization of the segments by placing the pages within the segment in sequential linear address space, but to retain the underlying paging mechanisms which reference and manage these pages. This approach allows the legacy operating system, which may be large and complex, to continue to view the segments as a collection of non-linear pages within the normal and historic memory management system, while allowing any chosen pieces of the software or the software emulator itself to not use the paging mechanism and achieve a potential increase in performance. This approach allows the “old” software and any pieces of the operating system from the past to continue to work properly.
There are at least three approaches to achieving the placement of pages within a segment into a linear arrangement. The first approach is when any segment is created to ensure that the pages are placed in linear order at the time the segment is created. This approach may not be easily accomplished within the legacy operating system especially since it requires that a hole of contiguous pages be found in a potentially busy memory system, and so an alternative approach may be needed. A second approach is to create the segment with non-linear pages, and then after the segment is totally in memory to identify a block of real memory for final linear placement of the pages within the segment, and interchange the pages currently within that space with the desired pages until all pages for the segment in question are now linear. This may not be possible instantaneously if some of the pages to be moved are wired or locked in place for I/O operations, or other reasons.
A third approach is to create a space within the legacy system's virtual address space that is reserved only for linear segments, and to manage that space separately. With the large memory spaces available on modern commodity processors this may be the most common and efficient approach.
The subject matter of the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, may best be understood by reference to the following description taken in conjunction with the subjoined claims and the accompanying drawing of which:
While the principles of the invention have now been made clear in an illustrative embodiment, there will be immediately obvious to those skilled in the art many modifications of structure, arrangements, proportions, the elements, materials, and components, used in the practice of the invention which are particularly adapted for specific environments and operating requirements without departing from those principles.
The target operating system reference space 15 also contains suitable information about the interconnection and interoperation among the various target system elements and components and a complete implementation in software of the target system operating system commands which includes information on the steps the host system must take to “execute” each target system instruction in a program originally prepared to run on a physical machine using the target system operating system. It can be loosely considered that, to the extent that the target system 1 can be said to “exist” at all, it is in the target operating system reference space 15 of the host system memory 12. Thus, an emulator program running on the host system 2 can replicate all the operations of a legacy application program written in the target system operating system as if the legacy application program were running on a physical target system.
In a current state-of-the-art example chosen to illustrate the invention, a 64-bit Intel Itanium series processor is used to emulate the Bull DPS 9000 36-bit memory space and the instruction set of the DPS 9000 with its proprietary GCOS 8 operating system. Within the memory space of the emulator, the 36-bit word of the DPS 9000 is stored right justified in the least significant 36 bits of the “host” (Itanium) 64-bit word during the emulation process. The upper 28 bits of the 64-bit word are typically zero; however, sometimes, certain specific bits in the “upper” 28 bits of the “containing” word are used as flags or for other temporary purposes. In any case, the upper 28 bits of the containing word are always viewed by the “emulated” view of the world as being non-existent. That is, only the emulation program itself uses these bits or else they are left as all zeroes. Leaving the bits as all zeroes can also be a signal to the software emulator that it is “emulating” a 36-bit instruction, and the non-zero indication would signal a 64-bit instruction.
Thus, while the principles of the invention have now been made clear in an illustrative embodiment, there will be immediately obvious to those skilled in the art many modifications of structure, arrangements, proportions, the elements, materials, and components, used in the practice of the invention which are particularly adapted for specific environments and operating requirements without departing from those principles.
It is specifically noted that there are many levels of memory hierarchy in modern computer systems, and the terms for describing the “real” memory address, “logical” memory address, “physical” memory address and other such terms are intended to express the concept of the invention and not to be limiting or literally interpreted. For example, the words “real memory” as visualized at one level of the memory hierarchy may not indeed be the lowest level of the memory hierarchy and various tables and translations of the address can take place in the host system hardware or software beneath what is seen by the programmer or user.
