Patent Application
20150092065
The present techniques relate generally to video display and processing systems, and devices that include such systems. More particularly, the present techniques relate to decreasing power consumption in such video display and processing systems.
Video processing and display systems, such as those used in computers and other electronic devices, transmit packetized video data via a data link from a source, such as a video player or computer graphics processing unit, to a sink system, which may include a display panel or recorder, at a predetermined throughput rate defined by a standard, such as the Display Port video interface standard developed by the Video Electronics Standards Association. Video processing systems are designed to meet the throughput rate of the relevant standard across a range of operating parameters, including a range of supply voltages, ambient temperatures, and process speeds.
Link training is the handshake process by which the source and sink of a video processing system synchronize. System parameters, including the number of data lanes to enable and the link rate, are determined via a link training handshake between the source and sink that occurs on the auxiliary channel (AUX). Link training is successfully completed when the sink is synchronized to the incoming data link. The throughput rate of a typical video processing/display system will be slower at slow process speeds and lower applied supply voltages, and power consumption will be relatively low under those operating conditions. Conversely, the throughput rate will be higher at faster process speeds and higher applied supply voltages, but power consumption will be increased under those operating conditions. Thus, system designers face an inherent design tradeoff between throughput rate and power consumption, i.e., higher throughput rates carry a penalty in the form of increased power consumption. Accordingly, typical video processing systems are designed to operate reliably at the slow corner (i.e., slow process speed and low supply voltage) and to accept the tradeoff of increased power consumption at the fast corner (i.e., fast process speed and higher supply voltage). Designing the systems to operate reliably at the slow corner also helps to ensure link training is successful across all operating corners. However, training the link to operate at the slow corner may not reflect actual operating conditions and thus may carry the above-referenced power consumption penalty when the system is operating outside the slow corner.
The same numbers are used throughout the disclosure and the figures to reference like components and features. Numbers in the 100 series refer to features originally found in
In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
Some embodiments may be implemented in one or a combination of hardware, firmware, and software. Some embodiments may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by a computing platform to perform the operations described herein. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine, e.g., a computer. For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; or electrical, optical, acoustical or other form of propagated signals, e.g., carrier waves, infrared signals, digital signals, or the interfaces that transmit and/or receive signals, among others.
An embodiment is an implementation or example. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” “various embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the present techniques. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. Elements or aspects from an embodiment can be combined with elements or aspects of another embodiment.
Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
It is to be noted that, although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of circuit elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
Electronic device 100 may also include a hard disc drive 106. Electronic device 100 may further include various other subsystems indicated at 108, including for example interface circuitry to connect peripheral devices such as a keyboard or mouse (not shown) and the like. Electronic device 100 may also include a graphics processing unit or GPU 110 for processing video data and an input/output (I/O) interface system 112. Each of CPU 102, memory 104, hard disc drive 106, subsystems 108, GPU 110 and I/O interface system 112 are interconnected via a signal bus 116, such as, for example, an ISA, EISA or SCSI bus. I/O interface system 112 includes source system 118, which will be more particularly described in connection with
Sink system 120 includes sink physical layer or sink PHY 240 and display driver and control circuitry 242. Sink PHY 240 receives the formatted video data from source 118 and formats the data for display, including regenerating the timing, clock and other signals or parameters to synchronize the received video data. Display driver and control circuitry 242 transfers the frames of video data to receiving system 130 in accordance with the timing parameters generated by source PHY 212, and includes logic to control the operation of receiving system 130. In embodiments, receiving system 130 may be a television or other display element or panel, a video recorder, or other device configured to receive, store, display, and/or otherwise process video data. Source and Sink systems 118 and 120, respectively, may also exchange control and other signals via AUX channel 250, which is a half-duplex bidirectional link. HPD signal link 260 is a hot plug detect line by which sink system 120 communicates to source system 118 that a receiving device has been connected to sink system 120.
Link training may be initiated upon a hot plug detect signal issued by sink system 120 that is transferred via HPD signal link 260 to source system 118. Link training may also be triggered by, for example, an interrupt request signal issued by sink system 120 to source system 118 via HPD signal link 260 indicating a potential loss of synchronization or at any other time the main link 220 has lost synchronization. Once initiated, link training determines the operating configuration and parameters of the main link 220, including the number of lanes to enable and the link rate, dependent at least in part upon the characteristics of sink system 120 and receiving system 130.
In embodiments, as will be further described hereinafter, link training of main link 220 may further include setting an initial value for the voltage swing on the lanes of main link 220 as provided by VR 224 and, thus, the initial lane voltage swing at which source PHY 212 transmits or otherwise provides the formatted video data to sink system 120 and receiving system 130. The initial lane voltage swing on main link 220 may, in embodiments, be established by CPU 102 executing instructions 105 to control the voltage level output by VR 224. In other embodiments, the initial lane voltage swing on main link 220 may be set by logic within CTRL 30 which, in turn, controls the voltage level output by VR 224. While, in still other embodiments, the initial lane voltage swing on main link 220 may be set by any combination of CPU 102, instructions 105, and CTRL 30. If link training is successful at the initial voltage, normal operation of electronic device 100 commences. If link training is not successful, CPU 102 executing instructions 105 or CTRL 30, or a combination thereof, read the information communicated by the sink PHY 120 to the source PHY 118 via the AUX channel 250 and, dependent at least in part thereon, increases the lane voltage swing provided by VR 224 to source PHY 118 thereby relaxing the timing constraints. The process is then repeated until link training is successful or until link training fails at a value above a threshold for the lane voltage swing.
Determining sink capabilities at block 302 includes determining the collective capabilities, including throughput rate, memory/buffer size, etc., of the sink system, such as sink system 120, the receiving system, such as receiving system 130, and the interconnection between the source and sink systems, and between the sink and receiving systems, such as buses 122 and 124.
At block 304, an initial value for main link lane voltage swing is set dependent at least in part upon the characteristics of the link determined at block 302. Other link training parameters are established at block 304 that may also be dependent at least in part upon the characteristics of the link determined at block 302, including the initial main link bit rate. The main link initial lane voltage swing is established, in embodiments, by VR 224 supplying the initial main link lane voltage swing to the lanes of main link 220 based upon one or more control signals from CTRL 230 and/or CPU 102 executing instructions 105 stored in memory 104. In embodiments, the main link lane voltage swing is set to an initial level below a threshold, dependent at least in part upon the characteristics of the link, as determined at block 302. The initial main link lane voltage may, in other embodiments, be set to the output voltage of VR 224 that is below a threshold.
At block 306, link training is conducted. As will be understood by one of ordinary skill in the art, link training generally includes adjusting drive settings and bit rates until the link is successfully trained, i.e., bit lock and signal lock are achieved on each of the lanes to be configured and any suitable number of lanes are symbol locked with inter-lane alignment. Whether link training was successful may be determined via the AUX channel 250, such as, for example, source system 118 reading the status registers (not shown) of at least one of sink 120 and receiving system 130. The details of the entire link training process are outside the scope of this disclosure and thus are not presented herein.
If link training is determined at block 308 to have been successfully completed at the initial value of main link lane voltage swing established at block 304, or at a subsequent value set at block 320, link training transitions at block 322 to EQ link training method 400, as will be more particularly described hereinafter with reference to
If it is determined at block 312 that the current bit rate is below a predetermined value, the current main link lane voltage swing is detected at block 316 to determine if the current main link lane voltage swing is above a predetermined value. If the current main link lane voltage swing is above a predetermined value, link training has failed and link training ends at block 324. Conversely, if the current link lane voltage swing is not above a predetermined value, the main link lane voltage swing is increased or incremented by any suitable amount at block 320, and link training is again attempted at block 306.
As shown in the process flow diagram of
Conduct EQ link training at block 402 includes, for example and as will be known to one of ordinary skill in the art, transmitting test patterns, such as, for example, test pattern set 2 or test pattern set 3, over the main link and writing certain initiating data bytes via the AUX channel. The details of the entire EQ link training process are beyond the scope of this disclosure and thus are not presented here.
The EQ link trained determination at block 404 determines whether EQ link training was successful. If so, normal operation of the video processing system is commenced at block 406 and the training process ends at block 414. If the EQ link training was not successful, the low bit rate check at block 408 is performed to determine whether the lowest bit rate has been reached. If the lowest bit rate has been reached, method 400 at junction B or block 412 returns to the link training method 300 illustrated in
Method 500 includes determine link capabilities 502, set initial lane voltage swing 504, conduct link training 506, and conduct EQ link training and link training check 508. Determine link capabilities 502, which generally corresponds to determine link capabilities 302 of the embodiment illustrated in
The various software components discussed herein may be stored on the tangible, non-transitory, computer-readable medium 600, as indicated in
An electronic device is provided herein that includes a source system for the processing of video data. The electronic device trains the main video data link at an initial main link lane voltage swing level, and in some embodiments at a value for the main link lane voltage swing that is below a threshold. If link training is not successful at the initial main link lane voltage swing level, the electronic device iteratively increases the main link lane voltage swing level until link training is successful or until link training fails at the value for the main link lane voltage swing above a threshold.
In some embodiments, the electronic device includes a voltage regulator, wherein the voltage regulator provides the voltage for the main link lane voltage swing. In some embodiments, the initial main link lane voltage swing can be below a threshold value. In addition, the electronic device can include at least one of a controller having logic and a microprocessor executing instructions that cause the voltage regulator to provide the initial main link lane voltage swing and to increment the main link lane voltage swing.
A method for the link training that reduces power consumption is provided herein. The method includes setting an initial value for the main link lane voltage swing and attempting link training at that initial value. If link training is not successful at the initial main link lane voltage swing value, the method iteratively increases the main link lane voltage swing value until link training is successful or until link training fails at the value for the main link lane voltage swing that is above a threshold.
In some embodiments, the method can include setting an initial bit rate, and conducting the link training of the main data link at the initial value of voltage swing at the initial bit rate. In addition, the method may include decrementing the initial bit rate to a current bit rate when the current value of voltage swing is equal to the threshold value of voltage swing. In some embodiments, the method can also include determining whether the link training has failed a predetermined number of times at the current value of the voltage swing, and, if so, incrementing the current value of the voltage swing.
At least one machine readable medium is provided herein. The readable medium includes instructions stored therein that, in response to being executed on an electronic device, cause the electronic device to reduce power consumption during link training of the main video data link of an electronic device. The instructions include causing the electronic device to set an initial value for the main link lane voltage swing and to conduct link training at that initial value. If link training is not successful at the initial main link lane voltage swing value, the instructions cause the electronic device to iteratively increase the main link lane voltage swing value until link training is successful or until link training fails at the value for the main link lane voltage swing that is above a threshold.
In some embodiments, the instructions can cause the electronic device to conduct an EQ training of the main data link. The instructions may also cause the electronic device to determine during the EQ training of the main link whether a low bit rate has been reached and, if not, to iteratively reduce the bit rate and conduct EQ training until one of EQ training is successful, or a predetermined low bit rate is reached at the value above a threshold of the lane voltage swing.
It is to be understood that specifics in the aforementioned examples may be used anywhere in one or more embodiments. For instance, all optional features of exemplary devices described above may also be implemented with respect to any of the other exemplary devices and/or the method described herein. Furthermore, although flow diagrams and/or state diagrams may have been used herein to describe embodiments, the present techniques are not limited to those diagrams or to their corresponding descriptions. For example, the illustrated flow need not move through each box or state or in exactly the same order as depicted and described.
The present techniques are not restricted to the particular details listed herein. Indeed, those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present techniques. Accordingly, it is the following claims including any amendments thereto that define the scope of the techniques.
