Patent Application
20190295485
This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2018-054626 filed on Mar. 22, 2018, the contents of which are incorporated herein by reference.
The technical field relates to a liquid crystal control circuit, an electronic timepiece, and a liquid crystal control method.
Recently, mobile devices represented by mobile phones have been dramatically developed, and a demand for higher performance and higher functionality of displays for mobile devices has increased. As performance required for displays, there are lager area, higher resolution, smaller thickness and less weight, narrower frame, lower power consumption, higher luminance, wider view angle, faster responsibility, and so on.
Also, since a lot of mobile devices are driven by batteries, the available time of each device is determined by the power consumption of the system and the capacity of the battery. For this reason, it is essential to reduce the power consumption of each system, and it is very strongly required to reduce the power consumption of each of devices to be installed in such mobile devices. For this purpose, MIP (Memory-in-Pixel) liquid crystal panels are suitable. In Japanese Patent No. 5450784, an invention related to control on an MIP liquid crystal display is disclosed.
In general liquid crystal displays, even in the case of still images such as standby images for mobile devices, in order to keep displaying such a still image, current should be continuously applied. In contrast, in MIP liquid crystal displays, since pixels constituting a screen have memories, if a still image is displayed, it is possible to keep displaying the still image, without applying current.
As compared to electronic paper displays competing as display elements, MIP liquid crystal displays consume less power during data updating, and can perform image rewriting more quickly, and are superior in visibility in bright environments and dark environments. Electronic paper displays need to perform screen refreshing in order to rewrite screens. For this reason, they cannot display videos. However, MIP liquid crystal displays can display videos.
Also, as compared to organic EL (Electro-Luminescence) displays competing as display elements, MIP liquid crystal displays are superior in power consumption and visibility in bright environments. In organic EL displays, a predetermined current is applied to each self-luminous display element. However, in MIP liquid crystal displays, when displaying a still image is kept, current is not applied to each display element.
In MIP liquid crystal displays, the timings when a COM inversion signal is applied to each display element in order to maintain the reliability of each display are not synchronized with the timings of image data signals. In such MIP liquid crystal displays, if the output timings of them overlap, image writing may not be normally performed. For this reason, timing control for avoiding competition between the COM inversion signal and image data signals is required.
According to the invention disclosed in Japanese Patent No. 5450784, it is possible to avoid competition between the COM inversion signal and image data signals. However, according to the invention of Japanese Patent No. 5450784, image data signals are transmitted at timings different from the timings when they should be transmitted under ordinary circumstances. Therefore, the quality of video display is damaged.
A liquid crystal control circuit related to preferred embodiments is provided for driving a MIP (Memory In Pixel) liquid crystal panel. The MIP liquid crystal panel has a plurality of pixels, each of which includes a memory element and a display element. The memory element holds electric potential depending on an image signal. The display element is applied voltage depending on the electric potential which the memory element holds. The liquid crystal control circuit includes an inversion unit that inverts polarity of AC voltage in a first mode in which an enable signal is output. The AC voltage being is applied to the display element in synchronization with outputting of the enable signal. The enable signal activates the image signal output to the MIP liquid crystal panel.
Hereinafter, an embodiment will be described in detail with reference to the drawings.
In a liquid crystal panel in which the timings of a COM inversion signal (VCOM) for maintaining the reliability of the liquid crystal panel and the timings of image data signals are not synchronized, like MIP liquid crystal panels, control for avoiding competition for timing between the VCOM and image data signals is performed.
The electronic timepiece 1 includes a CPU (Central Processing Unit) 2, a DMA (Direct Memory Access) controller 3, and a RAM (Random Access Memory) 4. The electronic timepiece 1 also includes the VCOM synchronous-transmission circuit 5 and an MIP liquid crystal panel 6. The electronic timepiece 1 is for measuring time and displaying the time.
The CPU 2 is for controlling the whole of the electronic timepiece 1, and is connected to the DMA controller 3 and the VCOM synchronous-transmission circuit 5, and directly controls them. The CPU 2 sets a mode switch signal and the number of times of VCOM inversion for the VCOM synchronous-transmission circuit 5, and outputs data transmission commands. Here, the CPU 2 selects such an optimum value that VCOM inversion is performed less and does not influence the reliability of the MIP liquid crystal panel, and sets the selected value as the number of times of VCOM inversion.
The DMA controller 3 is a dedicated circuit for transmitting image data from the RAM 4 (to be described below) to the MIP liquid crystal panel 6 via the VCOM synchronous-transmission circuit 5. The DMA controller is used to output image data to the VCOM synchronous-transmission circuit 5 after the CPU 2 outputs a data transmission command to the VCOM synchronous-transmission circuit 5. However, the DMA controller 3 may be configured with a dedicated circuit for outputting data, not as a general-purpose DMA controller.
The RAM 4 is a volatile semiconductor memory device, and is for storing image data to be displayed on the MIP liquid crystal panel 6.
The VCOM synchronous-transmission circuit 5 is a liquid crystal control circuit configured to drive and control the MIP liquid crystal panel 6 by outputting image data, the VCOM, and enable signals to the MIP liquid crystal panel. Image data is information on images to be displayed on the MIP liquid crystal panel 6. The VCOM is a VCOM inversion signal designating the polarity of AC voltage in order to maintain the reliability of the MIP liquid crystal panel 6. The enable signals are ENBS and ENBG shown in
The VCOM synchronous-transmission circuit 5 determines an operation mode according to the mode switch signal set by the CPU 2. Also, the VCOM synchronous-transmission circuit 5 transmits image data corresponding to the designated number of times at the interval from an inversion of the VCOM to the next inversion.
The MIP liquid crystal panel 6 has a plurality of pixels, each of which has a memory element which holds electric potential according to an image signal, and a display element to which voltage according to the electric potential which the memory element holds is applied. In the MIP liquid crystal panel 6, each pixel has a built-in 1-bit static RAM as the memory element for holding electric potential according to an image signal.
If gate bus lines are selected, the MIP liquid crystal panel 6 stores data of data bus lines in the static RAMs. According to the data stored in the static RAMs, a display voltage supply circuit (not shown in the drawings) supplies voltage to the pixel electrodes of the display elements. Then, each display element performs display according to the voltage applied between the counter electrode and the pixel electrode.
In the case of rewriting display data, peripheral circuits are operated, and the data of the static RAMs in the individual pixels is updated. In the case where still image display is performed and display rewriting is not required, electric potential is always supplied to the pixel electrodes by the display voltage supply circuit, so any variation does not occur in the electric potential of each pixel electrode. Therefore, the VCOM inversion interval of the MIP liquid crystal panel 6 can be set to a frequency of 1 Hz. As a result, the MIP liquid crystal panel 6 can significantly reduce the power consumption.
The electronic timepiece 1 is a digital watch, and displays the time in numbers on the MIP liquid crystal panel 6. Since the electronic timepiece 1 is required to be driven with a very small battery for a long period, it is very important to reduce the power consumption.
In the periodic VCOM inversion mode (a second mode), the mode switch signal is set at the L level. In the periodic VCOM inversion mode, the VCOM is inverted at a predetermined interval. The polarity of the VCOM of the present embodiment is inverted every second.
In the periodic VCOM inversion mode, there is no data transmission command. Therefore, the enable signal is not output, and a data transmission state flag is maintained at the L level, and a data transmission end interrupt is not generated. Therefore, competition for timing between the VCOM and image data output signals does not occur.
In the VCOM synchronous-transmission mode, the VCOM is not inverted at the predetermined interval, but is inverted immediately before transmission of each data signal (i.e. at the timing earlier than the timing of transmission of each data signal by (trVCOM+tsVCOM). Therefore, the VCOM inversion timing and the data transmission timing are always different from each other. The period trVCOM is a transient period required to invert the polarity of the VCOM signal. The period tsVCOM is the period from an inversion of the polarity of the VCOM signal to when it becomes possible to perform data transmission.
In the example of
A time point t1 is the time point later than the time point t0 by the period thVCOM (a predetermined first period). At the time point t1, the VCOM changes from the L level to the H level. In this way, the polarity of the AC voltage of the MIP liquid crystal panel 6 is inverted.
A time point t2 is the time point later than the time point t1 by the period (trVCOM+tsVCOM) (a predetermined second period). At the time point t2, the enable signal becomes a pulse form. By this, the MIP liquid crystal panel 6 activates an image data signal. In other words, at the time point t2, the VCOM synchronous-transmission circuit 5 starts outputting the image data signal.
A time point t3 is the time point when a pulse of the enable signal ends, and is the time point later than the time point t2 by a period tw. At the time point t3, the data transmission state flag changes from the H level to the L level, and a data transmission end interrupt is generated. By this, the VCOM synchronous-transmission circuit notifies the CPU 2 that the next data transmission is possible.
By the series of operations from the time point tO to the time point t3, a set of image data constituting an image frame is output to the MIP liquid crystal panel 6.
At a time point t4, the CPU 2 outputs a data transmission command to the VCOM synchronous-transmission circuit 5. Then, the data transmission state flag changes from the L level to the H level. By this, the VCOM synchronous-transmission circuit 5 notifies the CPU 2 that the data transmission command has been received.
A time point t5 is the time point later than the time point t4 by the period thVCOM. At the time point t5, the VCOM changes from the H level to the L level, i.e. the polarity is inverted.
A time point t6 is the time point later than the time point t5 by the period (trVCOM+tsVCOM). At the time point t6, the enable signal becomes a pulse form. By this, the MIP liquid crystal panel 6 activates an image data signal. In other words, at the time point t6, the VCOM synchronous-transmission circuit 5 starts outputting the image data signal.
A time point t7 is the time point when a pulse of the enable signal ends, and is the time point later than the time point t6 by the period tw. At the time point t7, the data transmission state flag changes from the H level to the L level, and a data transmission end interrupt is generated. By this, the VCOM synchronous-transmission circuit notifies the CPU 2 that the next data transmission is possible.
By the series of operations from the time point t4 to the time point t7, a set of image data constituting an image frame is output to the MIP liquid crystal panel 6.
The variations in the individual signals from a time point t8 to a time point t11 are the same as the variations in the individual signals from the time point tO to the time point t3.
As described above, in the VCOM synchronous-transmission mode (the first mode), in synchronization with outputting of the enable signal, the polarity of the AC voltage to be applied to each display element is inverted. In this way, it is possible to avoid competition between the VCOM inversion signal and image data signals.
If the VCOM synchronous-transmission circuit inverts the VCOM and waits for the predetermined period whenever data transmission is performed, the frame rate of the MIP liquid crystal panel 6 may decrease. For this reason, the present embodiment is configured such that it is possible to set the number of times of VCOM inversion. For example, with respect to n-number of times of data transmission (wherein n is an integer of 2 or greater), the VCOM synchronous-transmission circuit inverts the VCOM and waits for the predetermined period. Inversion of the VCOM is performed only when the first data transmission is performed. In the time chart shown in
In the example of
A time point t21 is the time point later than the time point t20 by the period thVCOM. At the time point t21, the VCOM changes from the L level to the H level, i.e. the polarity is inverted.
A time point t22 is the time point later than the time point t21 by the period (trVCOM+tsVCOM). At the time point t22, the enable signal becomes a pulse form. By this, the MIP liquid crystal panel 6 activates an image data signal. In other words, at the time point t22, outputting of the image data signal is started.
A time point t23 is the time point when a pulse of the enable signal ends, and is the time point later than the time point t22 by the period tw. At the time point t23, the data transmission state flag changes from the H level to the L level, and a data transmission end interrupt is generated. By this, the VCOM synchronous-transmission circuit notifies the CPU 2 that the next data transmission is possible.
At a time point t24, the CPU 2 outputs a data transmission command to the VCOM synchronous-transmission circuit 5. Then, the data transmission state flag changes from the L level to the H level. By this, the VCOM synchronous-transmission circuit 5 notifies the CPU 2 that the data transmission command has been received.
A time point t25 is the time point later than the time point t24 by a period Δt. In the second data transmission operation, since the VCOM is not inverted, it is unnecessary to wait for the predetermined period. Therefore, immediately after a data transmission command, it is possible to perform the next data transmission. However, in practice, operations such as setting of a rewrite address of the MIP liquid crystal panel 6, acquisition and setting of image data, and so on are required from when a data transmission command is received to when a pulse of the enable signal rises. For this, the period Δt is required.
At the time point t25, the enable signal becomes a pulse form. By this, the MIP liquid crystal panel 6 activates an image data signal. In other words, at the time point t25, outputting of the image data signal is started.
A time point t26 is the time point when a pulse of the enable signal ends, and is the time point later than the time point t25 by the period tw. At the time point t26, the data transmission state flag changes from the H level to the L level, and a data transmission end interrupt is generated. By this, the VCOM synchronous-transmission circuit notifies the CPU 2 that the next data transmission is possible.
At a time point t27, the CPU 2 outputs a data transmission command to the VCOM synchronous-transmission circuit 5. Then, the data transmission state flag changes from the L level to the H level. By this, the VCOM synchronous-transmission circuit 5 notifies the CPU 2 that the data transmission command has been received.
A time point t28 is the time point later than the time point t27 by the period thVCOM. At the time point t28, the VCOM changes from the L level to the H level, i.e. the polarity is inverted.
A time point t29 is the time point later than the time point t28 by the period (trVCOM+tsVCOM). At the time point t29, the enable signal becomes a pulse form. By this, the MIP liquid crystal panel 6 activates an image data signal. In other words, at the time point t29, outputting of the image data signal is started.
A time point t30 is the time point when a pulse of the enable signal ends, and is the time point later than the time point t29 by the period tw. At the time point t30, the data transmission state flag changes from the H level to the L level, and a data transmission end interrupt is generated. By this, the VCOM synchronous-transmission circuit 5 notifies the CPU 2 that the next data transmission is possible.
By performing control as described above, the VCOM synchronous-transmission circuit 5 can avoid competition for transmission between the VCOM and data while maintaining the frame rate of the MIP liquid crystal panel 6.
First, the VCOM synchronous-transmission circuit 5 starts the second mode (M10) in which the VCOM is periodically inverted. Processing in the mode M10 will be described below with reference to
In the mode M10, if the mode switch signal changes to the H level, the VCOM synchronous-transmission circuit 5 transitions to the first mode (M20) in which data is transmitted in synchronization with the VCOM. Processing in the mode M20 will be described below with reference to
In the mode M20, if the mode switch signal changes to the L level, the VCOM synchronous-transmission circuit 5 transitions to the second mode (M10) in which the VCOM is periodically inverted.
If starting processing, the VCOM synchronous-transmission circuit 5 determines whether the mode switch signal is at the L level (STEP S10). If the mode switch signal is not at the L level (“No” in STEP S10), the VCOM synchronous-transmission circuit 5 ends the processing of the
If 1 second has elapsed (“Yes” in STEP S11), the VCOM synchronous-transmission circuit 5 inverts the VCOM (STEP S12), and returns to STEP S10. If 1 second has not elapsed (“No” in STEP S10), the VCOM synchronous-transmission circuit 5 returns to STEP S10.
If transitioning to this mode, the VCOM synchronous-transmission circuit 5 sets the number of times of VCOM inversion (STEP S30). The number of times of VCOM inversion is set with respect to the VCOM synchronous-transmission circuit 5 by the CPU 2.
Next, the VCOM synchronous-transmission circuit 5 determines whether the mode switch signal is at the H level (STEP S31). If the mode switch signal is not at the H level (“No” in STEP S31), the VCOM synchronous-transmission circuit 5 ends the processing of
If a data transmission command has not been received (“No” in STEP S32), the VCOM synchronous-transmission circuit 5 returns to the process of STEP S31. If a data transmission command has been received (“Yes”), the VCOM synchronous-transmission circuit 5 proceeds to the process of STEP S33, and sets the data transmission state flag to the H level. In this way, the CPU 2 can detect that a data transmission command has been received by the VCOM synchronous-transmission circuit 5.
Thereafter, the VCOM synchronous-transmission circuit 5 waits for the period thVCOM (STEP S34), and inverts the VCOM (STEP S35), and waits for the period (trVCOM+tsVCOM) (STEP S36). Then, the VCOM synchronous-transmission circuit 5 transmits the enable signals (ENBG and ENBS) (STEP S37). The VCOM synchronous-transmission circuit 5 sets the data transmission state flag at the L level (STEP S38), and generates an data transmission end interrupt (STEP S39) to notify the end timing of the data transmission operation to the CPU 2.
In STEP S40, the VCOM synchronous-transmission circuit 5 determines whether image data constituting image frames has been transmitted the number of times of inversion set. If image data constituting image frames has been transmitted the number of times of inversion set (“Yes”), the VCOM synchronous-transmission circuit 5 returns to the process of STEP S31. If image data constituting image frames has not been transmitted the number of times of inversion set (“No”), the VCOM synchronous-transmission circuit 5 returns to the process of STEP S37.
The above-described embodiment can be modified, for example, in the following forms (a) to (c). (a) The VCOM synchronous-transmission circuit 5 is installed in the electronic device 1; however, it can be installed in other electronic devices. For example, the VCOM synchronous-transmission circuit can be installed in e-book readers, tablets, heart rate monitors, pedometers, thermometers, stopwatches, and so on.
(b) The period thVCOM from when the VCOM synchronous-transmission circuit 5 receives a data transmission command to when the VCOM synchronous-transmission circuit inverts the VCOM is not limited to a minimum period required to avoid competition between the VCOM inversion signal and data signals, and may be set to have a length equal to that of the minimum period or longer than that of the minimum period by 500 msec (milisecond) or less. 500 msec is half of the inversion interval in the mode in which the VCOM is periodically inverted.
(c) The period (trVCOM+tsVCOM) from when the VCOM synchronous-transmission circuit 5 inverts the VCOM to when the VCOM synchronous-transmission circuit transmits data is not limited to a minimum period required to avoid competition between the VCOM inversion signal and data signals, and may be set to have a length equal to that of the minimum period or longer than that of the minimum period by 500 msec or less. 500 msec is half of the inversion interval in the mode in which the VCOM is periodically inverted.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2018-054626 | Mar 2018 | JP | national |
