Patent Application
20080198119
This application claims priority, under 35 U.S.C. §119, of Korean Patent Application No. 10-2007-0016984 filed in the Korean Intellectual Property Office on Feb. 20, 2007, the entire contents of which are incorporated by reference herein.
(a) Field of the Invention
The present invention relates to liquid crystal displays and more particularly to a display panel having an integrated data-storage unit.
(b) Description of the Related Art
A typical liquid crystal display (LCD) includes two opposing panels having pixel electrodes (attached to specific pixels) and a common electrode (common to all pixels), and a liquid crystal layer therebetween having dielectric anisotropy interposed. The pixel electrodes are arranged in a matrix and connected to switching devices such as thin film transistors (TFTs). Data voltages are applied sequentially in to pixels row by row. The common electrode is disposed over the entire surface of one panel and applies a common voltage to all pixels in the matrix. The pixel electrodes, the common electrode, and the liquid crystal layer interposed therebetween constitute a liquid crystal capacitor. The liquid crystal capacitor together with the switching element (e.g., TFT) connected thereto becomes a unit of a pixel. In the LCD, voltages are applied to the two electrodes connected each pixel to generate an electric field at across the liquid crystal layer, and the strength of the electric field is controlled to control the transmittance of light that passes through the liquid crystal layer, thus obtaining desired images. In this case, in order to prevent a degradation, generated as the electric field is applied for alternating times long time in one direction to the liquid crystal layer and then the opposite direction. The polarity of the data voltages with respect to the common voltage is inverted by frames, by rows, or by pixels.
Small sized LCD display devices are typically used for mobile phones, etc., and dual display devices having outer and inner display panels are being actively developed.
The dual display devices include a main display unit that is mounted on the inside, a sub-display unit that is mounted on the outside, a driving FPC (flexible printed circuit film) that has wires that transmit signals from an external device, a main FPC disposed between the driving FPC and the main display panel, a sub-FPC disposed between the main display panel and the sub-display panel, and an integrated chip controlling the above elements.
The integrated chip generates control signals and driving signals for the main and sub-display panels, and is typically mounted on the main display device by a chip-on-glass (COG) technique. Since the driving FPC connects an external device and the LCD, the driving FPC is also called an interface FPC.
Data about the manufacturer, the year of manufacture, or simple display panel information is stored in the LCD using a data-storing element such as a read-only memory (ROM).
After being manufactured as a separate IC (integrated circuit), the data-storing element is mounted on the main display unit by the COG technique like the integrated chip. Alternatively, the data-storing element is built into the integrated chip.
However, when the data-storing element is manufactured as the IC, manufacturing cost of the LCD increases and separate driving voltages are required for driving the IC.
In addition, when the data-storing element is built into the integrated chip, the size of the chip increases.
A first aspect of the invention provides a method of manufacturing a liquid crystal display having an integrated data-storage. The method comprises: providing a first display panel and forming a first plurality of transistors and a second plurality of transistors in a thin film on the first display panel, wherein the first plurality of transistors are pixel transistors arranged in a matrix, and the second plurality of transistors perform data-storage. The second plurality of transistors of the data-storing unit includes N transistors corresponding to N bits of data to be stored, wherein N is a natural number. Each of the N transistors is configured to have its input terminal (electrode) connected to one of a first voltage and a second voltage according to one corresponding bit of the data. Each of the N transistors has an output terminal (electrode) commonly connected to a data output terminal of the data-storing unit. The second plurality of transistors of the data-storing unit further includes transistors interconnected to form a serial-in parallel-out shift register, the outputs of the shift register being connected to the input terminals of the N transistors.
Another aspect of the present invention provides, a liquid crystal display that includes a display panel having a plurality of pixels, and a data-storing unit integrated into the display panel. The data-storing unit includes a plurality of transistors, each having an input terminal connected to a first voltage or a second voltage and an output terminal connected to a data output terminal, and a Serial-In, Parallel-Out (SIPO) shift register formed of a plurality of registers (flip flops) connected in series, and supplied with a reset and first and second clock signals and connected to the input terminals of the transistors, respectively.
The data-storing unit may include a first pin that receives the reset signal and a second pin connected to the data output terminal.
The first and second clock signals may be generated based on a clock signal used in an SPI (serial peripheral interface), or may be generated based on a write/read signal used in a CPU I/F.
The liquid crystal display may further include a gate driver applying gate signals to the pixels and supplying third and fourth clock signals. The first and second clock signals may be generated based on the third and fourth clock signals.
The display panel may include a first display panel and a second display panel that is smaller than the first display panel, and the data-storing unit may be integrated into the first display panel.
The first and second clock signals may have phases opposite to each other.
According to another embodiment of the present invention, a display panel includes a plurality of gate lines, a plurality of data lines, a plurality of pixels connected to the gate lines and the data lines, and a data-storing unit, wherein the data-storing unit includes a plurality of transistors, each with an input terminal connected to a first voltage or a second voltage. Each of the plurality of transistors of the data-storing unit has an output terminal connected to a data output terminal, and a shift register formed of a plurality of registers (flip-flops) supplied with a reset signal and at least two clock signals and connected to the input terminals of the transistors, respectively.
The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, film, region, substrate, or panel is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the present invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. As an example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present invention.
Exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings for clear understanding of advantages of the present invention, wherein:
An LCD according to an exemplary embodiment of the present invention now will be described in detail with reference to
Referring to
The panel assembly 300 includes a plurality of signal lines G1-Gn, D1-Dm, and S1-S3, a plurality of pixels PX connected to the signal lines G1-Gn and D1-Dm and arranged substantially in a matrix, and a data-storing unit 710 connected to the signal lines S1 and S2. The matrix of pixels is contained within a display area that is defined (bounded) by a black matrix.
In the structural view shown in
Referring to
The switching element Q is disposed on the lower panel 100 and has three terminals, i.e., a control terminal connected to the gate line Gi, an input terminal connected to the data line Dj, and an output terminal connected to the LC capacitor Clc and the storage capacitor Cst.
The LC capacitor Clc includes a pixel electrode 191 disposed on the lower panel 100 and a common electrode 270 disposed on the upper panel 200 as two terminals. The LC layer 3 disposed between the two electrodes 191 and 270 functions as the dielectric of the LC capacitor Clc. The pixel electrode 191 is connected to the switching element Q The common electrode 270 is supplied with a common voltage Vcom and covers the entire surface of the upper panel 200. Alternatively, unlike as shown in
The storage capacitor Cst is an auxiliary capacitor for the LC capacitor Clc. The storage capacitor Cst includes the pixel electrode 191 and a separate signal line, which is provided on the lower panel 100, overlaps the pixel electrode 191 separated by an insulator, and is supplied with a predetermined voltage such as the common voltage Vcom. Alternatively, the storage capacitor Cst includes the pixel electrode 191 and an adjacent gate line called a previous gate line, which overlaps the pixel electrode 191 separated by an insulator.
The data-storing unit 710 is operated based on the reset signal transmitted through the reset signal input line S1, and outputs to the outside digital data that is stored therein through the data output line S2. In this exemplary embodiment, the data-storing unit 710 may be a ROM (read-only memory).
In a color display, each pixel uniquely represents one of the three primary colors (i.e., spatial division) or each pixel sequentially represents each of the three primary colors (i.e., temporal division) such that a spatial or temporal sum of the primary colors is recognized as a desired color. An example of a set of primary colors includes red, green, and blue.
One or more polarizers (not shown) are attached to the panel assembly 300. Meanwhile, referring to
The main and sub-display panels 300M and 300S are connected to each other through an auxiliary FPC 680S. A main FPC 680M is attached on the bottom of the main display panel 300M, and is also attached to a driving FPC 650.
The main FPC 680M includes a reset signal input wire L1 connected to the reset signal input line S1, a data output wire L2 connected to the data output line S2, and a plurality of signal line wires L3 connected to signal lines S3.
The wires L1-L3 formed on the main FPC 680M are connected to the reset signal input line S1, the data output line S2, and the signal lines S3 through contacts C1, C2, and C3, respectively. The ends of the reset signal input line S1, the data output line S2, and the signal lines S3, and the ends of the reset signal input wire L1, the data output wire L2, and the signal line wire L3 have pads, respectively, and the contacts C1-C3 are formed by connecting the pads.
In
The pads of the driving FPC 650, the pads of the main FPC 680M and sub-FPC 680S, and the pads of each of the display panels 300M and 300S are electrically connected to each other by an ACF (anisotropic conductive film) or by soldering.
Referring to
The gate driver 400 is a shift register that includes a plurality of stages (not shown) arranged in a cascade and each of the stages is connected to a portion of the gate lines G1-Gn. The gate driver 400 receives a scanning start signal STV, a plurality of clock signals, and a gate-off voltage Voff, and synthesizes a gate-on voltage Von and the gate-off voltage Voff to generate the gate signals for application to the gate lines G1-Gn.
The data driver 500 is connected to the data lines D1-Dm of the panel assembly 300 and applies data voltages, which are selected from among the gray voltages supplied from the gray voltage generator 800, to the data lines D1-Dm. Alternatively, the gray voltage generator 800 generates only a few of the reference gray voltages rather than all the gray voltages, and the data driver 500 may divide the reference gray voltages to generate the data voltages from among the provided reference gray voltages.
The signal controller 600 controls the gate driver 400, the data driver 500, etc.
As shown in
The integrated chip 700 receives external signals through an input portion 660 (
The operation of the above-described LCD will now be described in detail.
The signal controller 600 is supplied with input image signals R, G, and B and input control signals for controlling the display thereof from an external graphics controller (not shown). The input image signals R, G, and B contain luminance information of pixels PX, and the luminance has a predetermined number of grays, for example 1024 (=210), 256 (=28), or 64 (=26) grays. The input control signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, and a data enable signal DE.
Based on the input control signals and the input image signals R, G, and B, the signal controller 600 generates gate control signals CONT1 and data control signals CONT2 and processes the image signals R, G, and B to be suitable for the operation of the panel assembly 300 and the data driver 500. The signal controller 600 sends the gate control signals CONT1 to the gate driver 400 and sends the processed image signals DAT and the data control signals CONT2 to the data driver 500.
The gate control signals CONT1 include a scanning start signal STV for instructing the gate driver 400 to start scanning and at least one clock signal for controlling the output period of the gate-on voltage Von. The gate control signals CONT1 may include an output enable signal OE for defining the duration of the gate-on voltage Von.
The data control signals CONT2 include a horizontal synchronization start signal STH for initiating the start of data transmission for a row of pixels PX, a load signal LOAD for applying the data voltages to the data lines D1-Dm, and a data clock signal HCLK. The data control signal CONT2 may further include an inversion signal RVS for reversing the polarity of the data voltages (relative to the common voltage Vcom).
In response to the data control signals CONT2 from the signal controller 600, the data driver 500 receives a packet of the digital image signals DAT for a row of pixels PX from the signal controller 600, converts the digital image signals DAT into analog data voltages selected from the gray voltages, and applies the analog data voltages to the data lines D1-Dm.
The gate driver 400 applies the gate-on voltage Von to a gate line G1-Gn in response to the gate control signals CONT1 from the signal controller 600, thereby turning ON the switching transistors Q connected thereto. The data voltages applied to the data lines D1-Dm are then supplied to the pixels PX through the activated (ON) switching transistors Q.
A difference between a data voltage and the common voltage Vcom applied to a pixel PX is represented as a voltage across the LC capacitor Clc of the pixel PX, which is referred to as a pixel voltage. The LC molecules in the LC capacitor Clc assume orientations controlled by the magnitude of the pixel voltage, and the molecular orientations determine the polarization of light passing through the LC layer 3. The polarizer(s) converts light polarization to light transmittance such that the pixel PX has a luminance represented by a gray level indicated by the data voltage.
By repeating this procedure each unit of a horizontal period (which is also referred to as “1H” and is equal to one period of the horizontal synchronization signal Hsync and the data enable signal DE), all gate lines G1-Gn are sequentially supplied with the gate-on voltage Von, thereby applying the data voltages to all pixels PX to display an image for a frame.
When the next frame starts after one frame finishes, the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltages is reversed (which is referred to as “frame inversion”). The inversion signal RVS may also be controlled such that the polarity of the data voltages flowing in a data line are periodically reversed during one frame (for example row inversion and dot inversion), or the polarity of the data voltages in one packet are reversed (for example column inversion and dot inversion).
The data stored in the data-storing unit 710 is read by a device (not shown) connected thereto.
Referring to
Referring to
The transistors Tr are three-terminal elements such as TFTs (thin film transistors), with a control terminal (transistor gate) connected to an output terminal of the corresponding register SR, an input terminal connected to either a first voltage VCC or to a second voltage VSS depending upon a bit of stored data, and an output terminal connected to a data output terminal RDO. The sequence of the connections between the input terminals of the transistors Tr and either the voltage VCC or VSS defines the stored data in the data-storing unit 710. In other words, stored data is encoded (hard-wired) into the connections between the input terminals of the transistors Tr and the voltage VCC or VSS. The magnitude of the first voltage VCC is larger than that of the second voltage VSS, and the first voltage VCC is a high level voltage and corresponds to a logic value “1”, and the second voltage VSS is a low level voltage and corresponds to a logic value “0”.
The first and second voltages VCC and VSS may be voltages used in the integration chip 700 without application of a separate voltage from the outside.
Each of the registers SR includes a clock terminal CK, an input terminal IN, and (non-inverted) output terminals Q1 and Q2. Except for the first and last registers SR, the connections of the remaining registers SR are the same. Thus, in the middle transistors Tr, the input terminal IN is connected to the output terminal Q2 of the immediately previous transistor Tr, the clock terminal CK is connected to one of a first clock signal RCK and a second clock signal RCKB, and the output terminal Q1 is connected to the input terminal of the corresponding transistor Tr, respectively. As shown in
However, the input terminal IN of the first register SR is connected to a reset signal RST, and the output terminal Q2 of the last register SR is not connected. Except for the above connections of the first and last registers SR, the connections of the terminals CK, Q1, and Q2 of the first and last registers SR are the same as those of the middle registers SR.
The transistors Tr and the registers SR may be integrated into the LC panel assembly 300 along with (e.g., on the same thin film layer as) the TFT switching elements Q.
Referring to
When the LCD uses an SPI (serial peripheral interface), the first and second clock signals RCK and RCKB may be generated based on a clock signal that is applied to the SPI. The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard designed by Motorola, Inc. that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Alternatively, when the LCD uses a CPU I/F (central processing unit interface), the first and second clock signals RCK and RCKB may be generated based on a write/read (W/R) signal.
In addition, the first and second clock signals RCK and RCKB may be generated using clock signals that are applied to the gate driver 400 for generating the gate signals. As a result, since the first and second clock signals RCK and RCKB used in the data-storing unit 710 may be generated using internal signals of the LCD without the application of separate signals from the outside, the data-storing unit 710 receives the reset signal RST through the reset signal input line S1 and outputs data through the data output line S2 that is connected to the data output terminal RDO. Accordingly, the data-storing unit 710 needs only two pins, one for the reset signal input line S1 and one for the data output line S2.
The operation of the above data-storing unit 710 will now be described.
As shown in
Thus, the first transistor Tr is turned ON, and the corresponding voltage applied to the input terminal of the first transistor Tr, (for example the first voltage VCC), is transmitted to the data output terminal RDO to output a logic value (e.g., “1”).
As described above, the high level voltage from the output terminal Q2 of the first register SR is applied to the input terminal IN of the second register SR that is a subsequent stage and functions as a carry signal.
In synchronization with the carry signal, the second register SR operates to output a high level voltage to the output terminals Q1 and Q2 while the second clock signal RCKB outputs the high level voltage h1, and thereby a corresponding second transistor Tr is turned ON. By the turn-on of the second transistor Tr, a corresponding voltage, (for example the second voltage VSS), is transmitted to data output terminal RDO to output a logic value (e.g., “0”).
The plurality of registers SR, (the first register SR to the last register SR), are sequentially activated (i.e., sequentially output a logic high “1” voltage), and thereby the corresponding transistors Tr are sequentially turned ON. The first voltage VCC or the second voltage VSS applied to the input terminal of each turned-on transistor Tr is sequentially output to the data output terminal RDO.
In
At this time, in order to prevent data from being incorrectly output to the data output terminal RDO due to operation overlapping of the next adjacent registers SR, the data-storing unit 710 may output data only in synchronization with the data enable signal DE.
According to exemplary embodiments of the present invention, when data about the manufacturer, the date of manufacture or information about the display panel is stored in the LCD, the data-storing unit is integrated into the LC panel assembly (e.g., on the same layer as the TFTs). Since clock signals that are required for driving the data-storing unit are generated based on signals already provided and used in the LCD panels, the number of pins for inputting/outputting signals or data is reduced.
Since it is not necessary for a separate data-storing unit to be manufactured or mounted onto the LC panel assembly or built into an integrated chip, manufacturing costs decrease and the size of the integrated chip is not increased.
While this invention has been described in connection with what is presently considered to be the most practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2007-0016984 | Feb 2007 | KR | national |
