Patent Application
20090179845
This application claims the benefit of Korea Patent Application No. 10-2007-0141126 filed on Dec. 29, 2007, which is incorporated herein by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to a liquid crystal display and a method of driving the same. Exemplary embodiments are particularly suitable for preventing direct current (DC) image sticking, flicker, and nonuniform stains so as to increase the display quality of the liquid crystal display device.
2. Discussion of the Related Art
Active matrix type liquid crystal displays display a moving picture using a thin film transistor (TFT) as a switching element. The active matrix type liquid crystal displays have been implemented in televisions, as well as display devices in portable devices, such as office equipment and computers, because of the thin profile of active matrix type liquid crystal displays. Because of this thin profile feature, cathode ray tubes (CRT) are being rapidly replaced by active matrix type liquid crystal displays.
A liquid crystal display, shown in
The liquid crystal display is driven in an inversion manner in which a polarity of the liquid crystal cells Clc is inverted between the neighboring liquid crystal cells Clc and the polarity is inverted every one frame period, so as to reduce direct current (DC) offset components and to reduce the degradation of a liquid crystal. If a data voltage with a predetermined polarity is dominantly supplied to the liquid crystal cell Clc for a long time, image sticking may occur. The image sticking is called direct current (DC) image sticking because the liquid crystal cells Clc are repeatedly charged to a voltage with the same polarity. DC image sticking may also occur when the data voltage is supplied to the liquid crystal display in an interlaced manner. In the interlaced manner, the data voltage is supplied to the liquid crystal cells of odd-numbered horizontal lines during odd-numbered frame periods, and the data voltage is supplied to the liquid crystal cells of even-numbered horizontal lines during even-numbered frame periods.
As shown in
As another example of the DC image sticking, if the same image is moved or scrolled at a certain speed, voltages of the same polarity are repeatedly accumulated on the liquid crystal cell Clc depending on a relationship between the size of a scrolled picture and a scrolling speed (moving speed). Hence, the DC image sticking may appear. Another example of the DC image sticking is shown in
The display quality of the liquid crystal display is reduced by a flicker phenomenon as well as the DC image sticking. The flicker phenomenon means a luminance difference that can be periodically observed with the naked eye. Accordingly, the DC image sticking, and the flicker phenomenon have to be simultaneously prevented so as to improve the display quality of the liquid crystal display.
Nonuniform stains may appear on the display screen of the liquid crystal display. If a DC voltage of the same polarity is applied to a liquid crystal layer for a long time, impurity ions in the liquid crystal layer are separated depending on a polarity of the liquid crystal. Further, ions with different polarities are respectively accumulated on a pixel electrode and a common electrode inside the liquid crystal cells. If a DC voltage is applied to the liquid crystal layer for a long time, the amount of accumulated ions increases. Hence, an alignment layer is degraded and alignment characteristics of the liquid crystal are degraded. In other words, the application of the DC voltage to the liquid crystal display for the long time may cause the nonuniform stains on the display screen. The development of a liquid crystal material with a low permittivity or a method for improving an alignment material or an alignment method have been attempted so as to solve the nonuniform stain problem. However, it takes a long time and a heavy expense to develop a material used in the method. The use of the liquid crystal material with the low permittivity may reduce the drive characteristics of the liquid crystal. According to the experimental findings, as the amount of impurities ionized inside the liquid crystal layer increases and an acceleration factor becomes large, a time when the nonuniform stains are revealed becomes rapider. The acceleration factor may include a temperature, time, DC drive of the liquid crystal, and the like. Accordingly, the nonuniform stains may worsen at a high temperature or when the DC voltage of the same polarity is applied to the liquid crystal layer for the long time. Because the nonuniform stains appear between panels manufactured through the same manufacture line, the nonuniform stain problem cannot be solved by only the development of new material or an improvement in the process method. A method for suppressing the DC drive of the liquid crystal is effective in solving a nonuniform stain problem.
Accordingly, the present invention is directed to a liquid crystal display and driving method that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide a liquid crystal display and a method of driving the same capable of preventing DC image sticking, flicker, and nonuniform stains so as to increase the display quality.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the exemplary embodiments of the invention. These and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In one aspect, a liquid crystal display comprises a liquid crystal display panel including a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of liquid crystal cells, a data drive circuit that inverts a polarity of a data voltage supplied to the data lines in response to a polarity control signal, a gate drive circuit that supplies a gate pulse to the gate lines, and a timing controller that generates the polarity control signal and controls the data drive circuit and the gate drive circuit, wherein the timing controller allows the polarity control signal to have a different phase in each frame and allows the liquid crystal cells to be divided into a first liquid crystal cell group charged to the data voltage of a same polarity during two frame periods and a second liquid crystal cell group charged during a current frame period to the data voltage with a polarity opposite a polarity of the data voltage charged during a previous frame period, wherein the liquid crystal cells belonging to the first liquid crystal cell group and the liquid crystal cells belonging to the second liquid crystal cell group are arranged on one screen of the liquid crystal display panel, and wherein the liquid crystal cells belonging to the first liquid crystal cell group are successively charged to the data voltage of the same polarity during three or more frame periods at intervals of predetermined time equal to or longer than two frame periods.
In another aspect, a method of driving a liquid crystal display including a liquid crystal display panel including a plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of liquid crystal cells, a data drive circuit that inverts a polarity of a data voltage supplied to the data lines in response to a polarity control signal, a gate drive circuit that supplies a gate pulse to the gate lines, and a timing controller that generates the polarity control signal and controls the data drive circuit and the gate drive circuit, the method comprises allowing the polarity control signal to have a different phase in each frame and allowing the liquid crystal cells to be divided into a first liquid crystal cell group charged to the data voltage of the same polarity during two frame periods and a second liquid crystal cell group charged during a current frame period to the data voltage with a polarity opposite a polarity of the data voltage charged during a previous frame period, and arranging the liquid crystal cells belonging to the first liquid crystal cell group and the liquid crystal cells belonging to the second liquid crystal cell group on one screen and successively charging the liquid crystal cells belonging to the first liquid crystal cell group to the data voltage of the same polarity during three or more frame periods at intervals of predetermined time equal to or longer than two frame periods.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of embodiments of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
Reference will now be made in detail to an embodiment of the present invention, examples of which are illustrated in the accompanying drawings.
The exemplary embodiments of the invention invert a polarity of a data voltage every one frame period in scrolling data moving symbols or characters at 8-pixel speed in each frame period using a polarity control signal POL for controlling a polarity of a data voltage output from a data drive circuit, and allows the polarity of the data voltage in an N-th (where N is an integer equal to or larger than 4) frame period every M (where M is larger than N) frame periods to be the same as the polarity of the data voltage in a previous frame period of the N-th frame period. For instance, as shown in
As can be seen from a light waveform of
As shown in
A method of driving the liquid crystal display according to an exemplary embodiment of the invention supplies a data voltage having the same polarity to the liquid crystal cells during two (2) or more frame periods to prevent DC image sticking and nonuniform stains, and also inverts the polarity of the data voltage charged to the first liquid crystal cell group during two (2) frame periods to prevent flicker.
As shown in
Further, if data voltage having the same polarity is applied to all the liquid crystal cells, as shown in
As shown in
The liquid crystal display panel 90 includes an upper glass substrate, a lower glass substrate, and a liquid crystal layer between the upper and lower glass substrates. The lower glass substrate of the liquid crystal display panel 90 includes m data lines D1 to Dm and n gate lines G1 to Gn that cross each other. As such, the liquid crystal display panel 90 includes m×n liquid crystal cells Clc arranged in a matrix array at each crossing of the m data lines D1 to Dm and the n gate lines G1 to Gn. The liquid crystal cells Clc include a first liquid crystal cell group and a second liquid crystal cell group. The lower glass substrate further includes a thin film transistor TFT, a pixel electrode 1 of the liquid crystal cell Clc connected to the thin film transistor TFT, and a storage capacitor Cst, and the like.
The upper glass substrate of the liquid crystal display panel 90 includes a black matrix, a color filter, and a common electrode 2. The common electrode 2 is formed on the upper glass substrate in a vertical electric drive manner, such as a twisted nematic (TN) mode and a vertical alignment (VA) mode. The common electrode 2 and the pixel electrode 1 are formed on the lower glass substrate in a horizontal electric drive manner, such as an in-plane switching (IPS) mode and a fringe field switching (FFS) mode. Polarizers having optical axes that cross at a right angle are attached respectively to the upper and lower glass substrates. Alignment layers for setting a pre-tilt angle of the liquid crystal in an interface contacting the liquid crystal are respectively formed on the upper and lower glass substrates.
The timing controller 91 receives timing signals, such as vertical and horizontal sync signals Vsync and Hsync, a data enable signal DE, and a clock signal CLK which are input from a video source 95, and produces timing control signals for controlling operation timing of the logic circuit 92, the data drive circuit 93, and the gate drive circuit 94. The video source 95 includes, for example, a scaler mounted on a system board. The video source 95 converts video data input from an external video device or video data of a broadcasting signal received as a radio signal into digital data. Then, the video source 95 transmits the digital data to the timing controller 91 and at the same time, transmits the timing signals to the timing controller 91. The timing control signals produced by the timing controller 91 include, for example, a gate start pulse GSP, a gate shift clock signal GSC, a gate output enable signal GOE, a source start pulse SSP, a source sampling clock signal SSC, a source output enable signal SOE, and a polarity control signal POL. The gate start pulse GSP indicates a scan start line of a scan operation in 1 vertical period in which one screen is displayed. The gate shift clock signal GSC is a timing control signal that is input to a shift resistor installed in the gate drive circuit 94 to sequentially shift the gate start pulse GSP, and has a pulse width corresponding to a turned-on period of the thin film transistor TFT. The gate output enable signal GOE directs an output of the gate drive circuit 94. The source start pulse SSP indicates a start pixel in 1 horizontal line to which data will be displayed. The source sampling clock signal SSC directs a data latch operation to the data drive circuit 93 based on a rising or falling edge. The source output enable signal SOE directs an output of the data drive circuit 93. The polarity control signal POL indicates a polarity of the data voltage that will be supplied to the liquid crystal cells Clc of the liquid crystal display panel 90. The polarity control signal POL may include 1 dot inversion polarity control signal whose logic state is inverted every one horizontal period or a 2 dot inversion polarity control signal whose logic state is inverted every 2 horizontal periods. The exemplary embodiment of the invention will be described below with the assumption that the polarity control signal POL includes the 2 dot inversion polarity control signal whose logic state is inverted every 2 horizontal periods.
In an embodiment, the timing controller 91 divides digital video data RGB into odd-numbered pixel data RGBodd and even-numbered pixel data RGBeven so as to lower a transmission frequency of the digital video data RGB, and then supplies the data RGBodd and RGBeven to the data drive circuit 93 through 6 data buses.
The logic circuit 92 receives the gate start pulse GSP and the source output enable signal SOE to sequentially output polarity control signals having different phases during K frame periods, where K is a positive integer smaller than N. Then, the logic circuit 92 repeatedly performs the above-described output operation for a predetermined period of time. After the logic circuit 92 changes output order of the polarity control signals from the Nth frame period, the logic circuit 92 repeatedly performs the changed output operation for a predetermined period of time. The logic circuit 92 may be built in the timing controller 91.
The data drive circuit 93 latches the digital video data RGBodd and RGBeven under the control of the timing controller 91, and then converts the digital video data RGBodd and RGBeven into analog positive and negative gamma compensation voltages in response to the polarity control signal POL output from the logic circuit 92. Hence, the data drive circuit 93 may generate analog positive and negative data voltages and supplies the analog positive and negative data voltages to the data lines D1 to Dm. The data drive circuit 93 inverts a polarity of the data voltage in response to the polarity control signal POL output from the logic circuit 92.
The gate drive circuit 94 includes, for example, a shift resistor, a level shifter for shifting an output signal of the shift resistor to a swing width suitable for a TFT drive of the liquid crystal cells Clc, and an output buffer. The gate drive circuit 94 may also include a plurality of gate drive integrated circuits (ICs) and sequentially outputs gate pulses (or scan pulses) each having a width of about 1 horizontal period.
As shown in
The frame counter 101 outputs frame count information Fcnt instructing the number of frames in an image to be displayed on the liquid crystal display panel 90 in response to the gate start pulse GSP, that is generated once during one frame period as soon as one frame period starts.
The line counter 102 outputs line count information Lcnt instructing a row (or horizontal line) of data to be displayed on the liquid crystal display panel 90 in response to the source output enable signal SOE instructing an output time point of the data voltage from the logic circuit 92 every one horizontal period.
The POL generation circuit 103, as shown in
The first POL generation circuit 111 generates the first polarity control signal POL#1, whose logic state is inverted depending on the frame count information Fcnt and the line count information Lcnt. The first polarity control signal POL#1 is inverted every 2 horizontal periods so that the liquid crystal cells arranged parallel to each other in a vertical direction are charged to the data voltage, whose polarity is inverted in a vertical 2-dot inversion manner. Every time a predetermined time, for example, 0.5 or 1 second elapses, the first POL generation circuit 111 inverts a phase of the first polarity control signal POL#1. The first inverter 113 inverts the first polarity control signal POL#1 to generate the third polarity control signal POL#3 whose phase is opposite to the phase of the first polarity control signal POL#1.
The second POL generation circuit 112 generates a second polarity control signal POL#2, whose logic state is inverted depending on the frame count information Fcnt and the line count information Lcnt. A phase of the second polarity control signal POL#2 is shifted from the phase of the first polarity control signal POL#1 by about 1 horizontal period. For each predetermined time, for example, 0.5 or 1 second elapses, the second POL generation circuit 112 inverts the phase of the second polarity control signal POL#2. The second inverter 114 inverts the second polarity control signal POL#2 to generate the fourth polarity control signal POL#4 whose the phase is opposite to the phase of the second polarity control signal POL#2.
The frame controller 116 receives the frame count information Fcnt and the line count information Lcnt to control the multiplexer 115 so that the polarity control signal corresponding to each frame can be output as shown in
As shown in
The logic circuit 92, as shown in
A location of the liquid crystal cells belonging to the first liquid crystal cell group and a location of the liquid crystal cells belonging to the second liquid crystal cell group are reversed in each frame due to the polarity control signals POL_FGDG4#1 to POL_FGDG1#4 of the first group for a predetermined period of time.
After the predetermined period of time elapses, when the first polarity control signal POL_FGDG2#1 of the second group is generated during the Nth frame period, the liquid crystal cells of odd-numbered rows are charged to the data voltage with the same polarity as the data voltage charged during previous two frame periods of the Nth frame period.
After the predetermined period of time elapses, when the polarity control signals POL_FGDG3#1 to POL_FGDG3#4 of the third group are generated, a location of the liquid crystal cells belonging to the first liquid crystal cell group and a location of the liquid crystal cells belonging to the second liquid crystal cell group are reversed in each frame.
After the predetermined period of time elapses, when the first polarity control signal POL_FGDG4#1 of the fourth group is generated during a 2Nth frame period, the liquid crystal cells of the odd-numbered rows are charged to the data voltage with the same polarity as the data voltage charged during previous two frame periods of the 2Nth frame period. Further, the liquid crystal cells of the odd-numbered rows are charged to the data voltage with the same polarity as the data voltage, that is charged during the Nth frame period, during 3 frame periods ranging from (2N−2)th to 2N frame periods.
After the predetermined period of time elapses, a location of the liquid crystal cells belonging to the first liquid crystal cell group and a location of the liquid crystal cells belonging to the second liquid crystal cell group are reversed in each frame due to polarity control signals POL_FGDG5#1 to POL_FGDG5#4 belonging to a fifth group, as illustrated in
After the predetermined period of time elapses, when a first polarity control signal POL_FGDG6#1 belonging to a sixth group is generated during a 3Nth frame period, the liquid crystal cells of the odd-numbered rows are charged to the data voltage with the same polarity as the data voltage charged during previous two frame periods of the 3Nth frame period. Further, the liquid crystal cells of the odd-numbered rows are charged to the data voltage with a polarity opposite the polarity of the data voltage, that is charged during the (2N−2)th to 2N frame periods, during 3 frame periods ranging from (3N−2)th to 3N frame periods, as illustrated in
To generate the polarity control signals POL shown in
The second POL generation circuit 112 generates the second polarity control signal POL_FGDG1#2 of the first group whose a logic state is inverted in order of low, low, high, and high logic states until the liquid crystal cells of the first to fourth horizontal lines Line#1 to Line#4 are scanned during the generation of the polarity control signals POL_FGDG1#L to POL_FGDG1#4 of the first group and the generation of the polarity control signals POL_FGDG2#1 to POL_FGDG2#4 of the second group. A phase of the second polarity control signal POL_FGDG1#2 of the first group is shifted from the phases of the first polarity control signals POL_FGDG1#L and POL_FGDG2#1 of the first and second groups by 1 horizontal period. Sequentially, the second POL generation circuit 112 generates the second polarity control signals POL_FGDG3#2 and POL_FGDG4#2 of the third and fourth groups having phases opposite the phases of the second polarity control signals POL_FGDG1#2 and POL_FGDG2#2 of the first and second groups. Then, the second POL generation circuit 112 generates the second polarity control signals POL_FGDG5#2 and POL_FGDG6#2 of the fifth and sixth groups having phases opposite the phases of the second polarity control signals POL_FGDG3#2 and POL_FGDG4#2 of the third and fourth groups.
As can be seen from
The method of driving the liquid crystal display according to the first implementation improves the DC image sticking and the flicker as shown in
As shown in
After the logic circuit 92 sequentially outputs polarity control signals POL_FGDG1#1 to POL_FGDG1#4 belonging to a first group during 4 frame periods, the logic circuit 92 sequentially outputs polarity control signals POL_FGDG2#5 to POL_FGDG2#8 belonging to a second group during 4 frame periods. In other words, the logic circuit 92 alternately outputs the polarity control signals POL_FGDG1#5 to POL_FGDG1#8 of the first group and the polarity control signals POL_FGDG2#1 to POL_FGDG2#4 of the second group every 4 frame periods. Hence, a location of the first liquid crystal cell group and a location of the second liquid crystal cell group change in each of second and third frame periods #2 and #3, during which a polarity of the data voltage is controlled by the second and third polarity control signals POL_FGDG1#2 and POL_FGDG1#3 of the first group, and sixth and seventh frame periods #6 and #7, during which a polarity of the data voltage is controlled by the second and third polarity control signals POL_FGDG2#6 and POL_FGDG2#7 of the second group, and thus the DC image sticking and the flicker can be prevented by suppressing the DC drive of the liquid crystal as shown in
To generate the polarity control signals POL shown in
The second POL generation circuit 112 generates the second polarity control signal POL_FGDG1#2 of the first group whose logic state is inverted in an order of low, low, high, and high logic states until the liquid crystal cells of the first to fourth horizontal lines Line#1 to Line#4 are scanned. The second polarity control signal POL_FGDG1#2 of the first group has a phase shifted from the phases of the first polarity control signals POL_FGDG1#1 and POL_FGDG2#1 of the first and second groups by 1 horizontal period.
As shown in
After the logic circuit 92 sequentially outputs polarity control signals POL_FGDG3#1 to POL_FGDG3#4 belonging to a third group during 4 frame periods, the logic circuit 92 sequentially outputs polarity control signals POL_FGDG4#1 to POL_FGDG4#4 belonging to a fourth group during 4 frame periods. In other words, the logic circuit 92 alternately outputs the polarity control signals POL_FGDG3#1 to POL_FGDG3#4 of the third group and the polarity control signals POL_FGDG4#1 to POL_FGDG4#4 of the fourth group every 4 frame periods. Hence, a location of the first liquid crystal cell group and a location of the second liquid crystal cell group change in each of first, fourth, fifth, and sixth frame periods #1, #4, #5, and #6, and thus the DC image sticking and the flicker can be prevented by suppressing the DC drive of the liquid crystal as shown in
To generate the polarity control signals POL shown in
The second POL generation circuit 112 generates the second polarity control signal POL_FGDG3#2 of the third group whose logic state is inverted in an order of low, low, high, and high logic states until the liquid crystal cells of the first to fourth horizontal lines Line#1 to Line#4 are scanned. The second polarity control signal POL_FGDG3#2 of the third group has a phase shifted from the phases of the first polarity control signals POL_FGDG3#1 and POL_FGDG4#1 of the third and fourth groups by 1 horizontal period.
In the second and third embodiments, the second inverter 114 may be removed in the POL generation circuit 103 generating the polarity control signals.
The method of driving the liquid crystal display according to additional embodiments can obtain substantially the same effect as the above-described embodiments by alternately generating the polarity control signals of the second embodiment and the polarity control signals of the third embodiment and by controlling the data drive circuit 93.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2007-0141126 | Dec 2007 | KR | national |
