Patent Application
20080158126
The present invention relates to liquid crystal displays (LCDs) and particularly relates to a liquid crystal display that can eliminate flicker effect when switched on and can eliminate residual image effect when switched off, and a driving method of the liquid crystal display.
A liquid crystal display has the advantages of portability, low power consumption, and low radiation, and has been widely used in various portable information products such as notebooks, personal digital dassistants (PDAs), video cameras and the likes. The liquid crystal display generally includes a liquid crystal panel and a backlight module opposite to the liquid crystal panel. The liquid crystal panel includes a plurality of pixel units for displaying images.
Referring to
Typically, the common electrode 55 is applied with a predetermined common voltage Vcom, and the pixel electrode 54 is applied with a gray-scale voltage Vd. The common voltage Vcom of the common electrode 55 and the gray-scale voltage Vd of the pixel electrode 54 generate an electric field. The strength of the electrical field controls an amount of light beams transmitting through the liquid crystal capacitor 50. Thus, the pixel unit 5 displays an image with a desire gray-scale level. Generally, the gray-scale voltage of the pixel electrode 54 is switched from a positive value to a negative value with respect to the common voltage Vcom of the common electrode 55, in order to avoid deterioration of the liquid crystal layer.
Referring to
Furthermore, when the liquid crystal display is powered off, the pixel unit 5 is switched off, and the common voltage Vcom slowly drops to 0V. Thus, the voltage difference still exists between the common electrode 55 and the pixel electrode 54, and the electric field still exists for allowing the amount of transmission of light beams. Therefore, a residual image is induced.
What is needed, therefore, is a liquid crystal display which can overcome the above-described deficiencies. What is also needed, is a driving method of such liquid crystal display.
An exemplary liquid crystal display includes a liquid crystal panel including a number of thin film transistors, a timing control circuit, a common voltage generating circuit and a gamma circuit. The timing control circuit is configured for generating a number of timing signals. The common voltage generating circuit is configured for generating a common voltage. The gamma circuit is configured for generating a plurality of gray-scale voltages. When the liquid crystal panel is powered on, the common voltage is applied to the liquid crystal panel and comes to a predetermined value before the gray-scale voltages are applied to the liquid crystal panel and reaches predetermined values. And when liquid crystal panel is powered off, the common voltage and the gray-scale voltages drops to 0V simultaneously by control of the common voltage generating circuit and the gamma circuit with the thin film transistors switched on.
Novel features and advantages of the liquid crystal display will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, all the views are schematic.
Reference will now be made to the drawings to describe preferred and exemplary embodiments of the present invention in detail.
Referring to
The liquid crystal panel 12 includes a plurality of gate lines 121 that are parallel to each other and that extend along a first direction, a plurality of data lines 122 that are parallel to each other and that extend along a second direction orthogonal to the first direction, a plurality of thin film transistors 123 that are provided in the vicinity of points of intersections of the gate lines 121 and the data lines 122 and function as switching elements, a plurality of pixel electrodes 124, a common electrode 125 opposite to the pixel electrodes 124, and a liquid crystal layer (not shown) sandwiched between the pixel electrodes 124 and the common electrode 125. Each thin film transistor 123 includes a gate electrode 1231 coupled to one corresponding gate line 121, a source electrode 1232 coupled to one corresponding data line 122, and a drain electrode 1233 coupled to one corresponding pixel electrode 124. A smallest area formed by every adjacent two data lines 122 and every adjacent two gate lines 121 is defined as a pixel unit (not labeled).
The power convertor 19 includes an input terminal (not labeled) coupled to the power source 11, a first output terminal (not labeled) coupled to the timing control circuit 16, a second output terminal (not labeled) coupled to the common voltage generating circuit 14, a third output terminal (not labeled) coupled to the gamma circuit 13, a fourth output terminal (not labeled) coupled to the controller 15, a fifth output terminal (not labeled) coupled to the gate driving circuit 18, and a sixth output terminal (not labeled) coupled to the gate driving circuit 18.
The power convertor 19 is configured for generating working voltages for the timing control circuit 16, the common voltage generating circuit 14, the gamma circuit 13, and the controller 15, and generating a switch-on voltage VGH and a switch-off voltage VGL of the thin film transistors 123 for the gate driving circuit 18. The switch-on voltage VGH is a high level voltage, and the switch-off voltage VGL is a low level voltage.
The timing control circuit 16 includes an input terminal (not labeled) coupled to the power convertor 19 for receiving a working voltage, a first control terminal (not labeled) coupled to the common voltage generating circuit 14, a second control terminal (not labeled) coupled to the gamma circuit 13, a third control terminal (not labeled) coupled to the controller 15, and a fourth control terminal (not labeled) coupled to the gate driving circuit 18. The timing control circuit 16 is configured for generating a common voltage timing control signal for the common voltage generating circuit 14, generating a gray-scale voltage timing control signal for the gamma circuit 13, and generating a plurality of other timing control signals for the controller 15 and the gate driving circuit 18.
The common voltage generating circuit 14 includes a first input terminal (not labeled) coupled to the power convertor 19 for receiving a working voltage, a second input terminal (not labeled) coupled to the timing control circuit 16, and an output terminal (not labeled) coupled to the common electrode 125. The common voltage generating circuit 14 is configured for generating a common voltage Vcom and providing the common voltage Vcom to the common electrode 125 according to the common voltage timing control signal of the timing control circuit 16.
The gamma circuit 13 includes a third input terminal (not labeled) coupled to the power convertor 19 for receiving a working voltage, a fourth input terminal (not labeled) coupled to the timing control circuit 16, and an output terminal coupled to the data driving circuit 17. The gamma circuit 13 is configured for generating a gray-scale voltage Vd, and providing the gray-scale voltages to the data driving circuit 17 according the gray-scale voltage timing control signal of the timing control circuit 16.
The controller 15 includes a fifth input terminal (not labeled) coupled to the power convertor 19 for receiving a working voltage, a sixth input terminal (not labeled) coupled to the timing control circuit 16, and an output terminal (not labeled) coupled to the gate driving circuit 18. The controller 15 is configured for generating a control signal Xon for the gate driving circuit 18 according to a timing control signal of the time control circuit 16. The control signal Xon can be a high level voltage or a low level voltage.
The gate driving circuit 18 includes a seventh input terminal (not labeled) coupled to the timing control circuit 16, an eighth input terminal (not labeled) coupled to the controller 15, a ninth input terminal (not labeled) coupled to the power convertor 19 to receive the switch-on voltage VGH, a tenth input terminal (not labeled) coupled to the power convertor 19 to receive the switch-off voltage VGL, and a plurality of output terminals (not labeled) respectively coupled to the gate lines 121. The gate driving circuit 18 is configured for generating a plurality of scanning signals for the gate lines 121 according to a timing control signal of the timing control circuit 16.
The data driving circuit 17 includes an input terminal (not labeled) coupled to the gamma circuit 13, and a plurality of output terminals (not labeled) respectively coupled to the data lines 122. The data driving circuit 17 is configured for applying the gray-scale voltages to the data lines 122, respectively.
Referring to
When the control signal XON is a low level voltage, the gate driving circuit 18 applies the switch-on VGH voltage to all the gate lines 121 simultaneously, and all the thin film transistors 123 are switched on.
When the thin film transistors 123 are switched on, the gray-scale voltages generated by the gamma circuit 13 are applied to the pixel electrodes 124 via the data driving circuit 17, the data lines 122, and the thin film transistors 123. The common electrode 125 is applied with the common voltage Vcom. Thus, electric fields are generated between the common electrode 125 and the pixel electrodes 124, and the strength of the electric fields controls amounts of transmission light beams of the pixel units. The electric fields keep during a frame period.
Referring to
At a time t1, the liquid crystal display 1 is powered on. That is, the power source 11 is switched on.
At a time t2, the common voltage generating circuit 14 generates a common voltage Vcom according to the common voltage timing control signal of the timing control circuit 16, and outputs the common voltage Vcom to the common electrode 125.
At a time t3, the gamma circuit 13 generates a gray-scale voltage Vd according to the gray-scale voltage timing control signal of the timing control circuit 16, and outputs the gray-scale voltage Vd to the pixel electrode 124.
During a “T” period from t2 to t3, the common voltage Vcom is set at a predetermined value. The “T” period generally lasts about 10 ms to 30 ms. In the “T” period, the controller 15 generates the control signal XON according to a timing control signal of the timing control circuit 16, and outputs the control signal XON to the gate driving circuit 18. And the power convertor 19 generates the switch-on voltage VGH and the switch-off voltage VGL for the gate driving circuit 18.
After the time t3, the liquid crystal display 1 starts to work normally. The gate driving circuit 18 sequentially applies the switch-on voltage VGH to the gate lines 121, thus the thin film transistors 123 connected thereto are switched on. Then the gray-scale voltage Vd generated by the gamma circuit 13 is applied to the pixel electrodes 124 via the data driving circuit 17, the data lines 122 and the switched on thin film transistors 123. The common electrode 125 is applied with the common voltage Vcom. Thus, an electric field generates between the common electrode 125 and the pixel electrodes 124, and the strength of the electric fields controls amounts of transmission light beams of the pixel units. In the next frame periods, the steps are repeated.
At a time t4, the liquid crystal displayer 1 is powered off. That is, the power 11 is switched off, and a switch-off process is executed.
At a time t5, the common voltage Vcom and the gray-scale voltage Vd simultaneously drop to 0V. The control signal XON also drops to a low level voltage. The gate driving circuit 18 simultaneously applies the switch-on voltage VGH to all the gate lines 121, thus all the thin film transistors 123 are switched on. The voltages of the pixel electrodes 124 also drop to 0V with the dropping of the gray-scale voltages Vd. Therefore, voltages of the pixel electrodes 124 and the common electrode 125 all drop to 0V. Referring also to
Unlike conventional liquid crystal displays, when the liquid crystal display 1 is powered on, the common voltage Vcom is generated by the common voltage generating circuit 14 before the gray-scale voltage Vd is generated. And the common voltage Vcom is applied to the common electrode 125 and reaches to a predetermined value before the gray-scale voltages Vd are applied to the pixel electrodes 124. That is, voltage difference between the common electrode 125 and the pixel electrodes 124 do not vary, thus no flicker is induced. Furthermore, when the liquid crystal display 1 is powered off, the common voltage Vcom of the common electrode 125 and the gray-scale voltages Vd of the pixel electrodes 124 drop to 0V simultaneously, and all the thin film transistors 123 are switched on. Therefore, charges stored between the common electrode 125 and the pixel electrodes 14 are released via the activated thin film transistors 123 quickly. Accordingly, no residual images are induced.
It is to be understood, however, that even though numerous characteristics and advantages of preferred embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only; and that changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 95149685 | Dec 2006 | TW | national |
