Patent Grant
9378695
Korean Patent Application No. 10-2013-0090420, filed on Jul. 30, 2013, in the Korean Intellectual Property Office, and entitled, “Liquid Crystal Display and Driving Method Thereof,” is incorporated by reference herein in its entirety.
1. Field
One or more embodiments described herein relate to a display device.
2. Description of the Related Art
A liquid crystal display is one of the many types of flat panel displays currently in use. This type of display includes a liquid crystal layer between a pixel electrode and a common electrode, and data and gate drivers are controlled to generate an image from a plurality of pixels. In operation, the pixel electrode receives a data voltage through a switching element and a counter electrode receives a common voltage. These voltages cause an electric field to be generated in the liquid crystal layer to control transmittance of light, thereby displaying an image.
The liquid crystal display may also receive an image signal from an external graphics controller. The image signal contains luminance information on each pixel, and the data voltage to be applied to each pixel corresponds to the desired luminance information. The data voltage appears as a pixel voltage depending on a difference from the common voltage applied to the common electrode. Each pixels displays luminance represented by a gray scale value of the image signal depending on the pixel voltage.
One effect which degrades the quality of images on a liquid crystal display is known as the degradation phenomenon. This phenomenon occurs when the electric field to the liquid crystal layer is applied in one direction for a long period of time. In an attempt to prevent the degradation phenomenon, the polarity of the data voltage may be inverted respect to a reference voltage on a frame, row, column, or pixel basis. Further, in an attempt to prevent unwanted textures (e.g., a vertical line), the polarity of the pixel voltages of adjacent pixels may set to be different.
Another undesirable effect may occur as a result of the liquid crystal layer. For example, the liquid crystal display may have different response characteristics during the period between when the polarity of the pixel voltage changes from a negative to a positive voltage and when the polarity of the pixel voltage changes from a positive to a negative voltage. For example, the rising speed of the pixel voltage may be slower than a falling speed. The difference in these speeds may cause a change in luminance.
The luminance change may cause problems when the liquid crystal display is driven. For example, differences in luminance may be visually recognized when the liquid crystal display is driven at a relatively low frequency. Referring to a temporal contrast sensitivity function (TCSF), in particular, even though the actual change in luminance may be small when the liquid crystal display is driven at a low frequency, the change in luminance is recognized to be considerable. As a result, flicker may be visually recognized which leads to a degradation in display quality.
In accordance with one embodiment, a liquid crystal display includes a display panel having a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels; a gate driver to apply a gate-on voltage to each of the gate lines; a data driver to apply a positive data voltage and a negative data voltage to the data lines; a signal controller to control the gate driver and data driver and to receive image data; and a sensor to generate a blinking signal for input into the signal controller. The signal controller is configured to drive the data driver and gate driver at one of a moving image frequency or still image frequency, and the signal controller is configured to control refresh of the pixels based on to the blinking signal from the sensor when a still image is displayed.
The signal controller may be configured to control refresh of the pixels by generating a start pulse vertical signal STV synchronized with the blinking signal. The signal controller may be configured to synchronize a data enable signal with the start pulse vertical signal STV, which is synchronized with the blinking signal. The data driver may be configured to supply each of the pixels with a data voltage, a polarity of the data voltage inverted depending on the start pulse vertical signal STV.
The signal controller may generate the start pulse vertical signal STV in synchronism with the blinking signal based on a blinking enable signal BE. When a period of the blinking signal is longer than a period determined based on the still image driving frequency of the display panel, the signal controller may generate the start pulse vertical signal STV irrespective of receiving the blinking signal. The signal controller may generate the start pulse vertical signal STV to be synchronized with the still image driving frequency.
When the period of the blinking signal is longer than a period determined based on the still image driving frequency of the display panel, the signal controller may be configured to control driving of the display panel using a compensation lookup table, and the compensation lookup table includes values to compensate for a declined pixel voltage at a time of receiving the blinking signal. The signal controller may be configured to generate the start pulse vertical signal STV at a substantially constant rate at a time of receiving the blinking signal. The sensor may be configured to sense blinking based on motion of an eyelid of a user proximate the display panel.
In accordance with another embodiment, a method for driving a liquid crystal display includes receiving image data; identifying whether the image data is a moving image or a still image; controlling a gate driver and a data driver to display a moving image at a moving image frequency when the moving image is identified and to display a still image at a still image frequency when the still image is identified; sensing blinking to generate a blinking signal; and controlling refresh of one or more pixels in response to the blinking signal when the still image is displayed.
Controlling refresh of the one or more of pixels may include generating a start pulse vertical signal STV synchronized with the blinking signal. The method may include synchronizing a data enable signal with the start pulse vertical signal STV, which is synchronized with the blinking signal. The method may include inverting a polarity of a data voltage to each of the one or more pixels depending on the start pulse vertical signal STV.
Generating the start pulse vertical signal STV synchronized with the blinking signal may be controlled based on a blinking enable signal BE. Generating the start pulse vertical signal STV may be performed when a period of the blinking signal is longer than a period based on the still image frequency of the display panel and regardless of whether the blinking signal is received. The start pulse vertical signal STV may be synchronized with the still image driving frequency.
The method may include controlling the data driver based on a compensation lookup table when a period of the blinking signal is longer than a period based on the still image driving frequency. The compensation lookup table may include declined pixel voltages at the time of receiving the blinking signal. The start pulse vertical signal STV may be generated at a substantially constant interval at a time of receiving the blinking signal. The blinking signal may be generated only when the still image is displayed.
In accordance with another embodiment, an apparatus for controlling a liquid crystal display includes an input coupled to receive a plurality of eye blinking signals; and a signal controller to generate a plurality of start pulse signals based on the blinking signals during a predetermined mode of operation, the start pulse signals generated in a manner different from a vertical synchronization signal. The start pulse signals are generated to have an irregular spacing which corresponds to the blinking signals. The predetermined mode of operation may be a still image mode.
Features will become apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:
Example embodiments are described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art.
In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
A graphic processing unit (GPU) 10 may be positioned outside the liquid crystal display 1. The graphic processing unit 10 may provide input data including data for displaying an image and a panel self-refresh (PSR) signal. The PSR signal may be a signal to identify whether a corresponding image is a still image or a moving image. The liquid crystal panel 300 may display an image based on the input data and the PSR signal. When the input data corresponds to a still image as identified by the PSR signal, an image of a previous frame may be displayed repeatedly.
One of the gate lines G1 to Gn and one of the data lines D1 to Dm are connected to respective ones of the pixels PX. The pixels PX are arranged in a matrix form, and each pixel PX may include a thin film transistor Q, a liquid crystal capacitor Clc, and a sustain capacitor Cst. For each pixel, a control terminal of the thin film transistor Q may be connected to a corresponding one of the gate lines G1 to Gn and an input terminal of the thin film transistor Q may be connected to a corresponding one of the data lines D1 to Dm. An output terminal of the thin film transistor Q may be connected to a pixel electrode 191. The pixel electrode 191 may form one terminal of the liquid crystal capacitor Clc, and one terminal of the sustain capacitor Cst. The other terminal of the liquid crystal capacitor Clc is connected to a common electrode 270, and the other terminal of the sustain capacitor Cst may be applied with a sustain voltage.
According to one embodiment, the pixel electrode 191 and common electrode 270 (which may be considered to be field-generating electrodes) may be positioned on the lower panel 100. Also, in an alternative embodiment, the pixels PX of one row may be alternately connected to different adjacent gate lines on an alternating basis. That is, each gate line may be alternately connected to pixels in different rows, e.g., to upper and lower pixels. Thus, in this alternative embodiment, odd numbered pixels and even numbered pixels which belong to a same row may be connected to different gate lines. Each of the data lines D1 to Dm is connected to the pixels along a same column.
The signal controller 600 processes the input data, PSR signal, and one or more additional control signals (e.g., a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK) for operating the liquid crystal panel 300. The signal controller 600 generates and outputs image data DAT, a gate control signal CONT1, a data control signal CONT2, and a clock signal.
The gate control signal CONT1 includes a start pulse vertical signal STV for controlling a scanning start and a clock pulse vertical signal CPV which corresponds to generation of a gate-on voltage Von. An output period of the start pulse vertical signal STV coincides with one frame (or refresh rate). The gate control signal CONT1 may further include an output enable signal OE, which limits a duration of the gate-on voltage Von.
The data control signal CONT2 includes a start pulse horizontal signal STH, a load signal TP, and a data enable signal DE. The start pulse horizontal signal STH controls a transmission start of the image data DAT for a pixel of one row. The load signal TP controls applying data voltages to corresponding ones of the data lines D1 to Dm. The data control signal CONT2 may further include an inversion signal RVS that inverts a polarity of the data voltage relative to a common voltage Vcom.
The signal controller 600 uses the gate control signal CONT1 and data control signal CONT2 to enable the gate driver 400 and the data driver 500 to display a still image and moving images on the liquid crystal panel 300. The still image may be displayed at a still image frequency and the moving images at a moving image frequency. When a plurality of consecutive frames corresponds to same image data, the still image is displayed. When a plurality of consecutive frames corresponds to different image data, moving images are displayed. The signal controller 600 may identify whether the image data is a moving image or the still image based on the PSR signal.
The signal controller 600 may control display of a still image at a still image frequency which is lower than a moving image frequency at which moving images are displayed. According to one example, the still image frequency may be equal to or less than about ⅔ of the moving image frequency, e.g., a value of about 10 Hz or less or a value of about 1 Hz or less.
The gate lines G1 to Gn are connected to the gate driver 400. The gate-on voltage Von may be sequentially applied to the gate lines based on the gate control signal CONT1 from the signal controller 600. The gate-off voltage Voff may be applied to a section in which the gate-on voltage Von is not applied.
The data lines D1 to Dm are connected to the data driver 500. The data driver 500 receives the data control signal CONT2 and the image data DAT from the signal controller 600. The data driver 500 uses the gray scale voltage generated from a gray scale voltage generator to convert the image data DAT into data voltages for the data lines D1 to Dm. The data voltages may include data voltages having a positive polarity and data voltages having a negative polarity. The positive and negative polarity data voltages may be alternately applied based on a frame and a row and/or a column, and thus driven according to an inversion method. The inversion driving method may be applied to both cases of displaying moving images and a still image.
The blinking sensor 700 monitors a human eye and senses when blinking occurs. The blinking sensor 700 may generate and transmit a blinking signal BLK to the signal controller 600. Monitoring the human eye may be performed by a monitoring device, e.g., a camera. The monitoring device may be positioned inside or outside sensor 700. In
The signal controller 600 generates and outputs the start pulse vertical signal STV to be synchronized with the vertical synchronization signal Vsync. The signal controller 600 may also generate and output the start pulse vertical signal STV to be synchronized with the blinking signal BLK, at a time of receiving the blinking signal BLK. Therefore, the data voltage may be applied to each pixel during blinking, such that each pixel is recharged (refreshed).
According to one embodiment, the signal controller 600 generates and outputs the start pulse vertical signal STV in response to the blinking signal BLK in the case of a still image, e.g., in the case of low frequency driving. When the still image is displayed, each pixel may also be refreshed by the control of the signal controller 600, even in the section in which the blinking signal BLK is not present.
As further illustrated in the lower portion of
Referring to these figures in view of
However, as described above, when data voltages having different polarities are applied to a pixel depending on the start pulse vertical signal STV, output luminance instantly fluctuates due to asymmetric response speed that depends on polarity. The fluctuation portion of the output luminance may appear, for example, at every 1 second, when the liquid crystal display is driven at the still image frequency (e.g., 1 Hz), and thus may be visually recognized. In addition, considering the recognition characteristics of the human eye, the fluctuation portion may be visually recognized in a pronounced way, and therefore may be more easily recognized than fluctuation in the output luminance. This is particularly evident from
Also,
The blinking sensor 700 senses the eye state signal EYE to generate the blinking signal BLK. The controller 600 generates the start pulse vertical signal STV based on the blinking signal BLK. For example, the start pulse signal STV is generated to be synchronized with the blinking signal BLK. The controller 600 also synchronizes the data enable signal DE with the blinking signal BLK (or start pulse vertical signal STV). Therefore, each pixel is refreshed based on the data voltage being applied within a time period corresponding to when (e.g., at or near the moment) the user blinks his or her eye.
Because the refresh period is based on the blinking signal, the refresh period will vary (e.g., not be constant) and thus will be different from the period of the start pulse vertical signal STV, which is constant, for example, at 1 Hz. When a user does not blink his or her eye often, the refresh period will generally vary in a period longer than 1 second (1 Hz).
When refresh is performed, fluctuation in the output luminance appears due to asymmetric rising and falling characteristics of pixel charging depending on the polarity of the data voltage. As shown in
Also, in
The blinking enable signal BE may be particularly suitable when multiple users are present. For example, during low frequency driving, the start pulse vertical signal STV may be generated depending on the blinking of an eye of any one of the users. When this occurs, flicker may be much more recognizable by other users who have not blinked as the refresh period increases. Therefore when multiple users are present, the blinking enable signal BE may be set to a predetermined value, which, for example, may be a low value.
According to one embodiment, the blinking enable signal BE may control whether to generate the blinking signal BLK. When the blinking enable signal has a high value, the start pulse vertical signal STV may be generated to be synchronized with the blinking signal BLK, when the blinking signal BLK is input into the signal controller 600. When the blinking enable signal BE does not have a high value (e.g., a low value), the blinking signal BLK may not be generated and the signal controller 600 may generate the start pulse vertical signal STV to be synchronized with the vertical synchronization signal Vsync. In one embodiment, the blinking enable signal BE may be set to have a high value at a time of low frequency driving. This setting may be changed by the user (e.g., in response to a user-generated signal) or the signal controller.
The predetermined time may be set to correspond to a typical eye closing speed. For example, the predetermined time may be set to be about ⅙ the duration of when an eye may be expected to be closed. In other embodiments, the predetermined time may be a different value, taking into consideration, for example, a typical time required for a human to move his or her eye from about ½ of the pupil to about ⅔ of the pupil.
When it is sensed that the user intends to close his or her eye, the liquid crystal display may be driven in a blink mode (operation S750). In this case, the blinking sensor 700 generates the blinking signal BLK (operation S760) and the controller 600 changes the generation period of the start pulse vertical signal STV in response to the blinking signal BLK (operation S770). The blinking enable signal has a high value at this time (operation S780) based, for example, on detection of the presence of at least one user in an area proximate the display device.
Because the shape and size of an eyelid, pupil size and the degree of coverage of the pupil with an eyelid, and eye blinking speed is likely to be different for different people, in one embodiment blinking may be sensed based on information in a database that is personalized for each user, based on, for example, on eyelid position and moving speed.
In the case where blinking occurs at a normal rate, refresh may be performed by generating the start pulse vertical signal STV to be synchronized with the blinking signal BLK, as described in
When the user has his or her eye(s) closed during refresh (that is, during the change in luminance), the user may not see flicker at this time. However, because the difference in luminance immediately before the user closes his or her eye(s) and immediately after the user opens his or her eye is large, the user may recognize the difference in luminance as flicker when the user opens his or her eye(s). This is evident from a third refresh indicated by the dotted oval in the upper timing diagram of
When blinking signal BLK is not generated within a period determined by the lowest driving frequency of the display panel (within a predetermined or long period), generation of the start pulse vertical signal STV may be controlled based on a compensation enable signal CE.
Referring to
If a blink has not occurred during the predetermined time, the compensation mode is activated (operation S840) and the compensation enable signal CE is changed from a low value to a high value (operation S850). A predetermined time after the CE signal goes high, the BE signal goes low (operation S860). The start pulse vertical signal STV is generated at constant intervals as long as the CE signal has a high value and in synchronism with the changing of the BE signal to a low value (operation S870).
The CE signal may maintain a high value during low frequency driving until the detected frequency of blinking equals or becomes greater than the predetermined driving frequency of the display panel or when moving images are detected.
During the compensation mode, the signal controller 600 may generate the start pulse vertical signal STV of a normal driving frequency (the still image frequency of, for example, 10 Hz or the moving image frequency of, for example, 60 Hz) at the time the blinking signal BLK is input.
Data compensation may then be performed (operation S880). Taking into consideration reduced luminance that may occur immediately before refresh, the data voltage (which may represent the same or substantially the same luminance as the reduced luminance) may be applied to the pixel. Then, a data voltage having a gradually increasing gray scale value may be applied to the pixel.
In order to apply the data voltage having the gradually increasing gray scale value, a separate lookup table may be used. For example, when a pixel displays a still image using 254 gray scale values and then represents the luminance of 249 gray scale values immediately before refresh (due to gradually reducing luminance) in the compensation mode, the pixel may be driven in such a manner that a data voltage of 249 gray scale values is applied to the corresponding pixel in a first frame, a data voltage of 250 gray scale values is applied to the pixel in a second frame, and the gray scale value is gradually increased and then 254 gray scale values, which is a normal gray scale value, is applied in a fifth frame.
Meanwhile, the state in which the user continues to close his or her eye(s) may be considered. The blinking sensor 700 may generate an eye closing signal when an eyelid is not opened, even after the eyelid is completely closed and then the predetermined time passes. The controller 600 receives the eye closing signal and controls driving in a manner to reduce power consumption. This driving control may include, for example, generating the start pulse vertical signal STV as in the blinking mode as described above, or generating the start pulse vertical signal STV at the lowest driving frequency period of the display panel. Additionally, or alternatively, driving control may include turning off a light source such as a backlight.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
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