Claims
- 1. A liquid crystal display comprising:
a substrate having first, second and third regions; a first transistor on the first region of the substrate, the first transistor including:
a first metal-induced lateral crystallization (MILC) region having a first channel region; and a first metal-induced crystallization (MIC) region adjacent the first MILC, wherein a boundary between the first MILC region and the first MIC region is located outside the first channel region; a second transistor on the second region of the substrate, the second transistor including:
a second MILC region having a second channel region; and a second MIC region adjacent the second MILC region, wherein a boundary between the second MILC region and the second MIC region is located outside the second channel region; and a third transistor on the third region of the substrate.
- 2. The liquid crystal display according to claim 1, wherein the substrate includes a glass substrate having a driver circuit region and a pixel region, the first transistor, second transistor, and third transistor being on the glass substrate, the first and second transistors being part of the driver circuit region and the third transistor being part of the pixel region.
- 3. The liquid crystal display according to claim 1, wherein the third transistor includes an active layer made of amorphous silicon.
- 4. The liquid crystal display according to claim 1, wherein the third transistor includes an active layer made of polysilicon.
- 5. The liquid crystal display according to claim 1, wherein the third transistor includes:
a third MILC region having a third channel region; and a third MIC region adjacent the third MILC region, wherein a boundary between the third MILC region and the third MIC region is located outside the third channel region.
- 6. The liquid crystal display according to claim 1, wherein the first and second transistors are part of a CMOS transistor unit for a driver circuit of the liquid crystal display.
- 7. The liquid crystal display according to claim 1, wherein the first MILC region of the first transistor includes side portions at sides of the first channel region.
- 8. The liquid crystal display according to claim 7, wherein at least one of the side portions has a length of about 0.01 to 5.0 μm.
- 9. The liquid crystal display according to claim 1, wherein the first MILE region includes a portion of source and drain regions of the first transistor.
- 10. The liquid crystal display according to claim 1, wherein at least one of the first and second transistors has a polysilicon channel region and one of a lightly doped drain (LDD) and offset region.
- 11. The liquid crystal display according to claim 10, wherein the third transistor has an amorphous silicon channel region.
- 12. The liquid crystal display according to claim 11, wherein the third transistor has one of an LDD or offset region.
- 13. The liquid crystal display according to claim 10, wherein the third transistor has a polysilicon channel region.
- 14. The liquid crystal display according to claim 13, wherein the third transistor has one of an LDD or offset region.
- 15. The liquid crystal display according to claim 1, wherein the third transistor has an amorphous silicon channel region.
- 16. The liquid crystal display according to claim 15, wherein the third transistor has one of an LDD or offset region.
- 17. The liquid crystal display according to claim 1, wherein the third transistor has a polysilicon channel region.
- 18. The liquid crystal display according to claim 17, wherein the third transistor has one of an LDD or offset region.
- 19. A method of fabricating an LCD having first and second transistors for a driving circuit and a third transistor for a pixel array on a substrate, the method comprising the steps of:
forming an active layer for each of the first, second and third transistors on the substrate; formning a gate insulating layer and a gate electrode on each respective active layer of the first, se cond and third transistors; forming a metal layer on a first portion of each active layer of the first and the second transistors, the first portion excluding a second portion of each active layer adjacent each gate electrode of the first and the second transistors; forming source and drain regions for each of the first, second and third transistors using each respective gate electrode of the first, second and third transistors as a mask; and crystallizing each active layer of the first and the second transistors, the crystallizing being influenced by the metal layer.
- 20. The method according to claim 19, wherein said step of forming the metal layer includes the steps of:
forming a photoresist pattern covering the active layer excluding the first portion of each active layer of the first and the second transistors; depositing a metal over a resultant substrate including the photoresist pattern; and removing the photoresist pattern.
- 21. The method according to claim 19, wherein the metal layer includes one of Ni, Pd, Ti, Ag, Au, Al, Sb , Cu, Co, Cr, Mo, Ti, Ir, Ru, Rh, Cd and Pt, and their mixture.
- 22. The method according to claim 19, wherein the metal layer is formed to a thickness of 20 to 200 Å.
- 23. The method according to claim 19, wherein said second portion of each active layer of the first and the second transistors adjacent to each gate electrode has a length ranging from about 0.01 to 5 μm.
- 24. The method according to claim 19, wherein said step of crystallizing each active layer of the first and the second transistors includes the step of heating a resultant substrate having said each active layer of the first and the second transistors at a temperature of about 300 to 500° C.
- 25. The method according to claim 19, further comprising the steps of:
forming an insulating interlayer on an exposed surface of a resultant substrate; forming contact holes for exposing each of the source and drain regions of the first, second and third transistors; forming first, second and third wires connecting each of the source and drain regions of the first and second transistors electrically and, source and drain electrodes connecting of the third transistor, wherein the first and the second transistors form a CMOS transistor by the first, the second and the third wires; forming a passivation layer on the exposed surface of the resultant substrate; forming contact hole for exposing the drain region of the third transistor; and forming a pixel electrode connecting the drain electrode of the third transistor on the passivation layer.
- 26. A method of fabricating an LCD having first and second transistors for a driving circuit and a third transistor for a pixel array on a substrate, the method comprising the steps of:
forming an active layer for each of the first, second and third transistors on the substrate; forming a gate insulating layer and a gate electrode on each respective active layer of the first, second and third transistors; forming source and drain regions for each of the first, second and third transistors using each respective gate electrode of the first, second and third transistors as a mask; and forming a metal layer on a first portion of each active layer of the first and the second transistors, the first portion excluding a second portion of each active layer adjacent each gate electrode of the first and the second transistors; crystallizing each active layer of the first and the second transistors, the crystallizing being influenced by the metal layer.
- 27. The method according to claim 26, wherein said step of forming the metal layer includes the steps of:
forming a photoresist pattern covering the active layer excluding the first portion of each active layer of the first and the second transistors; depositing a metal over a resultant substrate including the photoresist pattern; and removing the photoresist pattern.
- 28. The method according to claim 26, wherein the metal layer includes one of Ni, Pd, Ti, Ag, Au, Al, Sb , Cu, Co, Cr, Mo, Ti, Ir, Ru, Rh, Cd and Pt, and their mixture.
- 29. The method according to claim 26, wherein the metal layer is formed to a thickness of 20 to 200 Å.
- 30. The method according to claim 26, wherein said second portion of each active layer of the first and the second transistors adjacent to each gate electrode has a length ranging from about 0.01 to 5 μm.
- 31. The method according to claim 26, wherein said step of crystallizing each active layer of the first and the second transistors includes the step of heating a resultant substrate having said each active layer of the first and the second transistors at a temperature of about 300 to 500° C.
- 32. The method according to claim 26, further comprising the steps of:
forming an insulating interlayer on an exposed surface of a resultant substrate; forming contact holes for exposing each of the source and drain regions of the first, second and third transistors; forming first, second and third wires connecting each of the source and drain regions of the first and second transistors electrically and, source and drain electrodes connecting of the third transistor, wherein the first and the second transistors form a CMOS transistor by the first, the second and the third wires; forming a passivation layer on the exposed surface of the resultant substrate; forming contact hole for exposing the drain region of the third transistor; and forming a pixel electrode connecting the drain electrode of the third transistor on the passivation layer.
Parent Case Info
[0001] This is a continuation-in-part of pending prior application No. 09/074,606 filed on May 8, 1998, which is incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09453172 |
Dec 1999 |
US |
Child |
09900140 |
Jul 2001 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09074606 |
May 1998 |
US |
Child |
09453172 |
Dec 1999 |
US |