Any and all applications for which a foreign or domestic priority claim is identified in the Application Data Sheet as filed with the present application are hereby incorporated by reference under 37 CFR 1.57. For example, this application claims priority to and the benefit of Korean Patent Application No. 10-2013-0053269 filed in the Korean Intellectual Property Office on May 10, 2013, the entire contents of which are incorporated herein by reference.
1. Field
The present disclosure relates to a liquid crystal display and a manufacturing method thereof, and more particularly, to a liquid crystal display having a liquid crystal layer (nano crystal) present in a microcavity and a manufacturing method thereof.
2. Description of the Related Technology
The liquid crystal display is a type of flat panel display widely used in recent years. The liquid crystal display includes two display panels in which a field generating electrode such as a pixel electrode and a common electrode are formed, and in which a liquid crystal layer is interposed between the two display panels. The liquid crystal display functions by applying a voltage to the field generating electrode to generate an electric field in the liquid crystal layer, determining an alignment of liquid crystal molecules of the liquid crystal layer by the electric field, and controlling polarization of incident light to display an image. A liquid crystal display having an EM (Embedded Microcavity) structure (nano crystal structure) is formed on a sacrificial layer using a photo resist, coating an upper portion with a supporting member, and then removing the sacrificial layer and filling the empty space with liquid crystal to form a display. In the empty space (microcavity) formed by removing the sacrificial layer, an alignment layer is formed to control the liquid crystal. In this case, the alignment layer is also injected in the microcavity. However, there are problems in that it takes much time to inject the alignment layer and the alignment layer is not uniformly coated on the walls of the microcavity.
The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
In one aspect, a liquid crystal display is provided. The liquid crystal display may use an inorganic alignment layer as an alignment layer in which liquid crystal molecules disposed in a microcavity are arranged.
In another aspect, a method of manufacturing a liquid crystal display is provided.
In another aspect, a liquid crystal display is provided that includes, for example, an insulation substrate, a pixel electrode formed on the insulation substrate, a lower alignment layer disposed on the pixel electrode and is an inorganic alignment layer formed of an inorganic insulating material, a liquid crystal layer disposed in a microcavity formed on the lower alignment layer, an upper alignment layer formed along a side and an upper surface of the microcavity and is an inorganic alignment layer formed of an inorganic insulating material, and a common electrode formed on the upper alignment layer, in which the upper alignment layer and the lower alignment layer enclose the liquid crystal layer.
In some embodiments, the inorganic insulating material may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiCx), amorphous silicon (a-Si), and FDLC (fluorinated diamond-like carbon). In some embodiments, the inorganic alignment layer may be formed of silicon oxide (SiOx). In some embodiments, a composition ratio of the silicon oxide (SiOx), x may have a value between about 2.3 and about 2.4. In some embodiments, a thickness of the upper alignment layer or the lower alignment layer may be between about 400 Å and about 1000 Å. In some embodiments, a dielectric constant of the upper alignment layer or the lower alignment layer may be between about 5 and about 7. In some embodiments, the upper alignment layer and the lower alignment layer may overlap between adjacent microcavities. In some embodiments, the upper alignment layer and the common electrode may be curved along the microcavity. In some embodiments, the liquid crystal display may further include a roof layer which covers the common electrode and includes a pillar. In some embodiments, the liquid crystal display may further include an upper insulating layer which covers the roof layer. In some embodiments, the liquid crystal display may further include a lower insulating layer which is disposed between the common electrode and the roof layer.
In another aspect, a method of manufacturing a liquid crystal display is provided, which includes, for example, forming a pixel electrode on an insulation substrate, forming a lower alignment layer with an inorganic alignment material so as to cover the pixel electrode, forming a sacrificial layer having a side and an upper surface on the lower alignment layer, forming an upper alignment layer with an inorganic alignment material on the side and the upper surface of the sacrificial layer, forming a common electrode to cover the upper alignment layer, forming a roof layer including a pillar to cover the common electrode, forming a liquid crystal injection hole to expose the sacrificial layer, removing the sacrificial layer exposed through the liquid crystal injection hole to form a microcavity, and injecting liquid crystal molecules in the microcavity to form a liquid crystal layer.
In some embodiments, the inorganic insulating material may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiCx), amorphous silicon (a-Si), and FDLC (fluorinated diamond-like carbon). In some embodiments, the inorganic alignment layer may be formed of silicon oxide (SiOx). In some embodiments, a composition ratio of the silicon oxide (SiOx), x may have a value of 2.3 or larger and 2.4 or smaller. In some embodiments, a thickness of the upper alignment layer or the lower alignment layer may be between about 400 Å and 1000 Å. In some embodiments, a dielectric constant of the upper alignment layer or the lower alignment layer may be between about 5 and 7. In some embodiments, the upper alignment layer or the lower alignment layer may be deposited under a condition that a deposition temperature is about 100° C., a deposition pressure is about 1.5 torr, nitrogen (N2O) is about 7000 sccm, SiH4 is about 120 sccm and the deposition time may be between about 27 seconds and about 75 seconds. In some embodiments, the forming of the lower alignment layer or the upper alignment layer may include removing the inorganic alignment layer deposited on a pad. In some embodiments, the forming of the lower alignment layer or the upper alignment layer may further include performing washing after forming the inorganic alignment layer with the inorganic alignment material.
In another aspect, as an alignment layer which initially aligns the liquid crystal molecules disposed in the microcavity, the inorganic alignment layer is used so that a process of injecting the alignment layer is not used, which may reduce the alignment layer formation step and shorten the manufacturing time. Further, the inorganic alignment layer is uniformly formed in the microcavity. In some embodiments, the alignment force of the inorganic alignment layer does not fall behind the alignment force of an alignment layer using the polyimide, so that there is no problem in the initial arrangement of the liquid crystal molecule.
Features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It will be understood these drawings depict only certain embodiments in accordance with the disclosure and, therefore, are not to be considered limiting of its scope; the disclosure will be described with additional specificity and detail through use of the accompanying drawings. An apparatus, system or method according to some of the described embodiments can have several aspects, no single one of which necessarily is solely responsible for the desirable attributes of the apparatus, system or method. After considering this discussion, and particularly after reading the section entitled “Detailed Description of Certain Inventive Embodiments” one will understand how illustrated features serve to explain certain principles of the present disclosure.
The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown and described. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
Now, a liquid crystal display according to an exemplary embodiment of the present disclosure will be described in detail with reference to
A gate line 121 and a sustain voltage line 131 are formed on an insulation substrate 110 formed of a transparent glass or plastic. The gate line 121 includes a first gate electrode 124a, a second gate electrode 124b, and a third gate electrode 124c. The sustain voltage line 131 includes storage electrodes 135a and 135b and a protrusion 134 which protrudes toward the gate line 121. The storage electrodes 135a and 135b have a structure which encloses a first sub-pixel electrode 192h and a second sub-pixel electrode 192l of a previous row pixel. A horizontal portion of the storage electrode of
A gate insulating layer 140 is formed on the gate line 121 and the sustain voltage line 131. On the gate insulating layer 140, a semiconductor 151 formed below the data line 171, a semiconductor 155 which is disposed below a source/drain electrode, and a semiconductor 154 formed in a channel portion of a thin film transistor are formed. On each of the semiconductors 151, 154, and 155 and between the data line 171 and the source/drain electrode, a plurality of ohmic contacts may be formed, which is not illustrated in the drawing.
On the semiconductors 151, 154, and 155 and the gate insulating layer 140, data conductors 171, 173c, 175a, 175b, 175c having a plurality of data lines 171, which has a first source electrode 173a and a second source electrode 173b, a first drain electrode 175a, a second drain electrode 175b, a third source electrode 173c and a third drain electrode 175c are formed.
The first gate electrode 124a, the first source electrode 173a, and the first drain electrode 175a form a first thin film transistor Qa together with the semiconductor 154 and a channel of the thin film transistor is formed in a semiconductor portion 154 between the first source electrode 173a and the first drain electrode 175a. Similarly, the second gate electrode 124b, the second source electrode 173b, and the second drain electrode 175b form a second thin film transistor Qb together with the semiconductor 154 and the channel of the thin film transistor is formed in the semiconductor portion 154 between the second source electrode 173b and the second drain electrode 175b. Further, the third gate electrode 124c, the third source electrode 173c, and the third drain electrode 175c form a third thin film transistor Qc together with the semiconductor 154 and the channel of the thin film transistor is formed in a semiconductor portion 154 between the third source electrode 173c and the third drain electrode 175c.
The data line 171 according to the present exemplary embodiment has a structure in which a width is reduced in a thin film transistor formation region near an extension 175c′ of the third drain electrode 175c. In some embodiments, the structure is intended to maintain a gap with an adjacent wiring line and reduce a signal interference, but the data line does not need to be formed with this structure.
A first passivation layer 180 is formed on the data conductors 171, 173c, 175a, 175b, and 175c and an exposed portion of the semiconductor 154. The first passivation layer 180 may include an inorganic insulator or an organic insulator such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiOxNy), or silicon oxide (SiOx).
A color filter 230 is formed on the passivation layer 180. Color filters 230 having the same color are formed in pixels that are adjacent in a vertical direction (data line direction). Further, color filters 230 and 230′ having different colors are formed in pixels that are adjacent in a horizontal direction (gate line direction) and two color filters 230 and 230′ may overlap on the data line 171. The color filters 230 and 230′ may represent one of three primary colors including red, green, and blue. However, the color filters 230 and 230′ are not limited to the three primary colors including red, green, and blue but may represent one of cyan, magenta, yellow, and white series colors.
A light blocking member (black matrix) 220 is formed on the color filters 230 and 230′. The light blocking member 220 is formed with respect to a region (hereinafter, referred to as a “transistor formation region”) where the gate line 121, the sustain voltage line 131, and the thin film transistor are formed and a region where the data line 171 is formed and is formed to have a lattice structure having an opening corresponding to a region where an image is displayed. A color filter 230 is formed in an opening of the light blocking member 220. Further, the light blocking member 220 is formed of a material through which light is not transmitted.
A second passivation layer 185 is formed on the color filter 230 and the light blocking member 220 to cover the color filter 230 and the light blocking member 220. The second passivation layer 185 may include an inorganic insulator or an organic insulator such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiOxNy), and silicon oxide (SiOx). Differently from the cross-sectional views of
A first contact hole 186a and a second contact hole 186b are formed in the color filter 230, the light blocking member 220, and the passivation layers 180 and 185 to expose the extension 175b′ of the first drain electrode 175a and the second drain electrode 175b. Further, a third contact hole 186c is formed in the color filter 230, the light blocking member 220, and the passivation layers 180 and 185 to expose the protrusion 134 of the sustain voltage line 131 and the extension 175c′ of the third drain electrode 175c.
In the present exemplary embodiment, even though contact holes 186a, 186b, and 186c are also formed in the light blocking member 220 and the color filter 230, it may be more difficult to etch the contact hole in the light blocking member 220 and the color filter 230 than to etch the contact hole in the passivation layers 180 and 185 depending on a material of the light blocking member 220 and the color filter 230. Therefore, when the light blocking member 220 or the color filter 230 is etched, the light blocking member 220 or the color filter 230 may be removed in advance from a position where the contact holes 186a, 186b, and 186c are formed.
In some embodiments, depending on the exemplary embodiment, the position of the light blocking member 220 is varied to etch only the color filter 230 and the passivation layers 180 and 185 to form the contact holes 186a, 186b, and 186c.
The pixel electrode 192 which includes the first sub-pixel electrode 192h and the second sub-pixel electrode 192l is formed on the second passivation layer 185. The pixel electrode 192 may be formed of a transparent conductive material such as ITO or IZO.
The first sub-pixel electrode 192h and the second sub-pixel electrode 192l are adjacent in the column direction, formed in a quadrangular shape as a whole and include a cross-shaped branch including a horizontal branch and a vertical branch intersecting therewith. Further, the first sub-pixel electrode 192h and the second sub-pixel electrode 192l are divided into four sub-regions by the horizontal branch and the vertical branch and each sub-region includes a plurality of minute branches.
The minute branches of the first sub-pixel electrode 192h and the second sub-pixel electrode 192l form an angle of approximately 40° to 45° with the gate line 121 or the horizontal branch. Further, the minute branches of two neighboring sub-regions may be perpendicular to each other. The width of the minute branch may be gradually increased and gaps between minute branches may be varied.
The first sub-pixel electrode 192h and the second sub-pixel electrode 192l are physically and electrically connected to the first drain electrode 175a and the second drain electrode 175b through the contact holes 186a and 186b and are applied with data voltages from the first drain electrode 175a and the second drain electrode 175b.
In some embodiments, a connecting member 194 electrically connects the extension 175c′ of the third drain electrode 175c with the protrusion 134 of the sustain voltage line 131 through the third contact hole 186c. As a result, a part of the data voltage applied to the second drain electrode 175b is divided by the third source electrode 173c so the voltage applied to the second sub-pixel electrode 192l may be lower than the voltage applied to the first sub-pixel electrode 192h.
Here, an area of the second sub-pixel electrode 192l may be one time or more and two times or less of the area of the first sub-pixel electrode 192h.
In some embodiments, in the second passivation layer 185, an opening in which gas discharged from the color filter 230 is collected and a cover which is formed of the same material as the pixel electrode 192 on the opening to cover the opening may be formed. The opening and the cover are components which prevent the gas discharged from the color filter 230 from being transmitted to other elements and may not be essential components.
A lower alignment layer 321 may be formed on the second passivation layer 185 and the pixel electrode 192. The lower alignment layer 321 is an inorganic alignment layer containing an inorganic insulating material and uses silicon oxide (SiOx) in the present exemplary embodiment. Silicon oxide (SiOx) which has various chemical formulas in accordance with a composition ratio of oxygen in silicon oxide (SiOx) may be used. The lower alignment layer 321 formed from silicon oxide (SiOx) may not be formed on a pad unit (not illustrated), which is formed outside the lower insulation substrate to apply a signal to the gate line 121 and the data line 171 through the pad unit.
Microcavities 305 (see
A top surface of the microcavity 305 has a horizontal plane and a side of the microcavity 305 is tapered. The microcavity 305 is a space generated when the sacrificial layer 300 (see
Similarly to the lower alignment layer 321, the upper alignment layer 322 is also an inorganic alignment layer containing an inorganic insulating material and uses silicon oxide (SiOx) in the present exemplary. Silicon oxide (SiOx) which has various chemical formulas in accordance with a composition ratio of oxygen in silicon oxide (SiOx) may be used.
Referring to
A plurality of upper alignment layers 322 is divided with respect to a region 307 (hereinafter, referred to as a “liquid crystal injection hole formation region”) where a liquid crystal injection hole is formed to be formed to be spaced apart from each other. The liquid crystal injection hole formation region 307 is formed in a direction parallel to the gate line 121 and an extension direction of the upper alignment layer 322 is the same as an extension direction of the gate line 121.
As illustrated in the cross-sectional view of
The liquid crystal layer 3 formed in the microcavity 305 is also referred to as a nano crystal. The liquid crystal layer 3 formed in the microcavity 305 may be injected in the microcavity 305 using a capillary force.
A common electrode 270 is disposed on the upper alignment layer 322. The common electrode 270 is formed along a curve of the upper alignment layer 322. A plurality of common electrodes 270 is divided with respect to the liquid crystal injection hole formation region 307 to be formed to be spaced apart from each other. The liquid crystal injection hole formation region 307 is formed in a direction parallel to the gate line 121 and an extension direction of the common electrode 270 is the same as an extension direction of the gate line 121.
The common electrode 270 is formed of a transparent conductive material such as ITO or IZO and generates an electric field together with the pixel electrode 192 to control an arrangement direction of the liquid crystal molecules 310.
A supporting member is formed on the common electrode 270. The supporting member according to the exemplary embodiment of the present disclosure includes a roof layer 360 and an upper insulating layer 370. In some exemplary embodiments, the upper insulating layer 370 may be omitted and the upper insulating layer 370 protects the roof layer 360.
The roof layer 360 is formed on the common electrode 270. The roof layer 360 may support so the microcavity is formed between the pixel electrode 192 and the common electrode 270. The roof layer 360 includes a pillar disposed in the upper portion of the liquid crystal layer 3 and a space between the liquid crystal layers 3. The liquid crystal layer 3 and the microcavity 305 are supported by the pillar of the roof layer 360 to be maintained. The roof layer 360 may be formed of a photo resist and other various organic materials.
The upper insulating layer 370 is formed on the roof layer 360. The upper insulating layer 370 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride oxide (SiOxNy).
A liquid crystal injection hole formation region 307 may be formed in one side of the roof layer 360 and the upper insulating layer 370 to inject the liquid crystal in the microcavity 305. The liquid crystal injection hole formation region 307 includes liquid crystal injection holes which are connected to each microcavity 305. The liquid crystal injection hole is an inlet through which the liquid crystal is injected in the microcavity 305. Further, the liquid crystal injection hole formation region 307 and the liquid crystal injection hole may be used to remove the sacrificial layer to form the microcavity 305.
A capping layer 390 is formed on the upper insulating layer 370 to seal the liquid crystal injection hole formation region 307. The capping layer 390 closes the liquid crystal injection hole formation region 307 and prevents the liquid crystal molecules 310 from flowing outside. The capping layer 390 is, as illustrated in
A polarizer (not illustrated) is disposed below the insulation substrate 110 and above the capping layer 390. The polarizer may include a polarizing element which generates polarization and a TAC (tri-acetyl-cellulose) layer which secures durability and in some exemplary embodiments, an upper polarizer and a lower polarizer may have transmissive axes which are vertical or parallel to each other.
In some embodiments, in
Hereinafter, a manufacturing method of a liquid crystal display according to an exemplary embodiment of the present disclosure will be described with reference to
First,
Thereafter, as illustrated in
That is, a material for forming the semiconductor and the material for forming the data line/source/drain electrode are sequentially deposited. Thereafter, two patterns are simultaneously formed by one process of exposing, developing, and etching using one mask (slit mask or transflective mask). In this case, the semiconductor 154 which is positioned in a channel portion of the thin film transistor is exposed through a slit or transflective region of the mask so as not to be etched. In this case, a plurality of ohmic contacts may be formed on the semiconductors 151, 154, and 155 and between the data line 171 and the source/drain electrode.
The first passivation layer 180 is formed in the entire region of the data conductors 171, 173c, 175a, 175b, and 175c and the exposed portion of the semiconductor 154. The first passivation layer 180 may include an inorganic insulator or an organic insulator such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiOxNy), or silicon oxide (SiOx).
Thereafter, as illustrated in
When the color filter 230 and the light blocking member 220 are formed, the color filter 230 is formed first. The color filter 230 with one color is formed to be long in a vertical direction (data line direction) and the color filters 230 and 230′ with different colors are formed in adjacent pixels in the horizontal direction (gate line direction). As a result, the exposure process, the development process, and the etching process are performed for every color filter 230 with different colors. The liquid crystal display having three primary colors forms the color filters 230 by performing the exposure process, the development process, and the etching process three times. In this case, on the data line 171, a color filter 230′ which is performed earlier is disposed below a color filter 230 which is formed later so as to overlap each other.
When the color filter 230 is etched, the color filter 230 may be removed in advance from the locations where the contact holes 186a, 186b, and 186c are formed.
The light blocking member 220 is formed of a material through which light is not transmitted, on the color filter 230. Referring to a slant portion (indicating the light blocking member 220) of
Referring to
Thereafter, a first contact hole 186a and a second contact hole 186b are formed in the color filter 230, the light blocking member 220 and the passivation layers 180 and 185 to expose the first drain electrode 175a and the extension 175b′ of the second drain electrode 175b. Further, a third contact hole 186c is formed in the color filter 230, the light blocking member 220 and the passivation layers 180 and 185 to expose the protrusion 134 of the sustain voltage line 131 and the extension 175c′ of the third drain electrode 175c.
Thereafter, the pixel electrode 192 which includes the first sub-pixel electrode 192h and the second sub-pixel electrode 192l is formed on the second passivation layer 185. In this case, the pixel electrode 192 may be formed of the transparent conductive material such as ITO or IZO. The first sub-pixel electrode 192h and the second sub-pixel electrode 192l are physically and electrically connected to the first drain electrode 175a and the second drain electrode 175b through the contact holes 186a and 186b. Further, a connecting member 194 which electrically connects the extension 175c′ of the third drain electrode 175c with the protrusion 134 of the sustain voltage line 131 through the third contact hole 186c is formed. As a result, a part of the data voltage applied to the second drain electrode 175b is divided by the third source electrode 173c so the voltage applied to the second sub-pixel electrode 192l may be lower than the voltage which is applied to the first sub-pixel electrode 192h.
Here,
Thereafter, as illustrated in
Thereafter, as illustrated in
First, a process of forming the sacrificial layer 300 will be described. An organic layer such as a photo resist which is a material for the sacrificial layer is deposited on the entire surface of the liquid crystal panel on which the lower alignment layer 321 is formed. Thereafter, the deposited material for the sacrificial layer is patterned to form a structure of the sacrificial layer 300. When an organic layer such as a photo resist is used, the sacrificial layer 300 may be formed by the exposure process and in some exemplary embodiments, may be formed by a separate etching process.
The sacrificial layer 300 extends along the extending direction of the data line 171 to be formed long along the adjacent pixels in a vertical direction. The sacrificial layer 300 is not formed above the data line 171 and adjacent sacrificial layers 300 are spaced apart from each other with a predetermined interval. Further, the sacrificial layer 300 has the same structure as the microcavity 305 which will be formed later. A top surface of the sacrificial layer 300 has a horizontal plane and a side of the sacrificial layer 300 is tapered.
The upper alignment layer 322 is formed on the top surface and a horizontal plane of the sacrificial layer 300 and between the sacrificial layers 300. Similarly to the lower alignment layer 321, the upper alignment layer 322 is an inorganic alignment layer containing an inorganic insulating material and uses silicon oxide (SiOx) in the present exemplary. Silicon oxide (SiOx) which has various chemical formulas in accordance with a composition ratio of oxygen in silicon oxide (SiOx) may be used. A transparent conductive material may be deposited on the upper alignment layer 322 to form the common electrode 270.
Thereafter, as illustrated in
Thereafter, as illustrated in
The upper insulating layer 370 is formed not only on the roof layer 360, but also directly on the common electrode 270 in the opening 361 in which the roof layer 360 is not formed.
Thereafter, as illustrated in
More specifically, as illustrated in
In some exemplary embodiments, the upper insulating layer 370, the common electrode 270 and the upper alignment layer 322 may be etched by the same etching process.
In order to etch the liquid crystal injection hole formation region 307, the photo resist PR is formed on the entire region and the photo resist PR corresponding to the liquid crystal injection hole formation region 307 may be removed to form a photo resist pattern, and then the lower layers are etched along the photo resist pattern to etch the liquid crystal injection hole formation region 307. In this case, as the layer in the liquid crystal injection hole formation region 307 which is etched, the material 370 for the upper insulating layer, the common electrode 270, and the upper alignment layer 322 are etched but the layer below the etched layer is not etched. In some exemplary embodiments, only a part of the sacrificial layer 300 is etched or none of the sacrificial layer 300 is etched. Here, the process of etching the liquid crystal injection hole formation region may be a dry etching process and if there is an etching solution which etches the layer to be etched, a wet etching process may be used.
Thereafter, as illustrated in
Thereafter, as illustrated in
Thereafter, to prevent the liquid crystal layer 3 injected in the microcavity 305 leaking to the outside, a process of forming a capping layer 390 to seal the microcavity 305 may be performed.
In some exemplary embodiments, the upper insulating layer 370 may be omitted.
Further, a process of attaching a polarizer (not illustrated) may be further performed above the lower and upper insulating layers 370 of the insulation substrate 110. The polarizer may include a polarizing element which generates polarization and a TAC (tri-acetyl-cellulose) layer which secures durability and in some exemplary embodiments, an upper polarizer and a lower polarizer may have transmissive axes which are vertical or parallel to each other.
In the liquid crystal display manufactured as described above, the lower alignment layer 321 and the upper alignment layer 322 which enclose the microcavity 305 are formed of the inorganic alignment layer and in this exemplary embodiment of the present disclosure, silicon oxide (SiOx) is used. An example of the inorganic insulating material used as the inorganic alignment layer includes silicon nitride (SiNx), silicon carbide (SiCx), amorphous silicon (a-Si), or FDLC (fluorinated diamond-like carbon) in addition to silicon oxide (SiOx).
As described above, the alignment layer is formed using a process of depositing the insulating layer formed of the inorganic material so that the processing time is shortened as compared with the case where the alignment layer is injected in the microcavity and the alignment layer is uniformly distributed in the microcavity 305.
Hereinafter, a Comparative Example which injects the alignment layer will be described with reference to
First,
In a step of forming the alignment layer in the Comparative Example, as illustrated in
Further, as illustrated in
Additionally, in a display device such as a TV which is used for a long time, the display device may be heated to a high temperature so that the high temperature characteristic is an important factor. Therefore, in the Comparative Example which forms an alignment layer in the microcavity using polyimide PI, the high temperature long-term stability may have a problem. However, when the inorganic alignment layer is deposited as described in the exemplary embodiment of the present disclosure, the above problem may not arise, which will be described with reference to
Referring to
Referring to
According to the exemplary embodiment of
Thereafter, in order to open the pad portion, SF6 and N2 which are etching gases are used to etch the inorganic alignment layer on the pad.
The alignment layer, which is formed to enclose the microcavity using the inorganic alignment layer generated as described above may have a structure illustrated in
When comparing
After performing a step of forming a pixel electrode 192 (referred to as a lower pixel transparent electrode), the silicon oxide (SiOx) is deposited thereon to form the lower alignment layer 321. Here, the lower alignment layer 321 is an inorganic alignment layer and determines an alignment direction of the liquid crystal molecules 310 and is an insulating layer which covers the pixel electrode 192 and functions as a short prevention layer which prevents the pixel electrode 192 from being shorted from other wiring or electrodes. That is, according to the exemplary embodiment, in the liquid crystal display having a microcavity, the pixel electrode 192, and the common electrode 270 approach each other so a short prevention layer is formed on the pixel electrode 192 to prevent the pixel electrode 192 and the common electrode 270 from being shorted. Therefore, according to the exemplary embodiment of the present disclosure, the lower alignment layer 321 also functions as a short prevention layer so that a separate film does not need to be formed.
Thereafter, the sacrificial layer 300 is formed on the lower alignment layer 321. The sacrificial layer 300 corresponds to a microcavity 305 in which the liquid crystal layer 3 will be formed.
Thereafter, silicon oxide (SiOx) is deposited on the lower alignment layer 321 and the sacrificial layer 300 to form the upper alignment layer 322. Here, the upper alignment layer 322 is an inorganic alignment layer to determine an alignment direction of the liquid crystal molecule 310 and also serves as an insulating layer (a second passivation). This is because the inorganic insulating material is used rather than the polyimide PI and the material is used as the insulating layer in the liquid crystal display. Accordingly, in some exemplary embodiments, an additional insulating layer does not need to be formed.
The common electrode 270 (referred to as an upper com transparent electrode) is formed on the upper alignment layer 322 to cover the upper alignment layer 322.
The roof layer 360 is formed on the common electrode 270. To form the roof layer 360, an organic layer such as a photo resist is deposited, exposed, and developed to complete the roof layer 360 having an opening 361.
On the roof layer 360 and in the opening 361, silicon nitride (SiNx) is deposited on the upper insulating layer 370 (referred to as a 3rd passi).
Thereafter, the upper insulating layer 370, the common electrode 270 and the upper alignment layer 322 may be deposited in the opening 361 of the roof layer 360 are etched to form the liquid crystal injection hole formation region 307 and expose the sacrificial layer 300. Specifically, the upper insulating layer 370 may be deposited in the opening 361 of the roof layer 360 by dry-etching and then the common electrode 270 may be wet-etched. Thereafter, the upper alignment layer 322 is dry-etched to expose the sacrificial layer 300. The sacrificial layer 300 exposed by the liquid crystal injection hole formation region 307 is removed by the wet-etching process to form the microcavity 305 and the liquid crystal molecules 310 are injected in the microcavity 305 to complete the liquid crystal layer 3.
The manufacturing method according to the exemplary embodiment of
The inorganic alignment layer may be a vertical alignment layer or a horizontal alignment layer in accordance with the manufacturing process. That is, e-beam is irradiated after depositing the inorganic alignment layer to form the alignment direction. Therefore, the inorganic alignment layer may be a vertical alignment layer or a horizontal alignment layer depending on the e-beam irradiating direction.
Hereinafter, with reference to
First,
The vertical alignment characteristic of the silicon oxide (SiOx) inorganic alignment layer is affected by a thickness of the alignment layer and a change in the thickness is evaluated as illustrated in
During the process of forming the inorganic alignment layer, the vertical alignment characteristic is not showed in a 116 Å condition having a small thickness and the vertical alignment is formed in 713 Å and 1087 Å conditions having a large thickness. Therefore, as an expected result, the vertical alignment characteristic may be improved in accordance with an increase of the thickness of the inorganic alignment layer. As the experimental result, it is checked that the silicon oxide (SiOx) inorganic alignment layer needs to have a thickness of 400 Å or 1000 Å or between about 400 Å and 1000 Å to have the vertical alignment characteristic. In some embodiments, the thickness is about 400 Å, 500 Å, 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å or any range therebetween.
To verify a possibility that the dielectric constant is low, a composition of the SiOx alignment layer is verified by an XPS analysis and the result is illustrated in two graphs in the upper portion of
To investigate a cause why the dielectric constant is increased as the thickness of the silicon oxide (SiOx) inorganic alignment layer increases, a graph obtained by measuring an OH concentration of the inorganic alignment layer by TOF-SIMS is illustrated in
As illustrated in the graph of
As described above, an interrelation of thickness/OH amount/dielectric constant/alignment characteristic of the inorganic alignment layer will be summarized as illustrated in
As illustrated in
Therefore, a vertical alignment characteristic of the inorganic alignment layer may be adjusted by adjusting a thickness of the inorganic alignment layer and a change in the thickness of the inorganic alignment layer causes the change in the OH concentration in the inorganic alignment layer, and thus, a dielectric constant is adjusted. A dielectric constant of the silicon oxide (SiOx) inorganic alignment layer may be 5, 6, or 7 or between about 5 and about 7.
As described above, a main physical property factor which determines the vertical alignment characteristic of the inorganic alignment layer is the dielectric constant and a main process variable for adjusting the dielectric constant is a deposition time, that is, a deposition thickness. Additionally, to confirm a deposition process which can adjust the dielectric constant, as illustrated in
Therefore, the most main factor which adjusts the dielectric constant as the process condition is the inorganic alignment layer thickness, but the power or the amount of SiH4 may slightly affect the change in the dielectric constant.
In some embodiments the inorganic alignment layer has a relatively thick alignment and dielectric constant characteristic to have an acceptable vertical alignment characteristic. However, the correlation between the alignment layer thickness and the dielectric constant, and the vertical alignment force is not investigated. Therefore, to investigate the correlation between the alignment layer thickness and the alignment force, as shown in
As illustrated in
The liquid crystal alignment force in accordance with the thickness of the silicon oxide (SiOx) inorganic alignment layer can be compared by the screen effect, but the vertical alignment forces of the silicon oxide (SiOx) inorganic alignment layer and the polyimide PI alignment layer cannot be compared. Therefore, in order to relatively compare the alignment forces of the silicon oxide (SiOx) inorganic alignment layer and the polyimide (PI) alignment layer, a wedge cell is formed to relatively compare the liquid crystal alignment status.
In
To evaluate the alignment force of an actual panel, after forming the inorganic alignment layer in the actual panel the finger print disappearing time is compared to deduct the result as illustrated in
Hereinafter, a long-term thermal stability of the inorganic alignment layer will be described with reference to
The vertical alignment characteristic of the silicon oxide (SiOx) inorganic alignment layer may be adjusted by a high dielectric constant characteristic of the silicon oxide (SiOx) inorganic alignment layer. However, the high dielectric constant characteristic of the silicon oxide (SiOx) inorganic alignment layer is based on an OH component present in the silicon oxide (SiOx) inorganic alignment layer, so that the thermal instability may be present. Therefore, in order to verify the above, the long-term thermal stability is evaluated as described below.
Under an assumption that after forming the inorganic alignment layer, the thermal treatment is performed for one hour (1 Hr) at 120° C., the change in the dielectric constant is measured and the result is illustrated in
In some embodiments, it is assumed that an operation temperature of the panel is 70° C. and a result which evaluates the stability of the dielectric constant at 70° C. is illustrated in
A described above, as a result that evaluates the long-term thermal stability of the dielectric constant, it is determined that the dielectric constant is slightly reduced in accordance with the evaluation time but the reduced range is small, which does not affect the vertical alignment. In order to actually verify this, an actual panel is manufactured and the long-term thermal stability of the liquid crystal alignment characteristic is evaluated and the result is illustrated in
As illustrated in
To confirm the long-term thermal treatment stability, the actual panel is additionally tested, but a characteristic change (VHR (voltage holding ratio) stability and the change in the liquid crystal response speed) of the polyimide PI alignment layer and the silicon oxide (SiOx) inorganic alignment layer is small before and after the thermal treatment.
Further, it may be confirmed that after the long-term thermal treatment at 312 Hr, as illustrated in
As described above, even when the inorganic alignment layer is used, there is no problem to use the inorganic alignment layer as the vertical alignment layer, the long-term thermal stability is good, the process may be simplified, the manufacturing time is reduced and the pixel electrode 192 is not shorted from other wiring lines and the electrode.
As the inorganic alignment layer, various inorganic materials may be used. In this case, if the silicon oxide (SiOx) is used, the thickness may be between about 400 Å and about 1000 Å and as a composition ratio of the silicon oxide (SiOx), x may have a value of 2.3 or 2.4 or between about 2.3 and about 2.4. Further, the dielectric constant of the silicon oxide (SiOx) inorganic alignment layer may be 5, 6 or 7 or between about 5 and about 7.
A condition when the silicon oxide (SiOx) inorganic alignment layer is deposited may be one of the deposition conditions of
Hereinafter, a structure of the liquid crystal display according to yet another exemplary embodiment of the present disclosure will be described with reference to
The lower insulating layer 350 is etched in the liquid crystal injection hole formation region 307 so as not to be formed therein.
Further, referring to
While this invention has been described in connection with what are presently considered to be practical exemplary embodiments, it will be appreciated by those skilled in the art that various modifications and changes may be made without departing from the scope of the present disclosure. It will also be appreciated by those of skill in the art that parts included in one embodiment are interchangeable with other embodiments; one or more parts from a depicted embodiment can be included with other depicted embodiments in any combination. For example, any of the various components described herein and/or depicted in the Figures may be combined, interchanged or excluded from other embodiments. With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity. Thus, while the present disclosure has described certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Number | Date | Country | Kind |
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10-2013-0053269 | May 2013 | KR | national |