Patent Grant
8184082
1. Technical Field
The present invention relates to a storage capacitor line driving liquid crystal display and a method of driving a liquid crystal display.
2. Related Art
A storage capacitor line driving method is known as one of driving methods of liquid crystal displays. This driving method is configured such that a storage capacitor is provided between a storage capacitor line and a pixel electrode. After a display signal is written in the pixel electrode, if the potential of the storage capacitor line is changed, the potential of the pixel electrode is changed to positive or negative. With this configuration, the dynamic range of the display signal can be reduced, and the liquid crystal display can be driven with low power consumption. Such a storage capacitor line driving liquid crystal display is disclosed in JP-A-2002-196358.
A partial display method is known as one of display methods of liquid crystal displays. In this display method, a partial area of a pixel area serves as a display area where an image is displayed, and a remaining area serves as a non-display area (white or black display area) where no image is displayed.
In the storage capacitor line driving liquid crystal display, when partial display is performed, storage capacitor line driving is stopped in the non-display area, thereby achieving low power consumption. Such a liquid crystal display is disclosed in JP-A-2007-140192.
When storage capacitor line driving is stopped while a polarity signal for deciding the potential level of the storage capacitor line is set at the level for the previous frame, a change of a display area requires a complex operation. As a result, the circuit configuration becomes complicated.
In order to simplify the circuit configuration, in the non-display area, the polarity signal may be fixed at an L level or an H level. In this case, during a transition sequence, such as a transition from a full screen display mode to a partial display mode, a transition from a partial display mode to a full screen display mode, or a change of a display area in a partial display mode, defective display may occur in a first frame depending on the level for the previous frame.
An advantage of some aspects of the invention is that it provides a liquid crystal display and a method of driving a liquid crystal display capable of achieving low power consumption without damaging display quality.
According to an aspect of the invention, there is provided a liquid crystal display that selectively operates in one of a full screen display mode, in which the full screen of the display panel is set as a display area, and a partial display mode, in which a partial area in the full screen is set as a display area and a remaining area is set as a non-display area. The liquid crystal display includes a plurality of gate lines, a plurality of source lines, a plurality of storage capacitor lines that are provided to correspond to the plurality of gate lines, a plurality of pixels that are provided at intersections between the plurality of gate lines and the plurality of source lines, a polarity signal generation circuit that generates a polarity signal corresponding to a frame inversion signal to be repeatedly alternately inverted between a first level and a second level different from the first level frame by frame in the display area, and generates a polarity signal corresponding to a fixed signal fixed at one of the first level and the second level in the non-display area, a storage capacitor line driving circuit that changes the potentials of the storage capacitor lines depending on the polarity signal generated by the polarity signal generation circuit, and a control circuit that changes the display area at a timing according to the frame inversion signal.
With this configuration, storage capacitor line driving can be activated in the display area, and storage capacitor line driving can be stopped in the non-display area. Therefore, the liquid crystal display can be driven with low power consumption. In addition, the display area is changed (a transition sequence is executed) depending on the frame inversion signal (frame polarity). For this reason, in a first frame when a transition sequence is executed, defective display can be suppressed. As such, low power consumption can be achieved without damaging display quality.
In the liquid crystal display according to the aspect of the invention, the control circuit may change the display area in a frame in which the level of the frame inversion signal is different from the fixed signal.
With this configuration, a frame in which a transition sequence is executed can be limited, and thus in a first frame when a transition sequence is executed, it is possible to suppress the occurrence of the problem of storage capacitor line driving being stopped in the display area and storage capacitor line driving being activated in the non-display area. As a result, defective display can be reliably suppressed.
In the liquid crystal display according to the aspect of the invention, the change of the display area may be one of a transition from the full screen display mode to the partial display mode, a transition from the partial display mode to the full screen display mode, and a change of the display area in the partial display mode.
With this configuration, when a transition sequence is executed to change the display area, defective display can be suppressed.
In the liquid crystal display according to the aspect of the invention, the polarity signal generation circuit may include a frame inversion signal generation circuit that generates the frame inversion signal, a memory that stores data for identifying the display area and the non-display area, and a logic circuit that, when data output from the memory indicates the display area, outputs the polarity signal corresponding to the frame inversion signal, and when data output from the memory indicates the non-display area, outputs the polarity signal corresponding to the fixed signal. The control circuit may update data stored in the memory to change the display area.
Therefore, with comparatively simple circuit configuration, the polarity signal to be inverted for each frame can be generated in the display area, and the polarity signal fixed at an L level (or H level) can be generated in the non-display area.
In the liquid crystal display according to the aspect of the invention, the logic circuit may be an AND circuit to which data output from the memory and the frame inversion signal generated by the frame inversion signal generation circuit are applied.
With this configuration, the polarity signal can be generated with simple circuit configuration.
In the liquid crystal display according to the aspect of the invention, each of the pixels may include a pixel switching element that is connected to a corresponding source line, a corresponding gate line, and a corresponding pixel electrode, and when the gate line is selected, allows electricity to be conducted between the pixel electrode and the source line, a pixel capacitor that is interposed between the pixel electrode and a common electrode to which a common potential is applied, and a storage capacitor that is interposed between the pixel electrode and a corresponding storage capacitor line. In the partial display mode, the common potential may be applied to the pixel electrodes of the pixels corresponding to the none display area.
With this configuration, in the non-display area of the partial display mode, the common potential is supplied to perform image display (non-display), and a so-called source write operation to write display signals from the source line driving circuit in the pixels can be stopped. Therefore, in the partial display mode which requires low power consumption, low power consumption can be achieved.
In the liquid crystal display according to the aspect of the invention, a switching element may be provided which is connected to a power supply line for supplying the common potential and the source line, and allows electricity to be conducted between the power supply line and the source line at a predetermined timing. In the non-display area of the partial display mode, the switching element may be controlled for one horizontal scanning period to allow electricity to be conducted between the power supply line and the source line.
Therefore, with comparatively simple circuit configuration, the common potential (non-display signal) can be supplied to the pixels of the non-display area.
According to another aspect of the invention, there is provided a method of driving a liquid crystal display, which selectively operates in one of a full screen display mode, in which the full screen of the display panel is set as a display area, and a partial display mode, in which a partial area in the full screen is set as a display area and a remaining area is set as a non-display area. The liquid crystal display includes a plurality of gate lines, a plurality of source lines, a plurality of storage capacitor lines that are provided to correspond to the plurality of gate lines, and a plurality of pixels that are provided at intersections between the plurality of gate lines and the plurality of source lines. The method comprising generating a polarity signal corresponding to a frame inversion signal to be repeatedly inverted between a first level and a second level frame by frame in the display area, and generating a polarity signal corresponding to a fixed signal fixed at one of the first level and the second level in the non-display area, changing the potentials of the storage capacitor lines depending on the polarity signal, and changing the display area at a timing according to the frame inversion signal.
With this configuration, it is possible to provide a method of driving a liquid crystal display that can achieve low power consumption without damaging display quality.
The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
Hereinafter, an embodiment of the invention will be described with reference to the drawings.
As shown in
The pixel area 100 has a plurality of pixels 110, and 320 rows of gate lines GL and 240 columns of source lines SL extending in a row (X) direction and a column (Y) direction, respectively. The pixels 110 are arranged at intersections between the gate lines GL of the first to 320th rows and the source lines SL of the first to 240th columns. Storage capacitor lines SC extend in the X direction to correspond to the gate lines GL of the first to 320th rows.
In this embodiment, the pixels 110 are arranged in a matrix of 320 rows×240 columns in the pixel area 100, but the invention is not limited to this arrangement.
The liquid crystal display of this embodiment selectively operates in one of a full screen display mode in which the full screen of the pixel area 100 is set as a display area, and a partial display mode in which a partial area of the full screen is set as a display area and a remaining area is set as a non-display area.
In the partial display mode, as shown in
Next, the detailed configuration of each pixel 110 will be described.
In
The other end of the pixel capacitor 12 is connected to a common electrode CE. The common electrode CE is common to all the pixels 110, as shown in
The pixel area 100 is formed by bonding a pair of substrates, that is, an element substrate having formed thereon the pixel electrodes 11 and a counter substrate having formed thereon the common electrode CE, such that the electrode forming surfaces of the substrates face each other with a predetermined gap therebetween, and by filling the gap with liquid crystal. Therefore, the pixel capacitor 12 is formed by each pixel electrode 11 and the common electrode CE with liquid crystal as a kind of dielectric interposed therebetween, and holds a differential voltage between the pixel electrode 11 and the common electrode CE. With this configuration, the amount of light that can be transmitted by the pixel capacitor 12 varies depending on the effective value of the held voltage.
In this embodiment, it is assumed that a normally white mode is set. In the normally white mode, if the effective value of the voltage held in the pixel capacitor 12 approaches zero, transmittance is maximized, and white display is performed, meanwhile, as the effective voltage value increases, the amount of light transmitted decreases, and transmittance is minimized, thereby performing black display.
In the pixel 110 of the first row and first column, one end of the storage capacitor 13 is connected to the pixel electrode 11 (the drain electrode of the TFT 10), and the other end of the storage capacitor 13 is connected to the storage capacitor line SC1 of the first row.
The gate line driving circuit 22 supplies gate signals G1, G2, G3, . . . , and G320 to the gate lines GL of the first, second, third, . . . , and 320th rows during one vertical scanning period (one frame period), respectively. That is, the gate line driving circuit 22 sequentially selects the gate lines GL in order of the first, second, third, . . . , and 320th rows, sets the gate signal to the selected gate line GL at an H level corresponding to a selection voltage, and sets the gate signals to other gate lines GL at an L level corresponding to a non-selection voltage (ground potential Gnd).
The source line driving circuit 20 supplies source signals (display signal) Sig1, Sig2, Sig3, . . . , and Sig240 having voltage levels according to the gray-scale levels of the pixels 110 in the gate line GL selected by the gate line driving circuit 22 to the first, second, third, . . . , and 240th source lines SL.
The source line driving circuit 20 has storage areas (not shown) corresponding to the matrix arrangement of 320 rows×240 columns, and each storage area stores display data assigning the gray-scale level (brightness) of a corresponding one of the pixels 110. Display data stored in each storage area is rewritten when the display content is changed.
For the first to 240th columns in the selected gate line GL, the source line driving circuit 20 executes an operation to read out display data of the pixels 110 in the selected gate line CL from the storage areas, to convert display data to the display signals Sig having voltage levels according to the gray-scale levels with assigned polarities, and to supply the display signals to the source lines SL.
One end of the source line SL is connected to an output terminal of a source driver 201 through a horizontal switch SWH in the source line driving circuit 20. The horizontal switch SWH is switched in accordance with a horizontal scanning signal. If the horizontal switch SWH is turned on, the display signal Sig is supplied from the source driver 201 to the source line SL. In this way, a so-called source write operation is performed to write the display signal Sig from the source line driving circuit 20 in the pixel electrode 11.
The DSG control circuit 21 is supplied with a control signal DSG and the common signal VCOM. As shown in
The control signal DSG is set to be at an H level in the non-display area during the partial display mode. Therefore, in the non-display area, the switch SWS is turned on, the source line SL and the common electrode CE are short-circuited, and thus the common potential LCCOM is supplied to the source line SL. Subsequently, if the TFT 10 is turned on in accordance with the gate signal C from the gate line driving circuit 22, the common potential LCCOM is applied to the pixel electrode 11. In this way, the voltage to be applied to the pixel capacitor 12 is approximately 0 V, and a non-display state is obtained.
Hereinafter, an operation to write the common potential LCCOM from the common electrode driver 211 in the pixel electrode 11 corresponding to the non-display area is referred to as a COM write operation.
The polarity signal generation circuit 24 includes a frame inversion signal generation circuit 241, a memory 242, an AND circuit 243, and a sequence execution determination circuit 244. The sequence execution determination circuit 244 corresponds to a control circuit.
The frame inversion signal generation circuit 241 generates a frame inversion signal POLF indicating a frame polarity to be repeatedly inverted between an H level and an L level frame by frame.
The memory 242 stores data for identifying a display area, in which an image is displayed, and a non-display area, in which no image is displayed, in the pixel area 100 to correspond to each line (each row). The value of data is “1” in the display area, and “0” in the non-display area. The memory 242 may be formed by, for example, a shift register, and holds and shifts data in synchronization with a clock HCLK, which is a pulse signal having a cycle of one horizontal scanning period (1H period).
The frame inversion signal POLF generated by the frame inversion signal generation circuit 241 and data read out from the memory 242 in synchronization with the clock HCLK are input to the two-input AND circuit 243.
When data read out from the memory 242 indicates the display area, that is, the value of data is “1”, the AND circuit 243 outputs the frame inversion signal POLF as a polarity signal POL. When data read out from the memory 242 indicates the non-display area, that is, the value of data is “0”, the output of the AND circuit 243 is fixed at “0”. In this case, the AND circuit 243 outputs the polarity signal POL fixed at “0” (=L level).
Therefore, in the display area, the polarity signal POL corresponding to the frame inversion signal POLF to be inverted for each frame is output, and in the non-display area, the polarity signal POL corresponding to a fixed signal (L level) is output.
The sequence execution determination circuit 244 receives a display area change signal (transition sequence command) and the frame inversion signal POLF, and when a transition sequence command to request a transition sequence, such as a transition from the full screen display mode to the partial display mode, a transition from the partial display mode to the full screen display mode, or a change of the display area in the partial display mode, is input, determines an execution timing of the transition sequence on the basis of the frame inversion signal POLF.
In the sequence execution determination processing, first, in Step S1, it is determined whether or not a transition sequence command to request a transition from the full screen display mode to the partial display mode, a transition from the partial display mode to the full screen display mode, or a change of the display area in the partial display mode is received. When the transition sequence command is not received, the process waits until the transition sequence command is received. When the transition sequence command is received, the process progresses to Step S2.
In Step S2, it is determined whether or not the frame inversion signal POLF is at the L level, and when POLF=H, the process waits until POLF=L. When POLF=L the process progresses to Step S3.
In Step S3, the transition sequence is executed, and data stored in the memory 242 is rewritten.
Therefore, when a transition from the full screen display mode to the partial display mode, a transition from the partial display mode to the full screen display mode, or a change of the display area in the partial display mode is performed, the frame inversion signal POLF is detected, and a corresponding transition sequence is performed for a frame next to a frame in which POLF=L, that is, in a frame in which the level of the frame inversion signal POLF is different from the polarity signal POL (the L level of the fixed signal) in the non-display area.
A signal Vreset is synchronous with a vertical synchronizing signal Vsync and used to reset a read counter of the memory 242.
Next, the configuration of the storage capacitor line driving circuit 23 will be described. For simplification of explanation,
The polarity signal POL output from the polarity signal generation circuit 24 is latched by first and second latch circuits LCH1 and LCH2, which are provided to correspond to the first and second storage capacitor lines SC1 and SC2, on the basis of first and second timing clocks TCLK1 and TCLK2, respectively. The first and second latch circuits LCH1 and LCH2 output and hold the latched polarity signal POL as first and second latch signals POL1 and POL2.
The first and second timing clocks TCLK1 and TCLK2 are created by a timing control circuit 231 on the basis of the gate signals G1 and G2 and a timing control signal TCLK.
The first and second latch signals POL1 and POL2 are used to control switching of first and second switches SW1 and SW2 at a subsequent stage. For example, when the first latch signal POLL is at an H level, a low potential VCOML is applied to the first storage capacitor line SC1, and when the first latch signal POL1 is at an L level, a high potential VCOMH is applied to the first storage capacitor line SC1.
That is, the potentials of the first and second storage capacitor lines SC1 and SC2 are decided by the rising timing of the first and second timing clocks TCLK1 and TCLK2, respectively. In such as storage capacitor line driving method, such a timing is generally after the gate signals G1 and G2 fall.
A transition sequence may be performed in a frame immediately after a transition sequence command is received, regardless of the frame inversion signal POLF, while the sequence execution determination processing is not performed by the sequence execution determination circuit 244. In this case, the frame inversion signal POLF may affect display in a first frame during a transition sequence. This will be described below.
In
During the full screen display mode, in one frame period, the display signals Sig are successively supplied from the source line driving circuit 20 to the source lines SL. Therefore, the display signals are supplied to all the pixel electrodes 11 in the display area, and thus full screen display is performed.
In this case, the memory 242 stores data “1” for all the lines. Therefore, in an n-th frame, when the frame inversion signal POLF generated by the frame inversion signal generation circuit 241 is at the L level, as shown in (b) of
In the n-th frame, if a command (partial ON command) to request a transition from the full screen display mode to the partial display mode is received, and data of the memory 242 corresponding to each line of the non-display area is rewritten from “1” to “0”, the display mode is switched to the partial display mode in an (n+1)th frame.
As described above, according to this embodiment, since frame inversion driving is performed, as shown in (b) of
As shown in (c) of
In this case, a source write operation to write the display signals Sig from the source line driving circuit 20 in the pixel electrodes 11 corresponding to the display area is performed. In the non-display area, the control signal DSG is maintained at the H level, and a COM write operation to write the common potential LCCOM from the common electrode driver 211 in the pixel electrode 11 corresponding to the non-display area is performed.
In the n-th frame, an area A is set as a display area, and an area B is set as a non-display area. In this case, in the memory 242, data “1” is stored with respect to the lines corresponding to the area A, and data “0” is stored with respect to the lines corresponding to the area B.
Therefore, in the n-th frame, when the frame inversion signal POLF is at the L level, as shown in (b) of
In the n-th frame, if a command to request a change of a display area in a partial display mode (area change command) is received, data in the memory 242 corresponding to the lines of a new display area (area C) is rewritten to “1”, and data in the memory 242 corresponding to the lines of a new non-display area (area D) is rewritten to “0”, the display area is switched from the area A to the area C in the (n+1)th frame.
Therefore, as shown in (b) of
As shown in (c) of
In the n-th frame, an area A is set as a display area, and an area B is set as a non-display area. In this case, in the memory 242, data “1” is stored with respect to the lines corresponding to the area A, and data “0” is stored with respect to the lines corresponding to the area B.
Therefore, in the n-th frame, when the frame inversion signal POLF is at the L level, as shown in (b) of
In the n-th frame, if a command to request a transition from the partial display mode to the full screen display mode (normal ON command) is received, and data in the memory 242 corresponding to the lines of the area B is rewritten from “0” to “1”, the display mode is switched to the full screen display mode in the (n+1)th frame.
Therefore, as shown in (b) of
Next, a change of a pixel potential by storage capacitor line driving will be described with reference to
After the display signal is written in the pixel electrode 11 through the source line SL, if storage capacitor line driving (capacitance swing) is performed, the dynamic range of the display signal can be reduced, and thus the liquid crystal display can be driven with low power consumption. Meanwhile, after the display signal is written in the pixel electrode 11 through the source line SL, if storage capacitor line driving is not performed, a write operation may not be sufficiently performed, and an adverse effect on display may occur.
In contrast, as shown in
As such, if storage capacitor line driving is stopped when the display area is driven, or if storage capacitor line driving is activated when the non-display area is driven, an adverse affect on display may be caused.
When the display mode is switched from the full screen display mode to the partial display mode, as shown in (b) of
When a display area is changed in the partial display mode, as shown in (b) of
When the display mode is switched from the partial display mode to the full screen display mode, as shown in (b) of
If a transition sequence is executed in a frame in which the level of the frame inversion signal POLF corresponds to the polarity signal POL (L level) in the non-display area, an NG operation is performed, and defective display may occur.
In this embodiment, the sequence execution determination processing is performed by the sequence execution determination circuit 244, and a frame in which a transition sequence is executed is limited in accordance with the frame inversion signal POLF.
The operation of the liquid crystal display of this embodiment will be described.
In the n-th frame, data “1” is stored in the memory 242 with respect to all the lines. In this case, if it is assumed that the frame inversion signal POLF is at the L level, the polarity signal POL=L for all the lines.
In the n-th frame, if the partial ON command is received, in the sequence execution determination processing of
In this way, data of the memory 242 corresponding to the lines of the nondisplay area in the partial display mode is rewritten from “1” to “0”, and the display mode is switched to the partial display mode from the (n+1)th frame.
Therefore, in the (n+1)th frame and later, the level of the polarity signal POL changes in the manner H→L→H→ . . . with respect to the lines corresponding to the display area frame by frame, and the polarity signal POL is fixed at the L level with respect to the lines corresponding to the non-display area.
In this case, in the (n+1)th frame (a first frame after the transition sequence is executed), an OK operation is performed such that the polarity signal POL is inverted in the display area, and the polarity signal POL is not inverted in the non-display area.
In the n-th frame, data “1” is stored in the memory 242 for all the lines. For this reason, in the n-th frame, the polarity signal POL=H for all the lines.
If the partial ON command is received in the n-th frame, in the sequence execution determination processing of
Therefore, in the (n+1)th frame, the full screen display mode is continuous. In the (n+1)th frame, the frame inversion signal POLF is inverted to the L level, and thus the polarity signal POL=L for all the lines.
In this case, the sequence execution determination circuit 244 determines Yes in Step S2, and the process progresses to Step S3. Thus, data in the memory 242 is rewritten. In this way, data of the memory 242 corresponding to the lines of the non-display area in the partial display mode is rewritten from “1” to “0”, and the display mode is switched to the partial display mode from the (n+2)th frame.
Therefore, in the (n+2)th frame and later, the level of the polarity signal POL changes in the manner H→L→H→ . . . with respect to the lines corresponding to the display area frame by frame, and the polarity signal POL is fixed at the L level with respect to the lines corresponding to the non-display area.
In this case, in the (n+2) frame (a first frame after the transition sequence is executed), an OK operation is performed such that the polarity signal POL is inverted in the display area, and the polarity signal POL is not inverted in the non-display area.
In this way, the frame inversion signal POLF is detected, and the transition sequence is executed in a frame next to a frame in which the frame inversion signal POLF is at the L level. Therefore, occurrence of the above NG operation can be suppressed, and defective display can be suppressed.
Similarly, in the case of the change of the display area in the partial display mode and the transition from the partial display mode to the full screen display mode, if the frame inversion signal POLF is detected, and the transition sequence is executed in a frame next to a frame in which the frame inversion signal POL, is at the L level, defective display can be suppressed.
As described above, according to the embodiment, a polarity signal at a level corresponding to a frame inversion signal to be repeatedly inverted between the H level and the L level frame by frame is generated in the display area, and a polarity signal at a level corresponding to a fixed signal fixed at an L level is generated in the non-display area. The potential of the storage capacitor line is switched depending on the polarity signal. Therefore, storage capacitor line driving can be activated in the display area, and storage capacitor line driving can be stopped in the non-display area. As a result, the liquid crystal display can be driven with low power consumption.
When a transition sequence command is received, a transition sequence is executed at the timing according to the frame inversion signal. Therefore, defective display in the first frame when the transition sequence is executed can be suppressed.
As such, low power consumption can be achieved without damaging display quality.
When the transition sequence command is received, the transition sequence is executed in a frame next to a frame in which the frame inversion signal becomes the L level. Therefore, a frame in which the transition sequence is executed is limited, and in the first frame when the transition sequence is executed, it is possible to suppress the occurrence of the problem of storage capacitor line driving being stopped in the display area and storage capacitor line driving being activated in the non-display area. As a result, defective display can be reliably suppressed.
The transition sequence command is one of a partial ON command to request a change from a full screen display mode to a partial display mode, a normal ON command to request a change from a partial display mode to a full screen display mode, and an area change command to request a change of a display area in a partial display mode. Therefore, when the transition sequence is executed, defective display can be suppressed.
A polarity signal generation circuit includes a frame inversion signal generation circuit, a memory, and an AND circuit. Therefore, with a comparatively simple circuit configuration, a polarity signal to be inverted for each frame can be generated in the display area, and a polarity signal fixed at the L level can be generated in the non-display area.
In the partial display mode, a common potential is supplied to perform image display (non-display) in the non-display area. Therefore, a source write operation to write display signals from the source line driving circuit in the pixel electrodes 11 can be stopped. As a result, in the partial display mode which requires low power consumption, low power consumption can be achieved.
A switching element is provided which is connected to a power supply line for supplying a common potential and a source line, and allows electricity to be conducted between the power supply line and the source line at a predetermined timing. In the non-display area of the partial display mode, the switching element is controlled for one horizontal scanning period to allow electricity to be conducted between the power supply line and the source line. Therefore, with a comparatively simple circuit configuration, a COM write operation for supplying the common potential to the pixel electrode 11 of the non-display area can be performed.
In the foregoing embodiment, a case in which the polarity signal POL of the non-display area is fixed at the L level by the polarity signal generation circuit 24 has been described, but the polarity signal POL of the non-display area may be fixed at the H level. In this case, in Step S2 of
In the foregoing embodiment, a case in which the polarity signal generation circuit 24 includes the frame inversion signal generation circuit 241, the memory 242, and the AND circuit 243 has been described, any configuration may be used insofar as the polarity signal POL is inverted in the display area for each frame, and the polarity signal POL is fixed at the L level (or the H level) in the non-display area.
The entire disclosure of Japanese Patent Application NO. 2008-042508 filed Feb. 25, 2008 is expressly incorporated by reference herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-042508 | Feb 2008 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 7091946 | Tsutsui et al. | Aug 2006 | B2 |
| 20060208985 | Hwang et al. | Sep 2006 | A1 |
| 20060208992 | Akutsu et al. | Sep 2006 | A1 |
| Number | Date | Country |
|---|---|---|
| A-2002-196358 | Jul 2002 | JP |
| A-2004-12891 | Jan 2004 | JP |
| A-2007-140192 | Jun 2007 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20090213058 A1 | Aug 2009 | US |
