LIQUID CRYSTAL DISPLAY APPARATUS AND DRIVING METHOD THEREOF

Abstract

A liquid crystal display (LCD) apparatus and method for automatically sensing and compensating a delay time of a gate signal fed to the LCD display panel. The LCD panel includes a signal converter for generating a power clock signal, a delay controller for generating a delay control signal corresponding to the delay value of the gate signal by comparing the power clock signal with a signal derived from the data lines, and a pixel voltage signal generator for supplying a pixel voltage signal to the data lines of the LCD panel in response to the delay control signal.

Description

BRIEF DESCRIPTION OF THE DRAWING

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when read together with the accompanying drawings in which:

FIG. 1 is a waveform chart illustrating a gate signal and a pixel voltage signal supplied respectively to a gate line and a data line of a conventional LCD apparatus;

FIG. 2 is a diagram for describing a ghost defect occurring in a conventional LCD panel;

FIG. 3 is a block diagram illustrating an LCD apparatus according to the present invention;

FIG. 4 is a diagram illustrating another exemplary embodiment of a driver for generating a delay control signal shown in FIG. 3;

FIG. 5 is a waveform chart for describing an operating process of a delay control generator using a clock generator shown in FIG. 4;

FIG. 6 is a diagram illustrating a first exemplary embodiment of an LCD panel shown in FIG. 3;

FIG. 7 is a diagram illustrating a second exemplary embodiment of the LCD panel shown in FIG. 3;

FIG. 8 is a diagram illustrating a first exemplary embodiment of a delay controller connected to a gate driver shown in FIG. 3;

FIG. 9 is a diagram illustrating a second exemplary embodiment of the delay controller connected to the gate driver shown in FIG. 3; and

FIG. 10 is a waveform chart for describing a driving method of the LCD apparatus according to the present invention.

Claims

1. A liquid crystal display (LCD) apparatus, comprising: an LCD panel including m data lines and n gate lines (where m and n are natural numbers) that intersect each other;a gate driver for supplying a gate signal to the gate lines of the LCD panel;a signal converter for generating a power clock signal to be applied to the gate driver;a delay controller for generating a delay control signal corresponding to a delayed value of the power clock signal; anda pixel voltage signal generator for supplying a pixel voltage signal to the data lines of the LCD panel in response to the delay value of the delay control signal.

2. The LCD apparatus as set forth in claim 1, wherein the delay controller compares a power clock signal with a gate signal supplied to at least any one of the n gate lines.

3. The LCD apparatus as set forth in claim 1, wherein the gate signal supplied to at least any one of the n gate lines is fed back to the delay controller.

4. The LCD apparatus as set forth in claim 1, wherein the delay controller counts the time between the power clock signal applied to the gate driver and a signal fed back from one of the n gate lines.

5. The LCD apparatus as set forth in claim 1, further comprising a data driver for driving the m data lines.

6. The LCD apparatus as set forth in claim 5, wherein the data driver comprises: k bus lines (where k is a natural number) for supplying k pixel voltage signals to the m data lines that are divided in blocks each having k data lines;a plurality of shift registers for generating a sampling control signal corresponding to each block; andk sampling switches for connecting the k bus lines to the k data lines of a corresponding block in response to the corresponding sampling control signal.

7. The LCD apparatus as set forth in claim 5, wherein the data driver comprises: a bus line for supplying a pixel voltage signal to be supplied to the plurality of data lines;a plurality of shift registers for generating a sampling control signal corresponding to each data line and sequentially supplying the sampling control signal; andm sampling switches for connecting the bus line to a corresponding data line in response to the sampling control signal.

8. The LCD apparatus as set forth in claim 5, wherein at least one of the gate driver and the data driver is formed by using a polysilicon thin film transistor.

9. A method of driving an LCD display having gate lines and data lines, comprising the steps of: generating a power clock signal;applying the power clock signal to a shift register to drive a gate line of the LCD panel;generating a delay control signal by comparing the power clock signal with the signal applied to a gate line; andsupplying a pixel voltage signal to a data line of the LCD panel in response to the delay control signal.

10. The method as set forth in claim 9, wherein the signal derived from a gate line is a signal fed back to the delay controller from the shift register.

11. The method as set forth in claim 9, wherein the step of supplying a pixel voltage signal comprises the steps of: supplying k pixel voltage signals (where k is a natural number) supplied to m data lines (where m is a natural number) of the LCD panel that are divided in blocks each having k data lines;generating a sampling control signal corresponding to each block; andsampling k data signals in response to the sampling control signal.

12. The method as set forth in claim 9, wherein the step of supplying a pixel voltage signal comprises the steps of: sequentially supplying a data signal to be supplied to m data lines (where m is a natural number) of the LCD panel to a bus line;generating a sampling control signal corresponding to each data line; andsequentially sampling m pixel voltage signals in response to the sampling control signal.