Patent Grant
9847065
This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0008243, filed on Jan. 16, 2015, in the Korean intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The present inventive concept relates to a liquid crystal display apparatus.
A liquid crystal display apparatus such as a flat panel display apparatus includes two sheets of display plates on which electric field generation electrodes such as a pixel electrode and a common electrode are formed and a liquid crystal layer disposed between the two sheets of display plates. The liquid crystal display apparatus applies a voltage to the electric field generation electrodes to generate electric fields in the liquid crystal layer. Thus, alignment of liquid crystal molecules of the liquid crystal layer is determined by the electric fields to control a polarization of incident light, and thus, an image is displayed.
The liquid crystal display apparatus may be driven in various modes. For example, the liquid crystal display apparatus may be driven in a horizontal electric mode, such as an in-plane switching (IPS) mode, a plane line switching (PLS) mode, or the like, in which liquid crystals are driven by horizontal electric fields.
When the liquid crystal display apparatus is driven in the PLS mode, variation of a gray scale may be realized by rotating horizontally aligned liquid crystal molecules by electric fields applied between the pixel electrode and the common electrode.
A flexoelectric effect may occur when a liquid crystal injected into a wedge type cell or the wedge type cell is deformed. The liquid crystal may be polarized due to a flexoelectric effect generated when alignment of the liquid crystal is deformed in a liquid crystal display apparatus driven in the PLS mode, in which electric fields are applied to liquid crystal molecules and the liquid crystal molecules are aligned in an electric field direction.
When the liquid crystal in the liquid crystal display apparatus has the flexoelectric effect, even though a polarity of a voltage of the pixel electrode with respect to a voltage of the common electrode voltage is periodically inverted, the polarization of the liquid crystal due to the flexoelectric effect might not be inverted in polarity. Thus, optical transmittance may be different for each pixel according to the polarity of the voltage of the pixel electrode with respect to the voltage of the common electrode. Thus, the liquid crystal display apparatus may have different brightness in each frame to cause flicker and afterimage phenomena on a screen, and thus, image quality of the liquid crystal display apparatus may deteriorate.
According to an exemplary embodiment of the present inventive concept, a display apparatus is provided. The display apparatus includes a display panel and a driving circuit. The display panel includes a plurality of pixels. Each of the plurality of pixels is connected to one of a plurality of gate lines and one of a plurality of data lines. The driving circuit is configured to drive the plurality of gate lines and the plurality of data lines to display an image on the display panel. The driving circuit is configured to alternately provide a first polarity data driving signal and a second polarity data driving signal to each of the plurality of data lines. During an asymmetrical mode, the first polarity data driving signal is provided to first data lines of the plurality of data lines during a first frame period before a blank period begins, and the second polarity data driving signal is provided to the first data lines during a second frame period after the blank period ends. The second frame period during which the second polarity data driving signal is provided to the first data lines excludes the blank period.
The plurality of data lines may include the first data lines and second data lines. The driving circuit may include a first gate driver and a second gate driver. The first gate driver may be configured to drive first gate lines of the gate lines. The first gate lines and the first data lines may be connected to first pixels of the pixels. The second gate driver may be configured to drive second gate lines of the gate lines. The second gate lines and the second data lines may be connected to second pixels of the pixels.
When the first polarity data driving signal is provided to each of the first data lines, the second polarity data driving signal may be provided to each of the second data lines.
The first frame period in which the first polarity data driving signal is provided to the first data lines during the asymmetrical mode may be longer than a first frame period in which the first polarity data driving signal is provided to the first data lines during a normal mode.
The second frame period in which the second polarity data driving signal is provided to the first data lines during the asymmetrical mode may be shorter than a second frame period in which the second polarity data driving signal is provided to the first data lines during the normal mode.
The first frame period in which the first polarity data driving signal is provided to the first data lines during the asymmetrical mode may include the blank period.
The first and second polarity driving signals may have opposite polarities to each other with respect to a common voltage.
The driving circuit may further include a voltage generator generating the common voltage.
The driving circuit may further include a timing controller and a source driver. The timing controller may be configured to output a first control signal including a data signal. The first control may be output in response to an image signal and a control signal. The source driver may be configured to output the first polarity data driving signal and the second polarity data driving signal in response to the data signal and the first control signal.
The timing controller may output a second control signal for controlling the first gate driver in response to the control signal, and a third control signal for controlling the second gate driver in response to the control signal.
The timing controller may further output a fourth control signal. The voltage generator may adjust a voltage level of the common voltage in response to the fourth control signal.
According to an exemplary embodiment of the present inventive concept, a display apparatus is provided. The display apparatus includes a display panel and a driving circuit. The display panel includes first pixels and second pixels. Each of the first pixels is connected to one of first gate lines and one of first data lines. Each of the second pixels is connected to one of second gate lines and one of second data lines. The driving circuit is configured to drive the first and second gate lines and the first and second data lines. The driving circuit is configured to provide a first polarity data driving signal to each of the first pixels, and to provide a second polarity data driving signal to each of the second pixels in a first period. The driving circuit is configured to provide the second polarity data driving signal to each of the first pixels, and to provide the first polarity data driving signal to each of the second pixels in a second period. During an asymmetrical mode, a first frame in which the first polarity data driving signal is provided to each of the first pixels has a different period from that of a second frame in which the second polarity data driving signal is provided to each of the first pixels.
The first frame may include a blank period. The first polarity data driving signal may be provided to each of the first pixels before the blank period begins, and the second polarity data driving signal may be provided to each of the first pixels after the blank period ends.
The first and second polarity driving signals may have opposite polarities to each other with respect to a common voltage. The driving circuit may include a voltage generator adjusting a voltage level of the common voltage.
During an asymmetrical mode, an amount of difference in period between the first frame and the second frame may be changed according to the adjusted voltage level of the common voltage.
The first frame in which the first polarity data driving signal is provided to each of the first pixels during the asymmetrical mode may have a longer period than that of a third frame in which the first polarity data driving signal is provided to each of the first pixels during a normal mode.
A fourth frame in which the second polarity data driving signal is provided to each of the first pixels during the asymmetrical mode may have a shorter period than a fifth frame in which the second polarity data driving signal is provided to each of the second pixels during the normal mode.
The above and other features of the present inventive concept will become more apparent with reference to the following figures, in which:
Hereinafter, exemplary embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings.
Referring to
The display panel 110 includes a plurality of data lines DL1 to DLm, a plurality of first gate lines GL11 to GL1n, and a plurality of second gate lines GL21 to GL2n. The first and second gate lines GL11 to GL1n and GL21 to GL2n are arranged to cross the data lines DL1 to DLm. The display panel 110 further includes a plurality of pixels PX11 to PXnm, each of which is arranged on an area on which each of the data lines DL1 to DLm and each of the gate lines GL11 to GL1n and GL21 to GL2n cross each other. Here, n and m are positive integers. The plurality of first gate lines GL1 to GLn extend from the first gate driver 122 in a first direction X1 and are spaced apart from each other in a second direction X2. The plurality of second gate lines GL21 to GL2n extend from the second gate driver 124 in a third direction X1 and are spaced apart from each other in the second direction X2. The third direction X1′ is substantially opposite to the first direction X1. The plurality of data lines DL1 to DLm extend from the source driver 123 in the second direction X2 and are spaced apart from each other in the first direction X1. The data lines DL1 to DLm and the first and second gate lines GL11 to GL and GL2 to GL2n are electrically insulated from each other.
As illustrated in
The timing controller 121 receives an image signal RGB and a control signal CTRL, which are provided from the outside. The timing controller 121 provides a first control signal CONT1 to the source driver 123, a second control signal CONT2 to the first gate driver 122, a third control signal CONT3 to the second gate driver 124, and a fourth control signal CONT4 to the voltage generator 125. The first control signal CONT1 may include a data signal and a clock signal. The first control signal CONT 1 may further include a polarity control signal and a load signal.
The source driver 123 drives the plurality of data lines DL1 to DLm in response to the first control signal CONT1 outputted from the timing controller 121. The source driver 123 may be realized as an independent integrated circuit. Thus, the source driver 123 may be electrically connected to a side of the display panel 110, or directly mounted on the display panel 110. In addition, the source driver 123 may be realized as a single chip or may include a plurality of chips. In an exemplary embodiment, the source driver 123 may change output timing of a data driving signal provided to the data lines DL1 to DLm.
The first gate driver 122 drives the first gate lines GL11 to GL1n in response to the second control signal CONT2 outputted from the timing controller 121. The second gate driver 124 drives the second gate lines GL21 to GL2n in response to the third control signal CONT3 outputted from the timing controller 121.
The first gate driver 122 may be realized as an independent integrated circuit chip. Thus, the first gate driver 122 may be electrically connected to one side (e.g., a left side of the display panel 110 of
The voltage generator 150 generates a common voltage VCOM in response to the fourth control signal CONT4 outputted from the timing controller 121. The voltage generator 150 may change a voltage level of the common voltage VCOM according to the fourth control signal CONT4. The voltage generator 150 may further generate various voltages that are required for operating the liquid crystal display apparatus 100 in addition to the common voltage VCOM.
When a gate-on voltage is applied to a certain gate line GLi, a switching transistor TR of each of the one row pixels PXi1 to PXim that are connected to the gate line GLi is turned on. Here, the source driver 123 provides data driving signals corresponding to data signals included in the first control signal CONT1 to the data lines DL1 to DLm. The data driving signals provided to the data lines DL1 to DLm may be respectively applied to corresponding pixels (e.g., PXi1 to PXim) through the switching transistor TR that is turned on. Here, a time that is taken to turn on one of row switching transistors TRs, which correspond to, e.g., the pixels PXi1 to PXim, respectively, is referred to as ‘1 horizontal period 1H’.
The source driver 123 of the liquid crystal display apparatus 100 inversely drives the data driving signals provided to the data lines DL1 to DLm to prevent the liquid crystal capacitor CLC from being degraded. For example, a polarity of a voltage of the pixel electrode with respect to the common voltage VCOM of the liquid crystal capacitor CLC is periodically inverted. When the liquid crystal capacitor CLC has a flexoelectric effect, polarization of the liquid crystal due to the flexoelectric effect might not be inverted according to the inverted voltage polarity of the pixel electrode with respect to the common voltage VCOM. Thus, optical transmittance in each pixel may be different according to the polarity of the voltage of the pixel electrode with respect to the common voltage VCOM.
Referring to
Referring to
Two data lines of the data lines DL1 to DL12 are arranged between two adjacent pixels in the first direction X1. For example, the data lines DL2 and DL3 are arranged between the pixels PX11 and PX12, and the data lines DL4 and DL5 are arranged between the pixels PX12 and PX13. The pixels PX11 and PX31 are connected to the data line DL1. The pixels PX21 and PX41 are connected to the data line DL2. The pixels PX22 and PX42 are connected to the data line DL3. The pixels PX 12 and PX32 are connected to the data line DL4.
When a positive data driving signal (+) is provided to the odd-order data lines DL1, DL3, DL5, and DL7 of the data lines DL1 to DL12 and a negative data driving signal (−) is provided to the even-order data lines DL2, DL4, DL6, and DL8 of the data lines DL1 to DL12, the pixels PX11 to PX46 of the display panel 110 may be driven in a dot inversion method.
When the pixels (e.g., PX11, PX13, PX15, PX22, PX24, PX26, PX31, PX33, PX35, PX42, PX44, and PX46), each of which is connected to one of the first gate lines (e.g., GL11 and GL12) driven by the first gate driver 122, is driven by the positive data driving signal (+), the pixels (e.g., PX12, PX14, PX16, PX21, PX23, PX25, PX32, PX34, and PX36), each which is connected to one of the second gate lines (e.g., GL21 and GL22) driven by the second gate driver 124, may be driven by the negative data driving signal (−). In addition, when the pixels (e.g., PX11, PX13, PX15, PX22, PX24, PX26, PX31, PX33, PX35, PX42, PX44, and PX46) is driven by the negative data driving signal (−), the pixels (e.g., PX12, PX14, PX16, PX21, PX23, PX25, PX32, PX34, and PX36) may be driven by the positive data driving signal (+).
For example, in a first frame, the pixels each connected to one of the first gate lines driven by the first gate driver 122 may be driven by the positive data driving signal (+) and the pixels each connected to one of the second gate lines driven by the second gate driver 124 may be driven by the negative data driving signal (−), and in a second frame subsequent to the first frame, the pixels each connected to one of the first gate lines driven by the first gate driver 122 may be driven by the negative data driving signal (−) and the pixels each connected to one of the second gate lines driven by the second gate driver 124 may be driven by the positive data driving signal (+).
Referring to
A negative frame period FN1 and a positive frame period FP1 of the first gate signals G11 to G1n have the same length as each other during a normal mode. In addition, a time duration TN1, in the negative frame period FN1, between an activation time (e.g., a rising time) of a first one G11 of the first gate signals G11 to G1n and an activation time (e.g., a rising time) of the last one G1n of the first gate signals G11 to G1n may be the same as a time duration TP1, in the positive frame period FP1, between an activation time of the first one G11 of the first gate signals G11 to G1n and the last one G1n of the first gate signals G11 to G1n.
In addition, the negative frame period FN2 and the positive frame period FP2 of the second gate signals G21 to G2n have the same length as each other during the normal mode. In addition, a time duration TN2, in the negative frame period FN2, between an activation time (e.g., a rising time) of a first one G21 of the second gate signals G21 to G2n and an activation time (e.g., a rising time) of the last one G2n of the second gate signals G21 to G2n may be the same as a time duration TP2, in the positive frame period FP2, between an activation time of the first one G21 of the second gate signals G21 to G2n and an activation time of the last one G2n of the second gate signals G21 to G2n.
As illustrated in
The timing controller of
Referring to
The negative frame period FN1 of the first gate signals G11 to G1n during the asymmetrical mode is shorter than the negative frame period FN1 of the first gate signals G11 to G1n during the normal mode. The positive frame period FP1 of the first gate signals G11 to G1n during the asymmetrical mode is longer than the positive frame period FP1 of the first gate signals G11 to G1n during the normal mode.
In addition, the negative frame period FN2 and the positive frame period FP2 of the second gate signals G21 to G2n have different lengths from each other during the asymmetrical mode. In addition, the time duration TN2, in the negative frame period FN2, between an activation time (e.g., a rising time) of the first one G21 of the second gate signals G21 to G2n and an activation time (e.g., a rising time) of the last one G2n of the second gate signals G21 to G2n may be the same as the time duration TP2, in the positive frame period FP2, between an activation time of the first one G21 of the second gate signals G21 to G2n and an activation time of the last one G2n of the second gate signals G21 to G2n.
The negative frame period FN2 of the second gate signals G21 to G2n during the asymmetrical mode is shorter than the negative frame period FN2 of the second gate signals G21 to G2n during the normal mode. The positive frame period FP2 of the second gate signals G21 to G2n during the asymmetrical mode is longer than the positive frame period FP2 of the second gate signals G21 to G2n during the normal mode.
Referring to
Although
Referring to
During the asymmetrical mode, a maximum voltage level VP of the positive data driving signal (+) and a maximum voltage level VN of the negative data driving signal (−) are different from each other (e.g., VP*VN) with respect to the common voltage VCOM.
Referring to
The positive frame period FP1 during the asymmetrical mode may include a blank period for which the gate lines are not driven. The blank period may correspond to a period until the negative frame period FN1 starts after the last one G1n of the first gate signals G11 to G1n is activated. The positive data driving signal (+), which is provided to a corresponding one of the pixels PX11 to PXnm through a corresponding one of the data lines DL1 to DLm, is maintained during the blank period. When the common voltage VCOM is adjusted toward the positive data driving signal (+), the positive frame period FP1 has a length longer than that of the negative frame period FN1 to compensate the adjusted common voltage VCOM.
Referring to
During the asymmetrical mode, a maximum voltage level VP of the positive data driving signal (+) and a maximum voltage level VN of the negative data driving signal (−) are different from each other (e.g., VP*VN) with respect to the common voltage VCOM.
Referring to
The positive frame period FP2 during the asymmetrical mode may include a blank period for which the gate lines are not driven. The blank period may correspond to a period until the negative frame period FN2 starts after the last one G2n of the second gate signals G21 to G2n is activated. The positive data driving signal (+), which is provided to a corresponding one of the pixels PX11 to PXnm through a corresponding one of the data lines DL1 to DLm is maintained during the blank period. When the common voltage VCOM is adjusted toward the positive data driving signal (+), the positive frame period FP2 has a length longer than that of the negative frame period FN2 to compensate the adjusted common voltage VCOM.
Referring to
Each of the data lines DL1 to DL7 is disposed between every two adjacent pixels in the first direction X1. Each of the pixels PX21 and PX41 is connected to the left data line DL2 adjacent thereto.
When a positive data driving signal (+) is provided to the odd-order data lines DL1, DL3, DL5, and DL7 of the data lines DL1 to DL12 and a negative data driving signal (−) is provided to the even-order data lines DL2, DL4, and DL6 of the data lines DL1 to DL12, the pixels PX11 to PX46 of the display panel 110 may be driven in a dot inversion method.
The pixels (e.g., PX11, PX13, PX15, PX22, PX24, PX26, PX31, PX33, and PX35), each of which is connected to a corresponding one of the first gate lines (e.g., GL11, GL12, GL13, and G14) driven by the first gate driver 122, may be driven by the positive data driving signal (+), and the pixels (e.g., PX12, PX14, PX16, PX21, PX23, PX25, PX32, PX34, and PX36), each of which connected to the second gate lines GL21, GL22, GL23, and GL24 driven by the second gate driver 124, may be driven by the negative data driving signal (−). In an exemplary embodiment, the pixels (e.g., PX11, PX13, PX15, PX22, PX24, PX26, PX31, PX33, and PX35) may be driven by the negative data driving signal (−), and the pixels (e.g., PX12, PX14, PX16, PX21, PX23, PX25, PX32, PX34, and PX36) may be driven by the positive data driving signal (+).
In the display panel 110 of
In the liquid crystal display apparatus according to an exemplary embodiment of the present inventive concept, a voltage level of the common voltage may be adjusted, and thus, the positive frame in which the pixel electrode has a voltage greater than that of the common electrode and the negative frame in which the pixel electrode has a voltage smaller than that of the common electrode may have the same light transmittance as each other. To compensate the adjusted common voltage, a period of each of the positive frame and the negative frame may be changed. Therefore, display quality of the liquid crystal display apparatus may be increased.
Although the present inventive concept has been described with exemplary embodiments thereof, it will be understood that the present inventive concept is not limited to exemplary embodiments set forth herein, and various changes in forms and details may be made therein without departing from the spirit and scope of the present inventive concept.
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| 10-2015-0008243 | Jan 2015 | KR | national |
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