BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing a pixel unit of the liquid crystal display according to the prior art.
FIG. 2 is a timing diagram showing scan signals on the scan lines depicted in FIG. 1.
FIG. 3 illustrates a relationship of voltages applied on the pixel electrode An and the pixel electrode Bn of the pixel unit depicted in FIG. 1.
FIG. 4 is a circuit diagram of a liquid crystal display according to a first embodiment of the present invention.
FIG. 5 is a timing diagram showing a scan signal generated by the gate driver depicted in FIG. 4.
FIG. 6 illustrates a relationship of voltages applied on the first pixel electrode PAn and the second pixel electrode PBn of the pixel unit depicted in FIG. 4.
FIG. 7 is a circuit diagram of a liquid crystal display according to a second embodiment of the present invention.
FIG. 8 is a timing diagram showing scan signals generated by the gate driver depicted in FIG. 7.
FIG. 9 illustrates a relationship of voltages applied on the first pixel electrode PAn and the second pixel electrode PBn of the pixel unit depicted in FIG. 4.
DETAILED DESCRIPTION OF THE INVENTION
With reference to FIG. 4 and FIG. 5, FIG. 4 is a circuit diagram of a liquid crystal display 100 according to a first embodiment of the present invention, and FIG. 5 is a timing diagram showing a scan signal generated by the gate driver depicted in FIG. 4. A liquid crystal display 100 comprises a source driver 102, a gate driver 104 and a plurality of the pixel units 110. The plurality of pixel units 110 are arranged in an array. Each pixel unit 110 comprises a first pixel electrode PAn, a second pixel electrode PBn, a first transistor Tn, a second transistor Sn and a level adjustment unit. The gate driver 104 can generate a scan signal in characteristic of at least three voltage levels of which a second voltage level V2 is greater than a first voltage level V1 and a third voltage level V3 is less than the first voltage level V1. The level adjustment unit can be a capacitor Cn.
With reference from FIG. 4 to FIG. 6, FIG. 6 illustrates a relationship of voltages applied on the first pixel electrode PAn and the second pixel electrode PBn of the pixel unit depicted in FIG. 4. First, in the time period T5-T6, the transistors Tn, Sn, Tn+1 are all turned on due to the scan signals at the second voltage level V2 generated by the gate driver 104 through the scan lines Gn, Gn+1. Meanwhile, the scan signal on the scan line Gn−1 is at the third voltage level V3, so the transistor Sn−1 is turned off. Therefore, data signal generated from the source driver 102 is delivered to the first pixel electrodes PAn and PAn+1 via data line DATA, and charges the second pixel electrode PBn since the transistor Sn is turned on. As such the first pixel electrode PAn and the second pixel electrode PBn are simultaneously fed by the same data signal. At the same time, the storage capacitor Cn is charged due to a voltage difference across its two ends.
In the time period T6-T7, the scan signal on the scan line Gn remains at the second voltage level V2 to switch on the transistors Tn, Sn, whereas the scan signal on the scan line Gn+1 is switched to the first voltage level V1, thereby turning off the transistor Tn+1. As can been seen in FIG. 6, at the time point T6, a voltage drop of the second pixel electrode PBn is induced by a feed-through voltage effect. In a duration of the time period T6-T7, because the scan signal on the scan line Gn−1 is varied from the third voltage level V3 to the first voltage level V1 (at the moment indicated by the arrow E shown in FIG. 5 and FIG. 6), and charge stored in the capacitor Cn is constant, the voltage level of the second pixel electrode PBn raises as a rise of voltage level of the scan signal on the scan line Gn−1. Accordingly, a proper capacitance of capacitor Cn can adjust the voltage level of the first pixel electrode PAn as the same as that of the second pixel electrode PBn.
Next, in the time period T7-T8, the scan signal on the scan line Gn−1 holds at the first voltage level V1 to turn on the transistor Sn−1, while the scan signal on the scan line Gn converts to the third voltage level V3 to turn off the transistors Tn, Sn. Even though the feed-through voltage effect still affects the transistors Tn, Sn at the time T7, the voltage of the first pixel electrode PAn is as the same as that of the second pixel electrode PBn due to voltage compensation happened prior to the time point T7 (the moment indicated by the arrow E). Accordingly, after the time point T7, the voltages on the first pixel electrode PAn and on the second pixel electrode PBn are identical, i.e. both pixel electrodes PAn and PBn of the pixel unit 110 can display the same gray level. As a result, the liquid crystal display 100 has improvement in display quality.
Please refer to FIG. 7 and FIG. 8. FIG. 7 is a circuit diagram of a liquid crystal display 200 according to a second embodiment of the present invention. FIG. 8 is a timing diagram showing scan signals generated by the gate driver depicted in FIG. 7. A liquid crystal display 200 comprises a source driver 202, a gate driver 204 and a plurality of the pixel units 210. The plurality of pixel units 210 are arranged in an array. Each pixel unit 210 comprises a first pixel electrode PAn, a second pixel electrode PBn, a first transistor Tn, a second transistor Sn, a first level adjustment unit and a second level adjustment unit. The gate driver 204 can generate a scan signal in characteristic of at least three voltage levels which a second voltage level V2 is greater than a first voltage level V1, and a third voltage level V3 is less than the first voltage level V1. The first and second level adjustment units can be a capacitor Cn, and a capacitor Dn respectively.
With reference from FIG. 7 to FIG. 9, FIG. 9 illustrates a relationship of voltages applied on the first pixel electrode PAn and the second pixel electrode PBn of the pixel unit depicted in FIG. 4. First, in the time period T5-T6, the transistors Tn, Sn, Tn+1 are all turned on due to the scan signals at the second voltage level V2 generated by the gate driver 204 through the scan lines Gn, Gn+1. Meanwhile, the scan signal on the scan line Gn−1 is at the third voltage level V3, so the transistor Sn−1 is turned off. Therefore, data signal generated from the source driver 102 is delivered to the first pixel electrodes PAn and PAn+1 via data line DATA, and charges the second pixel electrode PBn since the transistor Sn is turned on. As such the first pixel electrode PAn and the second pixel electrode PBn are simultaneously fed by the same data signal. At the same time, the storage capacitors Cn, Dn are charged due to a voltage difference across their two ends.
In the time period T6-T7, the scan signal on the scan line Gn remains at the second voltage level V2 to switch on the transistors Tn, Sn, whereas the scan signal on the scan line Gn+1 is switched to the first voltage level V1, thereby turning off the transistor Tn+1. As can been seen in FIG. 9, at the time point T6, a voltage drop of the second pixel electrode PBn is induced by a feed-through voltage effect. At this moment, the first pixel electrode PAn still receives the data signal without the feed-through voltage effect.
Next, in a time period T7-T8, the scan signal Gn−1 is at the third voltage level V3 to turn off the transistor Sn−1. Noted that, at the time T7, even though the scan signal on the scan line Gn is varied from the second voltage level V2 to the third voltage level V3, causing the transistors Tn, Sn turning off, an identical drop of voltages applied on the first pixel electrode PAn and the second pixel electrode PBn happens due to parasitic capacitance of the transistor. However, the voltage applied on the second pixel PBn drops at the time T6, so the voltages applied on the first pixel PAn and the second pixel PBn are different at the time T7.
At the time T8, the scan signal on the scan line Gn−1 is varied from the third voltage level V3 to the first voltage level V1, while the scan signal on the scan line Gn remains at the third voltage level V3, causing the transistors Sn−1, Tn, Sn turning off. In other words, at the time T8, because the scan signal on the scan line Gn−1 is varied from the third voltage level V3 to the first voltage level V1, and charge stored in the respective capacitors Cn, Dn is constant, the voltages of the first pixel electrode PAn and the second pixel electrode PBn raise as a rise of voltage level of the scan signal on the scan line Gn−1. Despite the voltages applied on the first pixel electrode and the second electrode are not identical in the time period T7-T8, proper selected capacitances of capacitors Cn, Dn can adjust the voltage of the first pixel electrode PAn as the same as that of the second pixel electrode PBn at the time T8. Consequently, after the time point T8, the voltages on the first pixel electrode PAn and on the second pixel electrode PBn are identical, i.e. both pixel electrodes PAn and PBn of the pixel unit 210 can display the same gray level. As a result, the liquid crystal display 200 has improvement in display quality
Compared with prior art, the liquid crystal display of the present invention utilizes a scan signal with three voltage levels and provides capacitors coupling to pixel electrodes of a pixel unit, to compensate the voltage differences of the pixel electrodes of the pixel unit resulting from the feed-through voltage. In this way, all pixel units of the liquid crystal display can improve in display quality.
While the preferred embodiments of the present invention have been illustrated and described in detail, various modifications and alterations can be made by persons skilled in this art. The embodiment of the present invention is therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications and alterations which maintain the spirit and realm of the present invention are within the scope as defined in the appended claims.