Patent Grant
7728805
The priority application number JP2004-346154 upon which this patent application is based is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a display, and more particularly, it relates to a display having a pixel portion.
2. Description of the Background Art
A liquid crystal display comprising a pixel portion including a liquid crystal layer is generally known as a display. In the conventional liquid crystal display, the liquid crystal layer of the pixel portion is held between a pixel electrode and a common electrode. The conventional liquid crystal display changes the arrangement of liquid crystal molecules by controlling a voltage (video signal) applied to the pixel electrode of the pixel portion, thereby displaying an image responsive to the video signal on a display portion.
When the aforementioned liquid crystal display applies a dc voltage to the liquid crystals (pixel electrode) of the pixel portion over a long period, an afterimage phenomenon referred to as seizure takes place. Therefore, the liquid crystal display must be driven by a method of inverting the voltage supply source (pixel voltage supply source) of the pixel electrode with respect to that of the common electrode in a prescribed cycle. For example, the liquid crystal display is driven by a DC driving method applying a dc voltage to the common electrode. Line inversion driving inverting the pixel voltage supply source with respect to the common electrode receiving the applied dc voltage every horizontal period is known as such a DC driving method, as disclosed in “Introduction to Liquid Crystal Display Engineering” by Yasoji Suzuki, The Daily Industrial News, Nov. 20, 1998, pp. 101-103. The liquid crystal display completes the operation of writing the video signal in all pixel portions arranged along a gate line every horizontal period.
When the liquid crystal display is driven by the conventional line inversion driving method shown in
In this regard, a liquid crystal display employing a dot inversion driving method of inverting a pixel voltage supply source (video signal) VIDEO with respect to the voltage supply source COM of a common electrode every adjacent pixel portions A and B, B and C, C and D, D and E or E and F is proposed in general.
A liquid crystal display capable of negatively/positively reversing images is known in general. This liquid crystal display negatively/positively reverses an image having a white background and black characters to that having a black background and white characters, for example. The liquid crystal display capable of negatively/positively reversing images performs negative/positive reversing by inverting a video signal in a driver IC driving/controlling the liquid crystal display. More specifically, the liquid crystal display inverts the respective bits of a 6-bit video signal, for example, by a video signal inversion circuit including six inverter circuits provided in the driver IC. In general, the liquid crystal display capable of negatively/positively reversing images also displays the images by the aforementioned conventional dot inversion driving method.
However, the conventional dot inversion driving method shown in
In order to negatively/positively reverse images in the aforementioned liquid crystal display employing the conventional dot inversion driving method, further, the driver IC must disadvantageously be provided therein with a video signal inversion circuit including inverter circuits of the same number as the bit number of the video signal. In order to negatively/positively reverse a 6-bit video signal, for example, the driver IC must include a video signal inversion circuit having six inverter circuits in order to invert the video signal, and hence the structure of the video signal inversion circuit is complicated and the driver IC remarkably consumes power when reversing the images.
The present invention has been proposed in order to solve the aforementioned problems, and an object of the present invention is to provide a display capable of rendering flickering hard to visually recognize, reducing power consumption and simplifying the structure of a circuit for negatively/positively reversing images.
In order to attain the aforementioned object, a display according to an aspect of the present invention comprises a plurality of drain lines and a plurality of gate lines arranged to intersect with each other, a first pixel portion and a second pixel portion each including a subsidiary capacitor having a first electrode connected to a pixel electrode and a second electrode, a first subsidiary capacitance line and a second subsidiary capacitance line connected to the second electrodes of the subsidiary capacitors of the first pixel portion and the second pixel portion respectively and a signal supply circuit including a plurality of signal supply circuit portions supplying either a first signal having a first voltage supply source or a second signal having a second voltage supply source for negatively/positively reversing an image to the first subsidiary capacitance line of the first pixel portion while supplying either a third signal having a third voltage supply source or a fourth signal having a fourth voltage supply source for negatively/positively reversing the image to the second subsidiary capacitance line of the second pixel portion. The display according to the present invention negatively/positively reverses an image having a white background and black characters to that having a black background and white characters, for example.
As hereinabove described, the display according to this aspect, provided with the first and second subsidiary capacitance lines connected to the second electrodes of the subsidiary capacitors of the first and second pixel portions respectively as well as the signal supply circuit including the plurality of signal supply circuit portions supplying the first and third signals having the first and third voltage supply sources to the first and second subsidiary capacitance lines of the first and second pixel portions respectively, can raise the voltage supply source of the second electrode of the subsidiary capacitor of the first pixel portion to a high level by supplying a high-level first signal to the second electrode of the subsidiary capacitor of the first pixel portion through the first subsidiary capacitance line assuming that the first and third voltage supply sources are at high and low levels respectively and the display supplies the first and third signals to the first and second subsidiary capacitance lines of the first and second pixel portions respectively. Further, the display can lower the voltage supply source of the second electrode of the subsidiary capacitor of the second pixel portion to a low level by supplying the low-level third signal to the second electrode of the subsidiary capacitor of the second pixel portion through the second subsidiary capacitance line. Thus, the display can set the pixel voltage supply source of the first pixel portion higher than that immediately after an operation of writing a high-level video signal in the first pixel portion by supplying the high-level first signal to the second electrode of the subsidiary capacitor of the first pixel portion after writing the video signal. Further, the display can set the pixel voltage supply source of the second pixel portion lower than that immediately after an operation of writing a low-level video signal in the second pixel portion by supplying the low-level third signal to the second electrode of the subsidiary capacitor of the second pixel portion after writing the video signal. Thus, the voltage of the video signal may not be increased, whereby the display can easily suppress increase of power consumption resulting from an increased voltage of the video signal. Consequently, power consumption can be reduced. Further, the display provided with the signal supply circuit including the plurality of signal supply circuit portions supplying the second and fourth signals having the second and fourth voltage supply sources for negatively/positively reversing the image to the first and second subsidiary capacitance lines of the first and second pixel portions respectively can supply the second and fourth signals to the first and second subsidiary capacitance lines respectively when negatively/positively reversing the image. Thus, the display can invert a high-level video signal of the first pixel portion by supplying a low-level second signal to the second electrode of the subsidiary capacitor of the first pixel portion after writing the high-level video signal in the first pixel portion, for example. Further, the display can invert a low-level video signal of the second pixel portion by supplying a high-level fourth signal to the second electrode of the subsidiary capacitor of the second pixel portion after writing the low-level video signal in the second pixel portion. Thus, the display capable of negatively/positively reversing the image without inverting the video signal may not invert the respective bits of a 6-bit video signal also when negatively/positively reversing the 6-bit video signal. Thus, a circuit for reversing the image can be more simplified and power consumption can be more reduced as compared with a case of inverting the respective bits of the 6-bit video signal. Further, the display can easily perform dot inversion driving of inverting the pixel voltage supply source (video signal) with respect to the voltage supply source of a common electrode every adjacent pixel portions by adjacently arranging the first and second pixel portions. In addition, the display can easily perform block inversion driving of inverting the pixel voltage supply source (video signal) with respect to the voltage supply source of the common electrode every plurality of pixel portions by constituting one block of only a plurality of first pixel portions while constituting another block of only a plurality of second pixel portions and adjacently arranging these blocks. The display, performing dot inversion driving or block inversion driving in the aforementioned manner so that no flickering linearly takes place dissimilarly to a case of performing line inversion driving of inverting the pixel voltage supply source (video signal) with respect to the voltage supply source of the common electrode every adjacent gate lines, can easily render flickering hard to visually recognize.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
An embodiment of the present invention is now described with reference to the drawings.
The structure of a liquid crystal display according to the embodiment of the present invention is described with reference to
Referring to
Each of the pixel portions 3a and 3b is constituted of a liquid crystal layer 31, an n-channel transistor 32 and a subsidiary capacitor 33. The liquid crystal layer 31 of each of the pixel portions 3a and 3b is arranged between a pixel electrode 34 and a common electrode (common electrode) 35.
The drains of the n-channel transistors 32 of the pixel portions 3a and 3b are connected to the drain lines D1 and D2 supplied with video signals respectively. The sources of the n-channel transistors 32 of the pixel portions 3a and 3b are connected to the pixel electrodes 34 respectively.
First electrodes 36 of the subsidiary capacitors 33 of the pixel portions 3a and 3b are connected to the pixel electrodes 34 respectively. Second electrodes 37a and 37b of the pixel portions 3a and 3b are connected to subsidiary capacitance lines SC1-1 and SC2-1 respectively. The electrodes 36 are examples of the “first electrode” in the present invention, and the electrodes 37a and 37b are examples of the “second electrode” in the present invention. The subsidiary capacitance lines SC1-1 and SC2-1 are examples of the “first subsidiary capacitance line” and the “second subsidiary capacitance line” respectively.
The substrate 1 is also provided thereon with n-channel transistors (H switches) 4a and 4b and an H driver 5 for driving (scanning) the drain lines D1 and D2 and subsequent drain lines (not shown). The n-channel transistors 4a and 4b corresponding to the pixel portions 3a and 3b (drain lines D1 and D2) are connected to video signal lines VIDEO1 and VIDEO2 respectively. A V driver 6 is also provided on the substrate 1 for driving (scanning) the first-stage gate line G1 and subsequent gate lines (not shown). The V driver 6 is an example of the “gate line driving circuit” or the “first shift register” in the present invention.
According to this embodiment, a signal supply circuit 7 and a shift register 8 are provided on the substrate 1. Both of the subsidiary capacitance lines SC1-1 and SC2-1 corresponding to the pixel portions 3a and 3b respectively are connected to the signal supply circuit 7 (signal supply circuit portion 7a). The signal supply circuit 7 has a function of alternately supplying high- and low-level signals VSCH and VSCL to the subsidiary capacitance lines SC1-1 and SC2-1 every frame period. The liquid crystal display completes the operation of writing video signals in all pixel portions 3a and 3b constituting the display portion 2 every frame period. The shift register 8 has a function of driving the signal supply circuit 7 for sequentially supplying the signals from the signal supply circuit 7 to the pair of subsidiary capacitance lines SC1-1 and SC2-1 provided along the first-stage gate line G1 up to a pair of subsidiary capacitance lines (not shown) provided along a final-stage gate line (not shown). The shift register 8 is an example of the “second shift register” in the present invention.
According to this embodiment, a driver IC 9 including a phase control circuit 9a is set outside the substrate 1. The driver IC 9 is an example of the “driving circuit” in the present invention. This driver IC 9 supplies a high voltage supply source HVDD, a low voltage supply source HVSS, a start signal STH and a clock signal CKH to the H driver 5. The driver IC 9 also supplies a higher voltage supply source VVDD, a lower voltage supply source VVSS, a start signal STV, a clock signal CKV and an enable signal ENB to the V driver 6. The driver IC 9 further supplies a higher voltage supply source VSCH and a lower voltage supply source VSCL to the signal supply circuit 7. The phase control circuit 9a supplies either a clock signal CKVSC or a clock signal XCKVSC for negatively/positively reversing an image to the signal supply circuit 7. The phase control circuit 9a generates the clock signal XCKVSC by inverting the phase of the clock signal CKVSC. The driver IC 9 supplies the shift register 8 with the same signals as those supplied to the V driver 6. The clock signal CKVSC is an example of the “first control signal” in the present invention, and the clock signal XCKVSC is an example of the “second control signal” in the present invention.
The internal structures of the V driver 6, the signal supply circuit 7 and the shift register 8 are described with reference to
The input terminals of the AND circuit portion 62a receive output signals from the shift register circuit portions 61a and 61b and the enable signal ENB. The input terminals of the AND circuit portion 62b receive output signals from the shift register circuits 61b and 61c and the enable signal ENB. Similarly, input terminals of each of the subsequent AND circuit portions receive output signals from shift register circuit portions precedent and subsequent thereto and the enable signal ENB. Each of the AND circuit portions 62a to 62e outputs a high-level signal only when the three input signals go high, and outputs a low-level signal when any one of the three input signals is at a low level. The output terminals of the AND circuit portions 62a to 62e are connected to gate lines G1 to G5 respectively. Level shifter circuits (not shown) are connected between the AND circuit portions 62a to 62e and the gate lines G1 to G5.
The signal supply circuit 7 includes signal supply circuit portions 7a to 7d, which are provided in correspondence to the gate lines G1 to G4 respectively.
The signal supply circuit portion 7a is constituted of inverters 71a to 71c, clocked inverters 72a and 72b and switches 73a to 73d, as shown in
An input terminal A of the inverter 71a receives an output signal from the shift register 8 (see
Input terminals A of the switches 73a and 73d and those of the switches 73b and 73c receive the positive and lower voltage supply sources VSCH and VSCL respectively. Output terminals X of the switches 73a and 73b and those of the switches 73c and 73d are connected to the subsidiary capacitance lines SC1-1 and SC2-1 respectively. The gates of the n-channel transistors of the switches 73a and 73c are connected to the node ND1, while those of the p-channel transistors of the switches 73a and 73c are connected to the node ND2. The gates of the n-channel transistors of the switches 73b and 73d are connected to the node ND2, while those of the p-channel transistors of the switches 73b and 73d are connected to the node ND1.
The circuit structures of the signal supply circuit portions 7b to 7d shown in
As shown in
The input terminals of the AND circuit portion 82a receive output signals from the shift register circuit portions 81a and 81b and the enable signal ENB. The input terminals of the AND circuit portion 82b receive output signals from the shift register circuits 81b and 81c and the enable signal ENB. Similarly, the input terminals of each of the subsequent AND circuit portions receive output signals from shift register circuit portions precedent and subsequent thereto and the enable signal ENB. The output terminals of the AND circuit portions 82a to 82e are connected to the signal supply circuit portions 7a to 7d respectively. The shift register 8 is provided with no AND circuit portion receiving output signals from the shift register circuit portions 81a and 81b, dissimilarly to the V driver 6, for the following reason: The shift register 8 receives the start signal STV, the clock signal CKV and the enable signal ENB identically to the V driver 6. In order to fluctuate the voltage supply source of the first-stage subsidiary capacitor after writing a video signal in the first-stage pixel portion, therefore, it is necessary to fluctuate this voltage supply source in response to a high-level signal of the second-stage AND circuit portion. Therefore, the shift register 8 requires no first-stage AND circuit portion receiving the output signals from the shift register circuit portions 81a and 81b.
The circuit structure of the phase control circuit 9a of the driver IC 9 (see
In order to display the image in the normal (nonreversed) state, the liquid crystal display inputs a high-level start signal STV in the V driver 6 and the shift register 8 shown in
Then, the clock signal CKV1 goes high again so that the AND circuit portions 62b and 62c receive a high-level signal from the shift register circuit portion 61c (see
Then, the liquid crystal display sequentially inputs high-level signals from the shift register circuit portions 61d to 61f (see
Also in the shift register 8 (AND circuit portions 82a to 82d: see
The liquid crystal display sequentially inputs the high-level signals sequentially output from the shift register 8 in the signal supply circuit portions 7a to 7d (see
In the phase control circuit 9a of the driver IC 9, the inverter 91a receives a high-level clock signal CKVSC in its input terminal and outputs a low-level clock signal CKVSC from its output terminal, as shown in
In the signal supply circuit portion 7a, the clocked inverter 72a enters an ON-state when receiving a high-level input signal from the shift register 8 (see
When the input signals from the shift register 8 go low, the clocked inverters 72a and 72b enter OFF- and ON-states respectively, whereby the inverter 71b continuously receives the low-level signal in its input terminal A. Consequently, the liquid crystal display holds the nodes ND1 and ND2 at the high and low levels respectively, thereby continuously supplying the high- and low-level signals VSCH and VSCL to the subsidiary capacitance lines SCd-1 and SC2-1 respectively. Also in the signal supply circuit portions 7b to 7d shown in
Thus, the liquid crystal display sequentially supplies the high- and low-level signals VSCH and VSCL from the signal supply circuit portions 7a to 7d to the subsidiary capacitance lines SC1-1 to SC1-4 and SC2-1 to SC2-4 at timing similar to that for supplying high-level signals to the gate lines G2 to G5. The subsidiary capacitance lines SC1-2, SC1-3 and SC1-4 are examples of the “first subsidiary capacitance line” in the present invention, and the subsidiary capacitance lines SC2-2, SC2-3 and SC2-4 are examples of the “second subsidiary capacitance line” in the present invention.
In the display portion 2 shown in
At this time, the liquid crystal display turns on the n-channel transistor 32 in the pixel portion 3a, thereby writing the high-level video signal in the pixel portion 3a. In other words, a pixel voltage supply source Vp1 goes up to the level of the video signal line VIDEO1, as shown in
According to this embodiment, the liquid crystal display supplies the high-level signal VSCH to the subsidiary capacitance line SC1-1 after the signal supplied to the gate line G1 goes low, thereby supplying the high-level signal VSCH to the second electrode 37a of the subsidiary capacitor 33 (see
The liquid crystal display turns on the n-channel transistor 32 in the pixel portion 3b (see
Also in the pixel portions arranged along the second- to fifth-stage gate lines G2 to G5 (see
Then, the liquid crystal display switches the clock signal CKVSC supplied from the phase control circuit 9a of the driver IC 9 to the signal supply circuit 7 in the nonreversed (normal) case to a low level. In this case, the switches 83a and 83c enter OFF-states and the switches 73b and 73d enter ON-states in the signal supply circuit portion 7a receiving the low-level clock signal CKVSC in its input terminal A as shown in
Thus, the liquid crystal display performs the operations shown in
According to this embodiment, as hereinabove described, the liquid crystal display supplies the high-level signal VSCH to the subsidiary capacitance line SC1-1 when the voltage supply source of the video signal line VIDEO0 supplied to the pixel voltage supply source Vp1 of the pixel portion 3a (see
In order to negatively/positively reverse the image according to this embodiment, the liquid crystal display supplies the low-level signal VSCL to the subsidiary capacitance line SC1-1 when the voltage supply source of the video signal line VIDEO0 supplied to the pixel voltage supply source Vp1 of the pixel portion 3a (see
Operations of the liquid crystal display for negatively/positively reversing the image are now described in detail. First, operations of the V driver 6 and the shift register 8 are similar to those for displaying the image in the normal (nonreversed) state. As shown in
When the signal supply circuit portion 7a receives a high-level input signal from the shift register 8 (see
When the input signal from the shift register 8 goes low, the clocked inverter 72a enters an OFF-state, while the clocked inverter 72b enters an ON-state and hence the inverter 71b continuously receives the high-level signal in its input terminal A. Consequently, the liquid crystal display continuously holds the nodes ND1 and ND2 at the low and high levels respectively, thereby continuously supplying the low- and high-level signals VSCL and VSCH to the subsidiary capacitance lines SC1-1 and SC2-1 respectively. Also in the signal supply circuit portions 7b to 7d shown in
Thus, the liquid crystal display sequentially supplies the low- and high-level signals VSCL and VSCH from the signal supply circuit portions 7a to 7d to the subsidiary capacitance lines SC1-1 to SC1-4 and SC2-1 to SC2-4 respectively at timing similar to that for supplying the high-level signals to the gate lines G2 to G5.
In the display portion 2 shown in
At this time, the liquid crystal display turns on the n-channel transistor 32 in the pixel portion 3a, thereby writing the high-level video signal in the pixel portion 3a. In other words, the pixel voltage supply source Vp1 goes up to the level of the video signal line VIDEO, as shown in
According to this embodiment, the liquid crystal display supplies the low-level signal VSCL to the subsidiary capacitance line SC1-1 after the signal supplied to the gate line G1 goes low, thereby supplying the low-level signal VSCL to the second electrode 37a (see
The liquid crystal display turns on the n-channel transistor 32 in the pixel portion 3b (see
Also in the pixel portions arranged along the second- to fifth-stage gate lines G2 to G5 (see
Then, the liquid crystal display switches the clock signal XCKVSC supplied to the signal supply circuit 7 (see
Thus, the liquid crystal display performs the operations shown in
According to this embodiment, as hereinabove described, the liquid crystal display provided with the signal supply circuit 7 supplying the high- and low-level signals VSCH and VSCL to the subsidiary capacitance lines SC1-1 to SC1-4 and SC2-1 to SC2-4 of the pixel portions 3a and 3b supplies the high-level signal VSCH to the electrode 37a of the subsidiary capacitor 33 of the pixel portion 3a through the subsidiary capacitance lines SC1-1 to SC1-4 thereby raising the voltage supply source of the electrode 37a of the subsidiary capacitor 33 of the pixel portion 3a to a high level assuming that the same supplies the high- and low-level signals VSCH and VSCL to the subsidiary capacitance lines SC1-1 to SC1-4 and SC2-1 to SC2-4 of the pixel portions 3a and 3b respectively, for example. Further, the liquid crystal display supplies the low-level signal VSCL to the electrode 37b of the subsidiary capacitor 33 of the pixel portion 3b through the subsidiary capacitance lines SC2-1 to SC2-4, thereby lowering the voltage supply source of the electrode 37b of the subsidiary capacitor 33 of the pixel portion 3b. Thus, the liquid crystal display can render the pixel voltage supply source Vp1 of the pixel portion 3a higher than that immediately after an operation of writing the high-level video signal in the pixel portion 3a by supplying the high-level signal VSCH to the electrode 37a of the subsidiary capacitor 33 of the pixel portion 3a after writing the high-level video signal. Further, the liquid crystal display can render the pixel voltage supply source Vp2 of the pixel portion 3b lower than that immediately after an operation of writing the low-level video signal in the pixel portion 3b by supplying the low-level signal VSCL to the electrode 37b of the subsidiary capacitor 33 of the pixel portion 3b after writing the low-level video signal. Thus, the voltages of the video signals may not be increased, whereby the liquid crystal display can easily suppress increase of power consumption resulting from increased voltages of the video signals. Consequently, the liquid crystal display can reduce power consumption.
According to this embodiment, further, the liquid crystal display can render the pixel voltage supply source Vp1 of the pixel portion 3a lower than that immediately after the operation of writing the high-level video signal in the pixel portion 3a by supplying the low-level signal VSCL to the electrode 37a of the subsidiary capacitor 33 of the pixel portion 3a after writing the high-level video signal. The liquid crystal display can further render the pixel voltage supply source Vp2 of the pixel portion 3b higher than that immediately after the operation of writing the low-level video signal in the pixel portion 3b by supplying the high-level signal VSCH to the electrode 37b of the subsidiary capacitor 33 of the pixel portion 3b after writing the low-level video signal. Thus, the liquid crystal display, which can negatively/positively reverse the image, may not invert the respective bits when negatively/positively reversing a 6-bit video signal, for example. Therefore, the liquid crystal display can simplify the circuit for reversing the image and reduce power consumption as compared with a case of inverting the respective bits of the 6-bit video signal. Further, the liquid crystal display can easily perform dot inversion driving by adjacently arranging the pixel portions 3a and 3b. In this case, no flickering linearly takes place dissimilarly to a case of performing line inversion driving, whereby the liquid crystal display can easily render flickering hard to visually recognize.
According to this embodiment, the phase control circuit 9a is constituted of the inverter 91a for inverting the clock signal CKVSC, the p-channel transistor 93 connected to the input terminal of the inverter 91a and turned on when the clock signal CKVSC is at a low level and the n-channel transistor 92 connected to the output terminal of the inverter 91a and turned on when the clock signal CKVSC is at a high level, whereby the structure of the phase control circuit 9a serving as a circuit for negatively/positively reversing an image can be simplified as compared with the conventional case of employing the video signal inversion circuit having six inverters for inverting the respective bits of a 6-bit video signal, for example.
According to this embodiment, the signal supply circuit portions 7a to 7d are provided in correspondence to the gate lines G1 to G4 respectively, whereby the liquid crystal display can sequentially supply the high- and low-level signals VSCH and VSCL to the subsidiary capacitance lines SC1-1 to SC1-4 and SC2-1 to SC2-4 corresponding to the gate lines G1 to G4 respectively through the signal supply circuits 7a to 7d when sequentially writing video signals in the pixel portions 3a and 3b of the gate lines G1 to G4. Further, the liquid crystal display can sequentially supply the low- and high-level signals VSCL and VSCH to the subsidiary capacitance lines SC1-1 to SC1-4 and SC2-1 to SC2-4 corresponding to the gate lines G1 to G4 respectively through the signal supply circuit portions 7a to 7d when sequentially writing video signals in the pixel portions 3a and 3b of the gate lines G1 to G4 for reversing an image.
According to this embodiment, the liquid crystal display provided with the V driver 6 for sequentially driving the plurality of gate lines G1 to G5 and the shift register 8 for sequentially driving the plurality of signal supply circuit portions 7a to 7d can easily sequentially drive the signal supply circuit portions 7a to 7d, corresponding to the gate lines G1 to G5 sequentially driven by the V driver 6, through the shift register 8.
According to this embodiment, the liquid crystal display can easily render the pixel voltage supply sources of all pixel portions 3a and 3b arranged along the gate line G1 higher or lower than those immediately after the operations of writing video signals in all pixel portions 3a and 3b arranged along the gate line G1 through the signal supply circuit portion 7a by supplying either the high-level signal VSCH or the low-level signal VSCL to the subsidiary capacitance line S1-1 and supplying either the low-level signal VSCL or the high-level signal VSCH to the subsidiary capacitance line SC2-1 after writing the video signals.
According to this embodiment, the liquid crystal display can easily perform dot inversion driving by alternately switching the high- and low-level signals VSCH and VSCL supplied to the subsidiary capacitance lines SC1-1 to SC1-4 and SC2-1 to SC2-4 every frame period for writing video signals in all pixel portions thereby inverting the pixel voltage supply sources Vp1 and Vp2 of the video signals written in the pixel electrodes 34 of the pixel portions 3a and 3b with respect to the voltage supply source COM of the common electrode 35 every frame period through the signal supply circuit portions 7a to 7d. In this case, the liquid crystal display can easily suppress seizure (afterimage phenomenon).
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
For example, while each signal supply circuit portion has the circuit structure shown in
While the liquid crystal display performs dot inversion driving by adjacently arranging the pixel portions 3a and 3b in the aforementioned embodiment, the present invention is not restricted to this but the liquid crystal display may alternatively perform block inversion driving by constituting first and second blocks of only a plurality of pixel portions 3a and only a plurality of pixel portions 3b respectively and adjacently arranging the first and second blocks.
While the liquid crystal display sequentially turns on the n-channel transistors for driving the drain lines in the aforementioned embodiment, the present invention is not restricted to this but the liquid crystal display may alternatively simultaneously turn on all n-channel transistors for driving the drain lines.
While the liquid crystal display sequentially drives the plurality of signal supply circuit portions through the shift register including the shift register circuit portions similar in circuit structure to the shift register circuit portions of the V driver in the aforementioned embodiment, the present invention is not restricted to this but the liquid crystal display may alternatively employ a shift register including shift register circuit portions different in circuit structure to the shift register circuit portions of the V driver so far as the same can sequentially drive the plurality of signal supply circuit portions.
While the liquid crystal display supplies the high- and low-level signals to at least a pair of subsidiary capacitance lines corresponding to a prescribed-stage gate line at timing similar to that for writing the video signals in the pixel portions along the subsequent-stage gate line in the aforementioned embodiment, the present invention is not restricted to this but the liquid crystal display may alternatively supply prescribed signals to at least a pair of subsidiary capacitance lines corresponding to a prescribed-stage gate line at timing different from that for writing video signals in pixel portions along a subsequent-stage gate line.
While the phase control circuit has the circuit structure shown in
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