Patent Application
20090073104
The present disclosure relates to a liquid crystal display (LCD) capable of split-screen displaying, and also relates to a computer system using such LCD.
LCDs are widely used in various electronic information devices, such as notebooks, personal digital assistants, video cameras, and the like. LCDs may employ a video graphic array (VGA) interface or a digital visual interface (DVI) to receive video signals provided by a computing system, and to further display images according to the video signals.
In special circumstances, such as a meeting or an exhibition, it may be needed to simultaneously display images according to video signals provided by two or more computing systems. Because the conventional LCD can only display images based on video signals outputted from a computer host one time, in this situation, a user has to provide an auxiliary LCD to meet the dual-displaying requirement. This is inconvenient for the user.
What is needed is to provide an LCD and a computer system that can overcome the limitations described.
In one exemplary embodiment, a liquid crystal display includes a liquid crystal panel having at least two pixel regions, a mode selector configured to provide a mode selection signal, and a timing controller configured to receive at least two video signal sets and in response to the mode selection signal, control the liquid crystal panel to display a picture corresponding to one of the at least two video signal sets using full-screen displaying or to simultaneously display at least two pictures, each of the at least two pictures corresponding to one of the at least two video signal sets using split-screen displaying. Each of the at least two pixel regions corresponds to one of the at least two pictures while using the split-screen displaying.
Other novel features and advantages will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
Reference will now be made to the drawings to describe certain inventive embodiments of the present disclosure in detail.
The liquid crystal panel 210 includes 2m rows of parallel scanning lines X1-X2m (where m is a natural number), 2n columns of parallel data lines Y1-Y2n (where n is also a natural number) perpendicular to the scanning lines X1-X2m, and a plurality of pixel units 270 cooperatively defined by the crossing scanning lines X1-X2m and data lines Y1-Y2n. Thereby, the pixel units 270 are arranged in a matrix having 2m rows and 2n columns. The matrix is divided into a first pixel region 211 involving the first to pth (2≦p≦2n−1) columns of the pixel units 270, and a second pixel region 212 involving the (p+1)th to (2n)th columns of the pixel units 270. In the illustrated embodiment, for example, the number k is adopted to be equal to n, such that a size of the first pixel region 211 is substantially the same as that of the second pixel region 212. Thus each of the first and second pixel regions 211, 212 includes 2m×n pixel units 270, that is, a physical resolution of each of the first and second pixel regions 211, 212 is 2m×n. Moreover, the scanning lines X1-X2m are electrically coupled to the scanning circuit 220. The data lines Y1-Yn are electrically coupled to the first data circuit 230. The data lines Y(n+1)−Y2n are electrically coupled to the second data circuit 240.
Each pixel unit 270 includes a thin-film transistor (TFT) 271, a pixel electrode 272, and a common electrode 273. A gate electrode of the TFT 271 is electrically coupled to a corresponding one of the scanning lines X1-X2m, and a source electrode of the TFT 271 is electrically coupled to a corresponding one of the data lines Y1-Y2n. Further, a drain electrode of the TFT 271 is electrically coupled to the pixel electrode 272. The common electrode 273 is generally opposite to the pixel electrode 272, with a plurality of liquid crystal molecules (not shown) sandwiched therebetween, so as to cooperatively form a liquid crystal capacitor 274.
The first interface circuit 280 and the second interface circuit 290 are capable of scaling video signals applied thereto. In particular, the first interface circuit 280 is electrically coupled to a first video source (not shown) to receive a first video signal set having a first primary resolution, and the second interface circuit 290 is electrically coupled to a second video source (not shown) to receive a second video signal set having a second primary resolution. In the first interface circuit 280, the first video signal set is scaled and converted to a first k-bit low voltage differential signal (LVDS) set with a first resolution equal to the physics resolution of the first pixel region 211, that is, 2m×n. Similarly, in the second interface circuit 290, the second video signal set is scaled and converted to a second k-bit LVDS set with a second resolution equal to the physics resolution of the second pixel region 212, that is, 2m×n, too. In addition, each of the first and second video sources can be a selected one of a computer host, a disc player, a memory reader, and the like.
The timing controller 250 controls the driving timing of the scanning circuit 220, the first data circuit 230, and the second data circuit 240. The timing controller 250 includes a control terminal 257 for receiving a mode selection signal from the mode selector 260, a first output terminal 256 for outputting a first timing control signal to the scanning circuit 220, and a second output terminal 255 for outputting a second timing control signal to both the first and second data circuits 230, 240.
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In one embodiment, the output terminal 269 is electrically coupled to the control terminal 257 of the timing controller 250 via a connecter 265. However, the output terminal 269 can also be electrically coupled to the control terminal 257 directly.
Typical operation of the LCD 200 is as follows. When the user inputs an instruction indicating that a default working mode of the LCD 200 is selected, the output terminal 269 of the mode selector 260 is electrically coupled to the third contact terminal 268. Because the third contact terminal 268 is floating, a high-impedance signal is generated and outputted to the timing controller 250. The high-impedance signal serves as a first mode selection signal, and controls the data analyzer 252 to select the first k-bit LVDS set from the receiving unit 251. The data analyzer 252 then converts the first k-bit LVDS set into a first k-bit signal subset and a second k-bit signal subset.
When the user inputs an instruction indicating that a first alternative working mode is selected of the LCD 200, the output terminal 269 of the mode selector 260 is electrically coupled to the first contact terminal 266. Because the first contact terminal 266 is electrically coupled to the power supply 261, a high voltage signal is generated and outputted to the timing controller 250. The high voltage signal serves as a second mode selection signal, and controls the data analyzer 252 to select the second k-bit LVDS set from the receiving unit 251. The data analyzer 252 then converts the second k-bit LVDS set into a first k-bit signal subset and a second k-bit signal subset.
When the user inputs an instruction indicating that a second alternative working mode is selected of the LCD 200, the output terminal 269 of the mode selector 260 is electrically coupled to the second contact terminal 267. Because the second contact terminal 267 is grounded, a low voltage signal is generated and outputted to the timing controller 250. The low voltage signal serves as a third mode selection signal, and controls the data analyzer 252 to select the first k-bit LVDS set and the second k-bit LVDS set from the receiving unit 251 simultaneously. The data analyzer 252 then converts the first LVDS set into a first k-bit signal subset, and converts the second LVDS set into a second k-bit signal subset.
Whichever working mode is selected, in addition, the data analyzer 252 further synchronizes the first signal subset and the second signal subset, so as to form a synchronous signal. The first signal subset and the second signal subset are received by the output unit 253 in parallel, converted to a first RSDS set and a second RSDS set respectively, and outputted to the first data circuit 230 and the second data circuit 240, respectively. The counter 254 receives and counts the synchronous signal, so as to generate a first timing control signal and a second timing control signal, respectively. The first timing control signal is then outputted to the scanning circuit 220, and the second timing control signal is then outputted to both the first data circuit 230 and the second data circuit 240.
The scanning circuit 220 provides a plurality of scanning pulses to the scanning lines X1-X2m sequentially according to the first timing control signal. Thereby, the TFTs 271 of the pixel units 270 located in the corresponding row of the matrix are switched on, and the corresponding pixel units 270 are activated.
The first data circuit 230 converts the first RSDS set to a plurality of first driving voltage signals, and outputs the first driving voltage signals to the pixel electrodes 271 of the activated pixel units 270 in the first pixel region 211 via the data lines Y1-Yn. The second data circuit 230 converts the second RSDS set to a plurality of second driving voltage signals, and outputs the second driving voltage signals to the pixel electrodes 271 of the activated pixel units 270 in the second pixel region 212 via the data lines Yn+1−Y2n. Each of the driving voltage signals causes an electric field to be generated between the corresponding pixel electrode 272 and the common electrode 273. The electric field drives the liquid crystal molecules of the pixel unit 270 to control light transmission of the pixel unit 270, such that the pixel unit 270 displays a particular color (e.g., red, green, or blue) having a corresponding gray level. The aggregation of colors displayed by all the pixel units 270 in the first pixel region 211 simultaneously constitutes a first sub-image, and the aggregation of colors displayed by all the pixel units 270 in the second pixel region 212 simultaneously constitutes a second sub-image.
When the default working mode is selected, the first sub-image and the second sub-image cooperatively form a complete picture corresponding to the first video signal set provided by the first video source. When the first alternative working mode is selected, the first sub-image and the second sub-image cooperatively form a complete picture corresponding to the second video signal set provided by the second video source. When the second alternative working mode is selected, the first sub-image and the second sub-image are independent and respectively correspond to the first video signal set and the second video signal set. In this situation, the LCD 200 simultaneously displays two pictures using split-screen displaying, with one picture in the first region 211 and the other picture in the second region 212. Moreover, the two pictures are located along an extending direction of the scanning line X1-X2m.
In summary, the LCD 200 employs the mode selector 260 to provide a mode selection signal, and employs the timing controller 250 having the data analyzer 252 to analyze and convert the first LVDS set and/or the second LVDS set according to the mode selection signal. Thereby, the LCD 200 is capable of displaying video signals provided by two video sources (e.g. two computing systems) simultaneously using split-screen displaying, and the dual-displaying requirement is met without applying an auxiliary LCD that might otherwise be necessary. This improves the convenience of the LCD 200 for the user. Moreover, due to the cooperation of the mode selector 260 and the timing controller 250, the LCD 200 can further be switched to full-screening display the picture corresponding the video signal set provided by one of the video sources as desired according to the inputting instruction. That is, the LCD 200 can be controlled to switch between full-screen displaying and split-screen displaying based on the viewing requirement of the user. This enables the LCD 200 to be applied in different kinds of circumstance.
With this configuration, by providing a corresponding instruction to a mode selector 360, the LCD 300 can be controlled to display two pictures corresponding to video signals provided to two video signals sources simultaneously using split-screen displaying, with the two pictures being located along the data lines Y1-Y2m.
In alternatively embodiments, the liquid crystal panels 210, 310 can be divided into a plurality of pixel regions, and mode selectors 260, 360 can be defined to have a plurality of working modes, such that while being used in one of the working mode, the LCDs 200, 300 can simultaneously displays a plurality of video signals provided by a plurality of video signal sources by split-screen displaying. That is, the number of split-screen of the LCDs 200, 300 can be expanded as desired.
It is to be further understood that even though numerous characteristics and advantages of preferred and exemplary embodiments have been set out in the foregoing description, together with details of structures and functions associated with the embodiments, the disclosure is illustrative only; and that changes may be made in detail (including in matters of arrangement of parts) within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 200710076998.3 | Sep 2007 | CN | national |
