The present invention relates to technology for controlling display and, specifically, to technology that can be particularly effectively adapted to controlling the drive of liquid crystal, such as technology that can be effectively utilized in a display control circuit in a dot-matrix liquid crystal panel for displaying characters or in a liquid crystal panel having a function of displaying pictures, marks, icons, characters (figures), etc. independently of the dot-matrix character display.
A liquid crystal display device, in general, comprises a liquid crystal display panel, a liquid crystal display controller formed as an integrated circuit on a semiconductor substrate for driving the liquid crystal display panel, and a microprocessor (MPU) or a microcontroller including a microprocessing unit (CPU) for controlling the writing of display data or the display operation of the liquid crystal display controller.
A liquid crystal display controller including a character generator for forming a display pattern of dot-matrix type is constituted by a display data memory for storing character codes (hereinafter referred to as a random access memory for display data or a display data RAM), a character generator memory for storing character patterns such as character fonts (hereinafter referred to as a read-only memory for a character generator or a character generator ROM), an address counter for reading display data from the display data RAM in accordance with the drive position of the liquid crystal display panel, a liquid crystal drive circuit for driving the liquid crystal by generating drive signals for common electrodes and for segment electrodes of a liquid crystal display panel, and a timing generation circuit for generating clock signals that give display timings.
The microprocessor writes, onto the display data RAM, character codes corresponding to characters to be displayed on the liquid crystal display panel. An address counter successively reads out character codes from the display data RAM in accordance with the drive position of the liquid crystal display panel, and successively reads out character patterns by making access to the character generator ROM by using character codes that are read out as part of the addresses. The character patterns that are read out are successively sent, as liquid crystal turn-on/off data, to a segment shift register in the liquid crystal drive circuit. When the data of one line are accumulated, the whole segment driver circuits output the drive voltages of the turn-on/turn-off level simultaneously thereby to drive the liquid crystal display panel.
Each character is constituted by a plurality of lines in a vertical direction and, hence, the above-mentioned control operation is repeated by the number of lines of the character for every display row (8 lines when the character comprises 5 (horizontal)×8 (vertical) dots). The turn-on/turn-off control operation for the display is executed in a time-division manner for each of the lines. Therefore, a selection signal of one line generated from the timing control circuit is sent to a common shift register. As the shift register shifts for each line, a common driver successively outputs a drive voltage of the selection level of the line.
In a portable telephone set or a portable electronic device such as a pager mounted with the above-mentioned liquid crystal display device, there is no need to produce a display on the whole surface of the liquid crystal display panel during the wait time; i.e., only a minimum of display may be made, such as the display of a calendar, the display of time, a mark called a pictogram or icons. In the liquid crystal display device in a portable telephone set or the like, however, the amount of display is decreased during the wait time but the liquid crystal drive duty is not changed. That is, even the common electrodes of lines that are not displayed are scanned, too, involving a problem that the consumption of electric power cannot be reduced to a sufficient degree during the wait time.
In a liquid crystal display controller having 32 common drivers for, for example, 32 lines are successively and selectively driven, by successively selecting from a common driver corresponding to a signal COM1 to a common driver corresponding to a signal COM32. A method of successively driving such common signal lines of 32 lines is called 1/32 duty drive. In this case, if the character font has a size of 5×8 dots, character strings of 4 rows can be displayed on the liquid crystal panel in the vertical direction. When this liquid crystal display controller is driven for 4 rows in a time-division manner even though 4 rows need not be displayed on the whole surface, the voltage for driving the liquid crystal and the current consumed by the liquid crystal display controller become the same as those of when 4 rows are displayed on the whole surface.
Here, if 4 rows are not displayed on the whole surface during the stand-by state of the system, but if part of the rows is selectively driven, the duty for driving the liquid crystal is lowered, the voltage for driving the liquid crystal is lowered, and then, less electric power is consumed by the liquid crystal drive controller. However, a change in the voltage for driving the liquid crystal results in a change in the optimum drive bias ratio, making it impossible to obtain a favorable display contrast Under the unchanged drive condition. Besides, if only the duty for driving the liquid crystal is simply lowered, then, the-display position of the character font is fixed to the uppermost row, causing a problem of poor balance of view from the standpoint of display.
Japanese Utility Model Laid-Open No. 131786/1990 discloses a liquid crystal matrix display device having a 4-power boosting circuit and a 6-power boosting circuit, and for selecting either of the boosting circuits depending upon the duty for driving the liquid crystal. Japanese Patent Laid-Open No. 119385/1991 discloses a liquid crystal display circuit capable of being switchably driven by a plurality of power supplies such as an AC power supply, battery, etc., by which the device is driven in case of power failure, and minimum of information such as a time piece and the like are displayed at a decreased drive duty with a lowered bias.
It is an object of the present invention to provide a liquid crystal display controller mounted in an electronic device, wherein the duty for driving the liquid crystal is dynamically changed depending upon the operation state of the system in order to decrease a total amount of electric power consumed by the system, and, when a variable duty display is made, an optimum liquid crystal drive voltage and an optimum liquid crystal drive bias condition are easily set depending upon the duty for driving liquid crystal.
Another object of the present invention is to provide a liquid crystal display controller capable of dynamically varying the boosting power of the boosted voltage, the duty for driving the liquid crystal, the bias for driving the liquid crystal and the liquid crystal display position, and a system using the above liquid crystal display controller.
A further object of the present invention is to provide a liquid crystal display controller capable of producing a display that is most easily viewed depending upon the operation state of the system and a system using the above liquid crystal display controller.
Representative aspects of the invention disclosed in this application will be briefly described below.
In the liquid crystal display controller are provided a drive duty selection register (also referred to as display line control register) that can be rewritten from a microprocessor and a drive bias selection register. In a liquid crystal display panel capable of displaying 4 rows, when the whole surface display (e.g., 4-row display) is changed to the display of a few rows only (e.g., 1-row display), preset values of the drive duty selection register and of the drive bias selection register are dynamically changed by the microprocessor. Thus, part of the liquid crystal display panel is selectively displayed at a low voltage on a low-duty drive.
A value set in the drive duty selection register can be regarded as data for specifying or controlling the number of rows to be displayed on the liquid crystal panel. Due to this specifying data, the number or kind of common shift registers to be used is selected.
Concretely speaking, in a common shift register (see
The preset value of the drive duty selection register is also used for setting the period of the shift clocks of the common shift register. That is, in a liquid crystal display panel capable of displaying 4 rows, when the display period of one frame in the whole surface display (4-row display) is, for example, 80 Hz, the display period of one row or two rows is 80 Hz as shown in
Moreover, the liquid crystal display controller is provided with a boosting circuit capable of changing the boosting power as desired. The boosting power of the boosting circuit is controlled by a boosting power selection register provided in the liquid crystal display controller. When the liquid crystal display panel is changed from the whole surface display to the display of a portion thereof only, a preset value of the boosting power selection register is dynamically changed by the microprocessor, so that the boosted voltage outputted from the boosting circuit is lowered. The boosting circuit has only one output terminal contributing to decreasing the number of terminals of the liquid crystal display controller and, hence, to decreasing the cost of the liquid crystal display controller.
By using the above-mentioned means, only part of the rows on the liquid crystal display panel can be selectively driven (at a low duty) by the instruction by the microprocessor, making it possible to lower the operating frequency of the common shift register and the voltage for driving the liquid crystal. This makes it possible to suppress a total amount of electric power consumed by the liquid crystal display controller. Moreover, owing to the provision of a drive bias selection register, an optimum drive bias can be changed with a change in the drive duty, making it possible to prevent the contrast from lowering. When the liquid crystal display panel is driven at a low duty, furthermore, the boosting power of the boosting circuit can be set at a low value in accordance with a preset value of the boosting power-selection register, lowering the boosted voltage to a minimum required limit. This makes it possible to lower the operation voltage of the liquid crystal drive power supply circuit, improving the efficiency of the boosting circuit and, hence, further suppressing the electric current consumed by the liquid crystal display controller.
Desirably, furthermore, a centering display instruction register is provided in the liquid crystal display controller. The preset value of the centering display instruction register is selectively set by the microprocessor. This makes it possible to display dot-matrix characters at a position easiest to view, e.g., at the central portion of the liquid crystal display panel in the stand-by state of the system such as a portable telephone set. In the case of, for example, a liquid crystal panel capable of displaying dot-matrix characters on 4 rows, the display can be controlled so as to display only on the second row from the above, only on the second and third rows from the above, etc. When the display is produced only on the second row from the above or only on the second and third rows from the above, corresponding common signal lines are driven at a selection level. For the rows (non-display rows) that are not selected as display rows, the common signal lines are driven at a non-selection level. In this case, the preset value of the centering display instruction register and the preset value of the drive duty selection register are fed to the shift control circuit (see
a), 5(b) and 5(c) are diagrams of displays on a liquid crystal display panel at the time of 1/32, 1/16 and ⅛ duty drives from COM1;
a), 8(b) and 8(c) are diagrams of displays on the liquid crystal display panel at the time of 1/32, 1/16 and ⅛ duty drives from COM9;
The liquid crystal display controller 2 includes a system interface circuit 4 for transferring signals to and from the microprocessor 3 that includes a central processing unit (CPU), an instruction register 5 for setting internal control data, a display data RAM (display memory) 7 for storing character codes of characters displayed on the screen of the liquid crystal panel 1, an address counter 6 for reading out display data from the display data RAM 7 in accordance with the drive positions of the liquid crystal display panel 1, a character generator memory 8 for expanding a character font pattern in the form of a dot-matrix from the character codes read out from the display data RAM 7, a parallel/serial converter circuit 9 for converting display data of a plurality of bits read out from the character generator memory 8 into serial data, a segment shift register 12 for shifting the converted display data and for holding one line of shifted display data, a latch circuit 13 for holding one line of shifted display data, a segment driver 14 for generating and outputting drive voltage waveforms applied to the segment electrodes of the liquid crystal display panel 1 based upon the display data that are being held, a common shift register 15 for generating signals for successively selecting common electrodes of the liquid crystal display panel 1, a common driver 16 for generating and outputting drive voltage waveforms applied to the common electrodes, a timing generation circuit 10 for generating timing signals that specify display positions for the display data memory 7 and for generating clock signals that give display timings for the shift registers 12 and 15, a boosting circuit 11 for generating a liquid crystal drive voltage based on a power supply voltage Vci from the system power supply 40, a liquid crystal drive bias circuit 18 for generating a liquid crystal drive bias voltage based on the boosted voltage, a power supply circuit 17 made up of a voltage follower (operational amplifier) that subjects the bias voltage generated by the liquid crystal drive bias circuit 18 to the impedance conversion and outputs it, and a liquid crystal drive voltage selection circuit 19 that selects a desired bias voltage out of bias voltages generated by the power supply circuit 17 and supplies it to the segment driver circuit 14 and to the common driver circuit 16. Upon receipt of a clock CLK supplied from an external unit, a clock pulse generation circuit CPG outputs an internal clock 0 to the timing signal generation circuit 10.
The liquid crystal display controller 2 is formed on a semiconductor chip as a semiconductor integrated circuit (LSI) of complementary metal/insulating film/semiconductor field-effect transistors (CMOS) by using a known technology for fabricating semiconductor integrated circuits. In
In the liquid crystal display controller 2 of this embodiment, the microprocessor 8 writes, through the system interface 4, the code of a character to be displayed on the display data RAM 7, correspondingly to the display positions, so that any character stored in the character generator memory 8 can be displayed. When the microprocessor 3 sets various control data for producing liquid crystal display in the instruction register 5 via the system interface 4, the controller controls the display in accordance with control data that have been set. Writing the data in the display data RAM 7 is started as the microprocessor 3 sets the first address of the character string to be displayed in the address counter 6. Thereafter, the address counter 6 automatically updates the address, and the character codes input from the microprocessor 3 are successively written in the display data RAM 7.
The display data (character codes) are successively read out as the display address signals generated by the timing generation circuit 10 are sent to the display data RAM 7, and the character patterns stored in the character generator memory 8 are read out, with the character codes as addresses. Furthermore, the character patterns are converted into serial data through the parallel/serial converter 9, and successively sent to the segment shift register 12 in the segment drive circuits (12, 13, 14). When one line of data are stored in the segment shift register 12, the data is latched in the latch circuit 13 simultaneously, the segment driver 14 selects a turn-on/turn-off voltage from the latched data and outputs it to the liquid crystal display panel 1. The level of the turn-on/turn-off voltage is generated by the liquid crystal drive voltage selector 19.
When a character font pattern constituted by, for example, 5×8 dots is displayed in 4 rows in the vertical direction, the common driver 16 requires a total of 32 output circuits since each display row has 8 lines. As shown in
In the liquid crystal display panel 1 capable of producing a display of up to four rows, the whole-surface display using four rows is not-in many cases required in the stand-by state of the system. During the stand-by period, for example, data such as time and date only are displayed on two rows or on one row. In a conventional liquid crystal display controller, the common drive signal has been output even to the rows in which no display is produced and a voltage of the turn-off level has been applied to the segment electrodes. Accordingly, the consumption of electric power has not been able to be decreased though the display is produced on a decreased number of rows only. According to the present invention, the common shift register 12 is so operated that the common drive signal is not applied to the rows in which no display is produced. This makes it possible to decrease the amount of electric power consumed by the liquid crystal display controller 1 in the stand-by state.
In this case, too, however, the selection level is output in the ranges of from COM1 to COM16 ( 1/16 duty drive) and from COM1 to COM8 (⅛ duty drive) as shown in
In this embodiment, therefore, when the display is produced on 2 rows or on 1 row, the selection drive from the common drive signal COM1 up to the common drive signal COM8 is skipped as shown in
The drive duty selection register 34 has, for example, two control bits NL1 and NL0, and selects a 4-row display ( 1/32 duty drive) when the value of NL1 and NL0 is “00”, selects a 2-row display ( 1/16 duty drive) when the value is “01”, and selects a 1-row display (⅛ duty drive) when the value is “10”. The centering display instruction register 31 has a control bit CEN, and does not select the central display when the value of CEN is “0” and selects the central display when the value is “1”.
The microprocessor 3 sets predetermined values in the drive duty selection register 34 and in the centering display instruction register 31. Based on the drive duty value in the drive duty selection register 34, the liquid crystal display controller 2 adjusts the period of a shift clock signal SCLK of the common shift register 15 generated by the timing generation circuit 10. For example, when the drive duty is changed from the 4-row display to the 2-row display, the period of the shift clock is doubled in order to maintain constant the frame period which is, for example, 80 Hz. When the drive duty is changed to 1-row display, furthermore, the period of the shift clock is lengthened four times. That is, the timing generation circuit 10 includes a clock frequency-dividing circuit capable of varying the frequency-dividing ratio. The frequency-dividing ratio of the clock frequency-dividing circuit is controlled based upon the drive duty value set in the drive duty selection register 34.
The drive duty value set in the drive duty selection register 34 is also supplied to the shift control circuit 35 to select a plurality of flip-flops among the flip-flops F/F1 to F/F32 according to the drive duty value that is set. The flip-flops F/F1 to F/F8 are used for producing a display on the first row of the liquid crystal panel 1, the flip-flops F/F9 to F/F 16 are used for producing a display on the second row of the liquid crystal panel 1, the flip-flops F/F17 to F/F24 are used for producing a display on the third row on the liquid crystal panel 1, and the flip-flops F/F25 to F/F32 are used for producing a display on the fourth row on the liquid crystal panel 1. Therefore, when the value of control bit CEN of the centering display instruction register 31 is “0”, the flip-flops F/F1 to F/F32 are selected by the shift control circuit 35 in the case of the 4-row display ( 1/32 duty drive), the flip-flops F/F1 to F/F16 are selected by the shift control circuit 35 in the case of the 2-row display ( 1/16 duty drive), and the flip-flops F/F1 to F/F9 are selected by the shift control circuit 35 in the case of the 1-row display (⅛ duty drive).
The preset value of the centering display instruction register 31 is supplied to the shift control circuit 35 which, at the time of a normal whole-surface display (4-row display), shifts the value “1” used as a shift register selection data from the flip-flop F/F1 to the flip-flop F/F32 successively, so that common signals of the selection level are output in a time-division manner from the common driver 16. During the period in which the shift register selection data “1” is being input, the flip-flops F/F1 to F/F32 selectively output signals CSF1 to CSF32 of the selection level to the common driver 16. Therefore, the common driver 16 discriminates common signal lines to be at the selection level, and outputs the corresponding common signals COM1 to COM32 of the selection level. When the system such as a-portable telephone set is in the stand-by state, the shift register selection data “1” is successively shifted from, for example, the flip-flop F/F9 to the flip-flop F/F24 based on the preset value (CEN=“1”) of the centering display instruction register 31 and on the drive duty value (NL1−NL0=“01”: 2-row display ( 1/16 duty drive)) set in the drive duty selection register 34, so that the common driver 16 outputs common signals of the selection level to the common lines of the central two rows in a time-division manner.
In general, lowering the drive duty lengthens the time taken to select the lines, and the display on the whole panel can be easily turned on. Therefore, to maintain the same contrast even after the drive duty is lowered, it is necessary to lower the liquid crystal drive voltage and the drive bias. Moreover, by lowering the liquid crystal drive voltage to decrease the drive duty, the merit of decreasing the consumption of electric power is obtained. In particular, in the liquid crystal display controller that requires a liquid crystal drive voltage higher than the voltage of the system power supply 40, it is necessary to generate the liquid crystal drive voltage by boosting the system power supply voltage. In this case, when the current is supplied to the circuits (11 to 18) of the liquid crystal drive system through the boosting circuit 11, the current consumption viewed from the system power supply side increases to, for example, two or three times the power depending upon the boosting power. Besides, the boosting efficiency of the boosting circuit 11 decreases with an increase in the boosting power. Therefore, when the current is supplied to the circuits (11 to 18) in the liquid crystal drive system through the boosting circuit 11, it is advantageous to lower the boosting power to a required minimum degree from the standpoint of suppressing the consumption of electric current.
In this embodiment, furthermore, the period of selection level of the common signals is increased two times or four times when the drive duty is decreased to ½ or ¼ to produce a display on 2 rows or on 1 row. This makes it possible to lower the drive duty without changing the frequency of 1 frame. That is, a decrease only in the drive duty results in an increase in the frame frequency and a deterioration of the picture quality. In this embodiment, however, the drive duty is lowered without changing the frame frequency and avoiding a deterioration of the picture quality.
The control operation of increasing the period of selection level of the common signals to 2 times or 4 times when the drive duty is lowered to ½ and ¼, can be easily realized by lowering the frequency of the clock signals supplied to the common shift register 15 from the timing generation circuit 10 down to ½ and ¼. Thus, since the frequency of the clock signals is lowered when the drive duty is lowered to ½ and ¼, the operating frequency of the internal circuit constituted by the CMOS circuit is lowered, producing an advantage of a decrease in the consumption of electric power.
In this embodiment as shown, a boosting power selection register 33 is provided corresponding to the boosting circuit 11. The microprocessor 3 sets a desired boosting power in the boosting power selection register 33 in the instruction register 5, so that the boosting power of the VLOUT output of the boosting circuit 11 can be arbitrarily changed from 1 power to 3 power.
Though there is no particular limitation, the boosting power selection register 33 is provided in the instruction register 5. A basic voltage Vci may be the one (e.g., 2.8 V) lower than Vcc obtained by dividing the power supply voltage Vcc (e.g., 3 V) by using resistors. A voltage lower than the power supply voltage Vcc is used as the basic voltage Vci for the boosting circuit 11. This is because, when the liquid crystal display panel 1 of this embodiment is driven, the liquid crystal drive voltage may be about 8 V even when it is driven at the highest duty. Besides, the consumption of electric power increases with an increase in the boosted voltage as described Therefore, the voltage must not be too high when the boosting power is increased to a maximum of 3 power.
As shown in Table 1, the boosting power selection register 33 has control bits BT1 and BT0. When the bits BT1, BT0 are “00”, the boosting circuit 11 ceases to operate, and the terminal VLOUT outputs a ground potential GND. When the control bits BT1, BT0 are “01”, the boosting power of the boosting circuit 11 becomes one, and the terminal VLOUT outputs a basic voltage Vci. When the control bits BT1, BT0 are 10, the boosting power of the boosting circuit 11 becomes two, and the terminal VLOUT outputs a voltage 2 times the basic voltage Vci. When the control bits BT1, BT0 are “11”, the boosting power of the boosting circuit 11 becomes three, and the terminal VLOUT outputs a voltage 3 times the basic voltage Vci.
As shown in
At the time of 2 power boosted voltage or 3 power boosted voltage as shown in
As described above, the boosting power of the boosting circuit 11 is arbitrarily set. When the liquid crystal needs to be driven at a low voltage, therefore, the boosting power is lowered to a required minimum limit, decreasing the operating voltages of the drive bias circuit 18 and the power supply circuit 17 serving as a power supply circuit for driving the liquid crystal, and improving the efficiency of the boosting circuit 11. This makes it possible to greatly suppress the electric current consumed by the controller 2.
Next, below will be concretely described a method of setting the boosting power of the boosting circuit 11. Assuming that the liquid crystal drive voltage is, for example, 8 V when the display is produced on 4 rows by the 1/32 duty drive, the boosting circuit 11 must boost the voltage by three times when the system power supply voltage is 3 V. Therefore, the data for instructing 3 power boosting is set in the boosting power selection register 33 from the microprocessor 3. Even when the display needs be produced on 1 row only while the system is in the stand-by state, the liquid crystal drive voltage is boosted by three times, i.e., is 8 V if the 1/32 duty drive is maintained, and the electric current consumed by the controller 2 cannot be decreased. Therefore, the data for instructing the ⅛ duty drive is set in the drive duty selection register 34 by the microprocessor 3 to thereby change the duty ratio. Furthermore, the data for instructing 2 power boosting is set in the register 33 by the microprocessor 3, so that the liquid crystal drive voltage is set to be about 5 V. Thus, a sufficiently large liquid crystal drive voltage is obtained even when the operation of the boosting circuit 11 is changed to 2 power boosting by the boosting power selection register 33, making it possible to decrease the consumption of electric current, when viewed from the system power supply 40 of 3 V to about two-thirds.
To obtain a favorable contrast after the liquid crystal drive duty is changed, furthermore, it is desirable to optimize the drive bias ratio. In general, when the drive duty is 1/N, the optimum drive bias ratio B for obtaining an optimum contrast is,
B=1/(√/N+1)
For example, the optimum drive biases at ⅛ duty, 1/16 duty and 1/32 duty are ¼ bias, ⅕ bias and 1/6.7 bias.
As shown in Table 2, the drive bias selection register 32 includes control bits BS2, BS1 and BSO. When the control bits BS2, BS1 and BS0 are set at “000”, the liquid crystal drive bias becomes 1/6.5 bias, whereby the switches SW1, SW4 and S1 are turned on and an equivalent circuit shown in
In
In
Next, the AC drive will be described with reference to
In the first frame (frame I), the selection level of the common signal COM2 is V1 and the non-selection level is V5. In the first frame (frame I), the selection level of the segment signal SEG2 is GND and the non-selection level is V4. Any dot turns on when the voltage obtained by subtracting the potential of the segment signal from the potential of the common signal, exceeds the threshold value of the liquid crystal. The difference in the potential is used as a pixel signal D. Therefore, the dot at the intersecting point of the transparent electrode ECOM2 and the transparent electrode ESEG2 is turned on. In the second frame (frame II), the selection level of the common signal COM2 is GND and the non-selection level is V2. In the first frame (frame I), the selection level of the segment signal SEG2 is V1 and the non-selection level is V3. Therefore, the dot at the intersecting point of the transparent electrode ECOM2 and the transparent electrode ESEG2 turns on. Thus, the polarities of selection level and non-selection level are inverted between the first frame (frame I) and the second frame (frame II). Such a drive method is called AC drive (AC bias), and the liquid crystal is effectively prevented from being deteriorated.
The portable telephone system shown in
The liquid crystal display panel 1 shown in
The liquid crystal display controller 2 of this embodiment is suited for driving a liquid crystal panel 140 that is capable of displaying both segments such as marks, icons, patterns and numerals, and dot matrices such as characters and numerals as shown in
The common driver 15, too, is changed for the liquid crystal display controller 2 shown in
The internal control bits of the drive duty selection register 34 are changed into three bits NL2 to NL0.
As shown in
The common shift register 15 of
That is, the flip-flops 25 and 26 generate segment common drive signals COMS1 and COMS2. The following operation is carried out when the control bit CEN of the centering display instruction register 31 is “0”. When the drive duty is ½, the shift register selection data “1” is shifted only to the flip-flop 25 and 26 to produce driver selection signals CSSF1 and CSSF2. When the drive duty is 1/10, the shift register selection data “1” is shifted to the flip-flops 1 to 9, 25 and 26 to produce driver selection signals CSF1 to CSF9, CSSF1 and CSSF2. When the drive duty is 1/18, the shift register selection data “1” is shifted to the flip-flops 1 to 16, 25 and 26 to produce driver selection signals CSF1 to CSF16, CSSF1 and CSSF2. When the drive duty is 1/26, the shift register selection data “1” is shifted to the flip-flops 1 to 24, 25 and 26 to produce driver selection signals CSF1 to CSDF24, CSSF1 and CSSF2.
When the control bit CEN of the centering display instruction register 31 is set at “1” by the microprocessor 3, the microprocessor 3 sets NL2 to NL0 at “001” and sets the drive bias selection registers BS2 to BS0 at “101”.
In the embodiment as described above, the liquid crystal display controller is provided with a drive duty selection register that can be rewritten by the microprocessor, and a drive bias selection register. When the display on the whole surface of the liquid crystal display panel is changed to the display of part of the rows, the preset values of the drive duty selection register and of the drive bias selection register are changed, so that the display is selectively produced on part of the liquid crystal display panel at a low voltage with a low-duty drive. Thus, only a portion of the liquid crystal display panel is selectively driven by the microprocessor at a low duty, making it possible to lower the operation frequency of the internal shift register and the voltage for driving the liquid crystal and, hence, to suppress the total electric current consumed by the whole liquid crystal display controller. Furthermore, the optimum drive bias is changed depending upon a change in the drive duty, making it possible to prevent the lowering of the contrast.
Moreover, provision is made of a boosting power selection register capable of setting the boosting power of the boosting circuit, and the boosting power of the boosting circuit is set to be low according to a decrease in the duty ratio. Accordingly, it is made possible to lower the boosted voltage to a required minimum limit and, hence, to lower the operation voltage of the liquid crystal drive power supply circuit, to improve the efficiency-of the boosting circuit and to suppress the electric current consumed by the semiconductor integrated circuit device 2.
Since the centering display instruction register is provided in the liquid crystal display controller, the display on part of the rows in the stand-by state is specified at a position where it can be most easily viewed, e.g., at a central portion on the liquid crystal display panel.
Though the invention accomplished by the present inventors has been concretely described above by way of embodiments, it should be noted that the present invention is in no way limited to the above-mentioned embodiments only but can be modified in various ways without departing from the spirit and scope of the invention. The above-mentioned embodiments have dealt with the liquid crystal display controller of the type that is successively driven line by line in a time-division manner. The invention, however, can also be applied to a liquid crystal display controller of the type which simultaneously and sequentially drives a plurality of lines. The above embodiments have dealt with the case where the display position of part of the rows is at the center of the screen in the stand-by state. It is, however, also possible to provide a register for setting the display position in the stand-by state, so that the display can be made at any position.
The above-mentioned embodiments have dealt with the case where the display portion of the liquid crystal display panel is constituted by a dot-matrix capable of displaying 4 character rows. By changing the number of the common drivers, however, the invention can be adapted to a liquid crystal display controller for driving a liquid crystal display panel capable of displaying 3 character rows or 5 or more character rows. In some portable telephone sets and the like, a pictogram where an antenna mark, a mark indicating the reception level, etc. is provided at the top portion or the bottom portion on the screen, and are generally constituted by electrodes of shapes corresponding to the marks. In this case, the common drivers in the liquid crystal display controllers should be so constituted as to output one more or two more common signals for the pictogram. Namely, only those common signals corresponding to the pictogram are selectively driven, but the character display portion is driven at the non-selection level at all times, to realize a low-duty drive such as 1/1 duty (static) drive, ½ duty, etc.
The foregoing description has-chiefly dealt with the case where the invention is adapted to the liquid crystal display controller which is in the field of utilizing the invention. The present invention, however, is in no way limited thereto only and can be utilized for controlling the drive of various display devices such of as phosphor indicator tube, or plasma display.
The effect obtained by a representative of the aspects of the invention disclosed in this application will be described below.
In the liquid crystal display controller for controlling a plurality of display rows, it is possible to decrease the consumption of electric current when the display needs not be produced on the whole rows such as in the stand-by state of the system. Since the control operation is entirely executed by the microprocessor with software, the liquid crystal is driven according to the operating state of the system consuming a minimum amount of electric power.
Number | Date | Country | Kind |
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9-16935 | Jan 1997 | JP | national |
This application is a continuation of U.S. patent application Ser. No. 12/709,929, filed Feb. 22, 2010, which is a continuation of U.S. patent application Ser. No. 11/594,190, filed Nov. 8, 2006, now U.S. Pat. No. 7,688,303, which is a continuation of U.S. patent application Ser. No. 10/778,165, filed Feb. 17, 2004, now U.S. Pat. No. 7,286,110, which is a continuation of U.S. patent application Ser. No. 10/279,987, filed Oct. 25, 2002, now U.S. Pat. No. 6,747,628, which is a continuation of U.S. patent application Ser. No. 09/621,618, filed Jul. 21, 2000, now U.S. Pat. No. 6,633,274, which is a continuation of U.S. patent application Ser. No. 09/015,332, filed Jan. 29, 1998, now U.S. Pat. No. 6,181,313, the contents of which are hereby incorporated by reference into this application.
Number | Date | Country | |
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Parent | 12709929 | Feb 2010 | US |
Child | 13487771 | US | |
Parent | 11594190 | Nov 2006 | US |
Child | 12709929 | US | |
Parent | 10778165 | Feb 2004 | US |
Child | 11594190 | US | |
Parent | 10279987 | Oct 2002 | US |
Child | 10778165 | US | |
Parent | 09621618 | Jul 2000 | US |
Child | 10279987 | US | |
Parent | 09015332 | Jan 1998 | US |
Child | 09621618 | US |