Patent Application
20100033413
This application claims the benefit of Korean Patent Application No. 10-2008-0078172 filed on Aug. 8, 2008, which is incorporated herein by reference for all purposes as if fully set forth herein.
1. Field of the Invention
This document relates to a liquid crystal display device, which can improve display grade, and a driving method thereof.
2. Related Art
A liquid crystal display device controls the light transmittance of a liquid crystal layer by an electric field applied to the liquid crystal layer in accordance with video signals to display a picture. As the liquid crystal display devices are thin and flat panel display devices having low power consumption, the liquid crystal display devices are used as displays for portable computers such as laptop computers, office automation devices, audio/video devices, and the like. Especially, an active matrix type liquid crystal display device where a switching device is formed for each liquid crystal cell is advantageous in realizing motion pictures because the switching device can be actively controlled.
The switching device used in the active matrix type liquid crystal display device is mainly a thin film transistor (hereinafter, referred to as “TFT”), as in
Referring to
However, when a DC voltage is applied for a long time to the liquid crystal layer of the liquid crystal display device, ions having negative charges are moved in the same motion vector direction and ions having positive charges are moved in the opposite motion vector direction in accordance with the polarity of an electric field applied to the liquid crystal, and polarized, and the accumulated amount of the ions having negative charges and the accumulated amount of the ions having positive charges are increased with time. As the accumulated amount of the ions increases, the orientation layer is deteriorated, and as a result, the orientation characteristic of the liquid crystal is deteriorated. Due to this, when a DC voltage is applied for a long time to the liquid crystal display device, a blur appears on a displayed image, and the blur becomes larger with time. To overcome this blur, a method of developing a liquid crystal material having a low dielectric constant or a method of improving an orientation material or orientation method has been attempted. However, this method requires a lot of time and cost to develop materials, and the lowering of the dielectric constant of liquid crystal may cause another problem of deterioration of the driving characteristics of the liquid crystal. According to experimentally obtained results, the more the impurities to be ionized in the liquid crystal layer, and the higher the acceleration factors, the faster the point of time of blur appearance. The acceleration factors include temperature, time, DC driving of liquid crystal, etc. Accordingly, the higher the temperature or the longer the period of time for applying a DC voltage of the same polarity to the liquid crystal layer, the faster a blur appears and the more severe the degree of the blur. Moreover, since a blur is different in shape and degree even in panels of the same model manufactured by the same manufacturing line, this cannot be solved only by developing a new material or by improving the process.
An aspect of this document is to provide a liquid crystal display device, which suppresses a blur phenomenon caused by the polarization and accumulation of ions to increase a display grade by sequentially varying the level of a common voltage applied to a liquid crystal layer at specific frame intervals and sequentially varying the level of a gamma reference voltage of a black gray level in accordance with a change in the level of the common voltage.
To achieve the above advantages, there is provided a liquid crystal display device according to an exemplary embodiment of the present invention, comprising: a liquid crystal display panel for displaying gray levels by a potential difference between a common electrode for applying a common voltage and pixel electrodes for applying data voltages; a common voltage regulating circuit for generating a variable common voltage which is longitudinally symmetrical with respect to a DC common voltage of a predetermined level and whose voltage level is stepwisely varied at predetermined intervals; and a black gamma reference voltage regulating circuit for adding the variable common voltage to an offset voltage set as a gamma reference voltage of a black gray level to generate a variable gamma reference voltage varying with respect to the gamma reference voltage of the black gray level, the variable gamma reference voltage of the black gray level being varied in synchronization with the variable common voltage.
The level of the variable common voltage is stepwisely varied during a second period, and maintained as the DC common voltage during a first period prior to the second period.
The common voltage regulating circuit comprises: a multistep common voltage generator for generating a multistep common voltage whose voltage level is stepwisely varied at the predetermined intervals; and a common voltage adder for generating the variable common voltage by selectively outputting the DC common voltage and the multistep common voltage.
The multistep common voltage generator comprises: a control clock generator for counting a number of frames by using an input timing control signal and generating a control clock every time an accumulated count value becomes a multiple of a predetermined value; a control data generator for generating control data of specific bits, whose digital value is stepwisely increased or decreased at the predetermined intervals, in synchronization with the control clock; a memory for storing a switch control signal corresponding to the control data in a lookup table; a register for reading out the switch control signal from the memory by using the control data as a read address; a decoder for decoding the read-out switch control signal and outputting the same; a resistor string for dividing a high potential power voltage and a low potential power voltage and generating a plurality of voltages whose levels are different from each other; and a switch array for connecting to a supply line for supplying the multistep common voltage to any one of a plurality of divided voltage output nodes formed in the resistor string in response to the decoded switch control signal.
The generation cycle of the control clock is determined in consideration of the polarization and accumulated amount of ions in the liquid crystal layer in accordance with the time and temperature at which a DC voltage is applied to the liquid crystal layer of the liquid crystal display panel.
The liquid crystal display device further comprises a data check signal generator, and the data check signal generator comprises: a frame memory for storing digital video data for one frame inputted from an external system board; and a data check unit for storing in advance a specific data pattern that may cause flicker, and then comparing the specific data pattern with the digital video data of the one frame and generating a data check signal at a first logic level if both are the same and at a second logic level if both are different.
The common voltage adder comprises a multiplexer for outputting the DC common voltage in response to the data check signal of the first logic level and outputting the multistep common voltage in response to the data check signal of the second logic level.
The common voltage adder comprises: a frame counter for generating count information about the number of frames by counting an input timing control signal; a selection signal generator for comparing the count information with a predetermined reference value and generating a selection signal at a first logic level if the count information is lower than the reference value and at a second logic level if the count information exceeds the reference value; and a multiplexer for outputting the DC common voltage in response to the selection signal of the first logic level and outputting the multistep common voltage in response to the selection signal of the second logic level.
The common voltage adder comprises a multiplexer for outputting the DC common voltage in response to option pin touch information set to the first logic level and outputting the multistep common voltage in response to the option pin touch information set to the second logic level.
A driving method of a liquid crystal display device having a liquid crystal display panel according to an exemplary embodiment of the present invention, which displays gray levels by a potential difference between a common electrode for applying a common voltage and pixel electrodes for applying data voltages, comprises: generating a variable common voltage which is longitudinally symmetrical with respect to a DC common voltage of a predetermined level and whose voltage level is stepwisely varied at predetermined intervals; and adding the variable common voltage to an offset voltage set as a gamma reference voltage of a black gray level to generate a variable gamma reference voltage varying with respect to the gamma reference voltage of the black gray level, the variable gamma reference voltage of the black gray level being varied in synchronization with the variable common voltage.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
In the drawings:
Hereinafter, an implementation of this document will be described in detail with reference to
Referring to
In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes m x n liquid crystal cells Clc arranged in a matrix type by a structure in which m data lines DL and n gate lines Gl intersect each other.
Formed on the lower glass substrate of the liquid crystal display panel 10 are data lines DL, gate lines GL, TFTs, and storage capacitors Cst. The liquid crystal cells Clc are driven by an electric field between pixel electrodes 1 and a common electrode 2 by being connected to the TFTs. Formed on the upper glass substrate of the liquid crystal display panel 10 are a black matrix, color filters, and the common electrode 2. The common electrode 2 is formed on the upper glass substrate in devices employing a vertical electric field driving method, such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode. Alternatively, the common electrode 2 may be formed along with the pixel electrode 1 on the lower glass substrate in devices employing a horizontal electric field driving method, such as an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode. Polarizers are respectively applied to the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10. Alignment films for setting the pre-tilt angle of liquid crystal are then formed.
The timing controller 11 receives timing signals such as a data enable signal DE and a dot clock CLK signal, and generates control signals GDC and DDC for controlling the operation timing of the data drive circuit 12 and the gate drive circuit 13.
Gate timing control signals GDC for controlling the operation timing of the gate drive circuit 13 include a gate start pulse GSP which indicates a starting horizontal line from which a scan starts in a first vertical period when an image or data is displayed, a gate shift clock signal GSC which is inputted to a shift register within the gate drive circuit 13 and is generated to have a pulse width corresponding to the on-period of the TFT as a timing control signal for sequentially shifting the gate start pulse GSP, and a gate output enable signal GOE which indicates the output of the gate drive circuit 13.
Data timing control signals DDC for controlling the operation timing of the data drive circuit 12 include a source sampling clock SSC which indicates a latch operation of the data within the data drive circuit 12 on the basis of a rising or falling edge, a source output enable signal SOE which indicates the output of the data drive circuit 12, and a polarity control signal POL which indicates the polarity of the data voltage which is to be supplied to the liquid crystal cell Clc of the liquid crystal display panel 10 and the like.
Further, the timing controller 11 re-aligns digital video data RGB inputted from an external system board in accordance with the resolution of the liquid crystal display panel 10 to supply to the data drive circuit 12. The timing controller 11 supplies a gate start pulse GSP to the common voltage regulating circuit 15.
The data drive circuit 12 converts the digital video data RGB into an analog gamma compensation voltage on the basis of gamma reference voltages GMA_G/W of a gray level or white gray level which are supplied from a gamma reference voltage generator (not shown) in response to a data control signal DDC from the timing controller 11, and supplies the analog gamma compensation voltage as a data voltage of a gray level or white gray level to the data lines DL of the liquid crystal display panel 10. Further, the data drive circuit 12 converts the digital video data RGB into an analog gamma compensation voltage, whose level is sequentially varied, on the basis of variable gamma reference voltages MGMA_B of a black gray level supplied from the black gamma reference voltage regulating circuit 18 in response to a data control signal DDC from the timing controller 11, and supplies the analog gamma compensation voltage as a data voltage of a black gray level to the data lines DL of the liquid crystal display panel 10. Although described later, the variable gamma reference voltages MGMA_B of the black gray level have a different level at specific frame intervals in synchronization with a change in the level of a variable common voltage MVcom. Since the liquid crystal display device according to the present invention is inversely driven, the gamma reference voltages GMA_G/W and GMA_B of the gray level/white gray level and the black gray level, respectively, include positive and negative polarity voltages having the same level with respect to a DC common voltage Vcom_DC. While the gamma reference voltages GMA_G/W of the gray level/white gray level are directly applied to the data drive circuit 12 from the gamma reference voltage generator, the gamma reference voltages GMA_B of the black gray level outputted from the gamma reference voltage generator are applied to the data drive circuit 12 after being varied through the black gamma reference voltage regulating circuit 18.
In order to convert the digital video data RGB into an analog gamma compensation voltage, the data drive circuit 12 is configured to have a plurality of data drive ICs, each of which comprises a shift register for sampling the clock signal, a register for temporally storing the digital video data RGB, a latch for storing the data for each line in response to the clock signal from the shift register and for outputting the stored data of the one line portion at the same time, a digital/analog converter for selecting a positive/negative gamma voltage with reference to the gamma reference voltage in correspondence to the digital data value from the latch, a multiplexer for selecting the data line to which the analog data converted by the positive/negative gamma voltage are supplied, and an output buffer connected between the multiplexer and the data line DL.
The gate drive circuit 13 sequentially supplies the scan pulse, which selects the horizontal line of the liquid crystal display panel 10 to which the data voltage is supplied, to the gate lines GL. To this end, the gate drive circuit 13 is configured to have a plurality of gate drive ICs, each of which comprises a shift register, a level shifter for converting a swing width of an output signal of the shift register into a swing width which is suitable for driving the TFT of the liquid crystal cell Clc, and an output buffer connected between the level shifter and the gate line GL.
The common voltage regulating circuit 15 generates a variable common voltage MVcom which has the same level as the DC common voltage Vcom_DC during a preset initial period, and which is longitudinally symmetrical with respect to the DC common voltage Vcom_DC and swung in multisteps during a normal driving period. To this end, the common voltage regulating circuit 15 includes a multistep common voltage generator 14 and a common voltage adder 16. The multistep common voltage generator 14, as shown in
The black gamma reference voltage regulating circuit 18 generates a variable gamma reference voltage MGMA_B of a black gray level by using the gamma reference voltage GMA_B of the black gray level supplied from the gamma reference voltage generator as an offset voltage and adding the variable common voltage MVcom supplied from the common voltage regulating circuit 15 to the offset voltage. To this end, the black gamma reference voltage regulating circuit 18 comprises a voltage synthesis circuit, and this voltage synthesis circuit matches the level of the DC common voltage Vcom_DC, which is an intermediate level of the variable common voltage MVcom, with the level of the gamma reference voltage GMA_B of the black gray level to add both of them. The variable gamma reference voltage MGMA_B of the black gray level comprises, as shown in
Referring to
The control clock generator 141 comprises a frame counter for counting a number of frames in synchronization with the gate start pulse GSP supplied from the timing controller 11 and generating a control clock SCL as shown in
The control data generator 142 generates control data SDA of specific bits (for example, 6 bits) in synchronization with the control clock SCL from the control clock generator 141. If the control data SDA is of 6 bits, a binary code of the control data SDA sequentially and repetitively increases and decreases between 0 to 63 levels in synchronization with the control clock SCL. To this end, the control data generator 142 may be implemented as a linear feedback shift register (LFSR). The linear feedback shift register LFSR is a shift register whose input bit is a linear function of its previous state, and can generate a pseudo-random bit sequence having a long period if a proper feedback function is selected. Meanwhile, it is natural that the control data SDA is not limited to 6 bits but may have a number of bits greater or less than that.
The memory 143a comprises a nonvolatile memory capable of updating and erasing data, for example, an EEPROM (Electrically Erasable Programmable Read Only Memory) and/or an EDID ROM (Extended Display Identification Data), and stores control data SDA increased or decreased in synchronization with the control clock SCL and a switch control signal Φ corresponding to the control data SDA by using a lookup table.
The register 143 reads out the switch control signal Φ stored in the memory 143a in accordance with the control clock SCL by using the control data SDA from the control data generator 142 as a read address, and then supplies the read-out switch control signal Φ to the decoder 144. The switch control signal Φ outputted from the register 143 may be composed of a digital signal of 6 bits.
The decoder 144 decodes the switching control signal Φ from the register 143, and outputs the decoded switch control signal Φ through an output pin corresponding to the digital value of the switch control signal Φ. The decoder 144 has 64 output pins P0 to P63 so as to correspond to the switch control signal Φ of 6 bits. The output pins P0 to P63 are respectively connected to the gate terminals G of switches T0 to T63 constituting the switch array 145.
The switch array 145 comprises a plurality of switches T0 to T63. The gate terminals G of the switches T0 to T63 are respectively connected to the output pins P0 to P63 of the decoder 144 to receive a switch control signal Φ. Drain terminals D of the switches T0 to T63 are respectively connected to divided voltage output nodes n0 to n63 formed between adjacent resistors R1 to R63 in the resistor string 146. Source terminals S of the switches T0 to T63 are commonly connected to a common voltage supply line VSL. Therefore, the switches T0 to T63 selects any one of a plurality of divided voltages as one of them is turned on in response to the switch control signal Φ from the decoder 144.
The resistor string 146 has a plurality of resistors R1 to R63 connected in series between a high potential power voltage VH and a low potential power voltage VL, and generates a plurality of divided voltages having a different level through the divided voltage output nodes n0 to n63 between the resistors. As shown in
Referring to
The data check signal CHdata is generated through a data check signal generator 11a as shown in
The multiplexer 161 generates a variable common voltage MVcom by selectively outputting a multistep common voltage Vcom_Multi and a DC common voltage Vcom_DC in response the data check signal CHdata from the data check signal generator 11a.
Accordingly, as shown in
Resultantly, during the initialization period T1 for setting an optimal point of a common voltage, the optimal point setting is easily and accurately done by preventing a swing of the variable common voltage MVcom. During the normal driving period T2, the polarization and accumulation of ions caused by a DC voltage of the same polarity applied to liquid crystal cells for a long time are prevented by stepwisely swinging the variable common voltage MVcom.
Referring to
The frame counter 261 generates count information CS about the number of frames by counting a gate start pulse GSP generated in one vertical period interval.
The selection signal generator 262 compares the count information CS from the frame counter 261 with a predetermined reference value r1, and generates a selection signal SEL at a first logic level L1 during an initialization period until the count information CS reaches the reference value r1 and at a second logic level L2 during a normal driving period in which the count information CS exceeds the reference value r1.
The multiplexer 263 generates a variable common voltage MVcom by selectively outputting a multistep common voltage Vcom_Multi and a DC common voltage Vcom_DC in response to the selection signal SEL from the selection signal generator 262.
Accordingly, as shown in
Resultantly, during the initialization period T1 for setting an optimal point of a common voltage, the optimal point setting is easily and accurately done by preventing a swing of the variable common voltage MVcom. During the normal driving period T2, the polarization and accumulation of ions caused by a DC voltage of the same polarity applied to liquid crystal cells for a long time are prevented by stepwisely swinging the variable common voltage MVcom.
Referring to
The option pin touch information OPT is generated at a first logic level L1 if an option pin P connected to the timing controller 11 is connected to a high potential voltage source VH by changing over the switch SW by the user and at a second logic level if the option pin P is connected to a low potential voltage source VL. The user typically connects the option pin P to the high potential voltage source VH during the initialization period and connects the option pin P to the low potential voltage source VL during the normal driving period.
The multiplexer 361 generates a variable common voltage MVcom by selectively outputting a multistep common voltage Vcom_Multi and a DC common voltage Vcom_DC in response to the option pin touch information OPT.
Accordingly, as shown in
Resultantly, during the initialization period T1 for setting an optimal point of a common voltage, the optimal point setting is easily and accurately done by preventing a swing of the variable common voltage MVcom. During the normal driving period T2, the polarization and accumulation of ions caused by a DC voltage of the same polarity applied to liquid crystal cells for a long time are prevented by stepwisely swinging the variable common voltage MVcom.
Referring to
As described above, the liquid crystal display device and driving method thereof according to the present invention can disperse the orientation and intensity of an electric field vector formed on the liquid crystal layer by sequentially varying the level of a common voltage applied to the liquid crystal layer at predetermined time intervals, and accordingly can greatly increase a display grade by suppressing a blur phenomenon caused by the polarization and accumulation of ions.
Furthermore, the liquid crystal display device and driving method thereof according to the present invention can easily and accurately achieve an optimal point setting by preventing a swing of the common voltage upon setting an optimal point of a common voltage for flicker, while dispersing the orientation and intensity of an electric field vector formed on the liquid crystal layer by sequentially varying the level of a common voltage applied to the liquid crystal layer at predetermined time intervals.
Furthermore, the liquid crystal display device and driving method thereof according to the present invention can eliminate a black luminance difference between a positive polarity black voltage and negative polarity black voltage of liquid crystal cells caused by the swing operation of the common voltage by varying the level of the gamma reference voltages of the black gray level in synchronization with the swing cycle and step change width of the common voltage.
As described above, it will be appreciated by those skilled in the art that various changes and modifications might be made without departing from the technical idea of the invention. Accordingly, the technical scope of this invention is not restricted by the description of the specification but defined by the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2008-0078172 | Aug 2008 | KR | national |
