1. Technical Field
The present disclosure relates to liquid crystal display, and more particularly to an LCD device and driving method thereof.
2 Description of Related Art
In a commonly used thin film transistor liquid crystal display (TFTLCD), content is displayed by rotating liquid crystal (LC) molecules inside the TFTLCD to specific attitudes to control a transparency (brightness) with adjusting bias voltages loaded to two sides of the TFTLCD. The LC molecules are permanently damaged and no longer rotate smoothly if electric fields generated by the bias voltages remain in the same direction for a long time. Hence, to prevent permanent damage, different driving methods with alternative directions of the bias voltages are provided, such as frame inversion, column inversion, line/row inversion and, dot inversion. Row inversion includes 1-line and 2-line row driving methods.
With reference to
Typically, a sequential square wave is input to a common electrode of the TFTLCD as a Vcom signal, referred to common voltages hereinafter. Periods of the Vcom signal during each frame are the same. Driving voltages applied to electrodes of an array side of the pixels in the TFTLCD correspond to the Vcom signal, whereby a bias voltage and a direction of the bias voltage to each pixel is determined. When voltage of the Vcom signal is lower than the driving voltage of a specific pixel, the bias voltage of the specific pixel is defined as being in the positive (“+”) bias direction. Otherwise, the bias voltage is defined as being in the negative (“−”) bias direction. However in practical use, the common voltages are often shifted and form a non-stable waveform frame by frame. Therefore, brightness of each pixel in one row is slightly changed with transformation of the frames when the TFTLCD displays a static picture as shown in
Referring to
Unfortunately, the double-line row inversion driving method is not flicker free when displaying sequential frames having two illuminated and two unilluminated rows.
Neither the 1-line row inversion nor the double line row inversion driving method is able to completely eliminate flicker entirely.
What is needed therefore, is a driving method and LCD that can overcome the limitations described.
The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of at least one embodiment. In the drawings, like reference numerals designate corresponding parts throughout the various views.
With reference to
The LCD panel 10 includes multiple gate lines 11, multiple data lines 12, and multiple pixels 13. The gate lines 11 are parallel to each other. The data lines 12 are parallel to each other, and intersect with and are electronically isolated from the gate lines 11. The data lines 12 and the gate lines 11 define multiple intersections where the data lines 12 cross the gate lines 11. Each pixel 13 is defined between four intersections, and includes a thin film transistor (TFT) 14, a pixel electrode 15, a common electrode 16, and a liquid crystal molecular cell sandwiched between the pixel electrode 15 and the common electrode 16. Each TFT 14 is formed adjacent to an intersection of the gate and data lines 11, 12. The pixel electrodes 15 are mounted and allocated between the crossed gate lines 11 and data lines 12. A gate, source and drain electrodes of each TFT 14 are electronically connected to a corresponding gate line 11, a corresponding data line 12, and a corresponding electrode 15 respectively.
An external circuit 70 continuously transmits a tricolor (red, green and blue, RGB) signal and multiple control signals to the timing controller 50. The control signals include a vertical synchronization (VSYNC) signal and a horizontal synchronization (HSYNC) signal.
The VSYNC signal is a starting synchronization signal for a frame display and is a fetch trigger to read the tricolor signals. The HSYNC signal is a starting synchronization signal to a gate scan and is a fetch trigger of all pixels 13 in an on scanning gate line 11 to read the tricolor signals. A period of the HSYNC signal is an interval to scan one gate line 11.
The timing controller 50 receives the tricolor signals and the control signals, and generates a polar inverse signal POL and multiple sequential signals by the control program in the memory 60 based on the control signals. The timing controller 50 sends the polar inverse signal POL to the common voltage generating circuit 40, and respectively sends the tricolor signals and corresponding sequential signals to the data driving circuit 30 and the gate driving circuit 20. The polar inverse signal POL is a serial square wave having at least two non-identical frame periods. The square waves in each non-identical frame period of the polar inverse signal POL have a constant. During each frame, the polar inverse signal POL refers to the VSYNC and HSYNC signals and has about 50% duty ratio. The constant frame period of the polar inverse signal POL in each frame is 2k times to the period of the HSYNC signal, and k is an integer except zero.
In step S1, the method is initiated.
In step S2, one period of the VSYNC signal is set and counted a number “n,” where “n” is a positive integer. When the timing controller 50 receives the VSYNC signal and detects a trigger (the voltage of the VSYNC changing from a low level (e.g., a logical zero) to a high level (e.g., a logical one)), the timing controller 50 runs the control program in the memory 60 to set the period of the VSYNC having the trigger as the number “n.”
In step S3, the period of HSYNC signal is doubled to generate the polar inverse signal POL. The timing controller 50 runs the control program in the memory 60 to double the period of HSYNC signal to be the period of the polar inverse signal POL, and sends the polar inverse signal POL to the common voltage generating circuit 40.
In step S4, the timing controller 50 determines whether the trigger of a number “n+1” period of the VSYNC signal has been received. If so, step S5 is implemented. If not, step S3 is repeated. The timing controller 50 continuously receives the VSYNC signal and determines whether the number “n+1” trigger of the VSYNC signal has been read, that is, a subsequent frame is to be displayed by the LCD device. If so, the timing controller 50 implements step S5. If not step S3 is repeated.
In step S5, the number of period of the VSYNC signal is set as “n+1.”
In step S6, the period of HSYNC signal is multiplied by 4 to generate the polar inverse signal POL. The timing controller 50 runs the control program in the memory 60 to multiply the period of HSYNC signal by 4 to be the period of the polar inverse signal POL, and sends the polar inverse signal POL to the common voltage generating circuit 40.
In step S7, the timing controller 50 determines whether the trigger of a number “n+2” period of the VSYNC signal has been received. If so, step S2 is repeated. If not, step S6 is repeated. The timing controller 50 continuously receives the VSYNC signal and determines whether the trigger of the number “n+2” period of the VSYNC signal has been read, that is, a subsequent frame is to be displayed by the LCD device. If so, the timing controller 50 repeats step S2 If not, step S6 is repeated.
The gate driving circuit 20 successively sends the gate-scanning signals G1-G4n respectively to the gate lines 11 based on the sequential signals, whereby the TFTs 14 are successively switched on. The period of each gate-scanning signal G1-G4n corresponds to one frame and has a duty interval substantially equal to the time interval for scanning one gate line 11.
As one gate line 11 is scanned, the common voltage generating circuit 40 refers to the received polar inverse signal POL to generate and send the common voltage VCOM having an alternate bias direction to the common electrode 16 of the LCD panel 10. When the received polar inverse signal POL is a high voltage level, the common voltage generating circuit 40 generates a positive biasing direction common voltage VCOM to the common electrode 16. Otherwise, when the received polar inverse signal POL is a low voltage level, the common voltage generating circuit 40 generates a negative biasing direction common voltage VCOM to the common electrode 16. Hence, the common voltage VCOM is converted in accordance with the polar inverse signal POL into a serial square wave having at least two non-identical frame periods, which means that the polar inverse signal POL is not a signal-frequency (period) square wave. Therefore, a period of the common voltage VCOM of the first embodiment in accordance with
As one gate line 11 is scanned (on-scanning), the data driving circuit 30 follows the sequential signal and transforms the received tricolor signals to generate the gray level voltage signal Vn. The gray level voltage signal Vn is applied to the pixel electrodes 15 through the TFT 14 in the scanned gate line 11, where the gray level voltage signal Vn is generated by referring to the bias direction of the common voltage VCOM at that time. The pixels in the scanned gate line 11 of the LCD panel 10 are able to display the gray level in accordance with the gray level voltage signal Vn.
In summary, the timing controller 50 reads and runs the control program in the memory 60, generates the polar inverse signal POL based on the received VSYNC and HSYNC signals. The common voltage generating circuit 40 receives the polar inverse signal POL and sends the common voltage VCOM with alternate positive and negative bias directions to the common electrode 16. The common voltage VCOM is a bias direction alternating voltage signal in accordance with the polar inverse signal POL, and has a period covering two frames. Periods of waveforms of the common voltage VCOM in the two frames are non-identical. One period of one of the waveforms of the common voltage VCOM is twice the period of the gate-scanning signals G1-G4n. Another period of the other one of the waveforms of the common voltage VCOM is four times to the period of the gate-scanning signals G1-G4n. The data driving circuit 30 sends the gray level voltage signal Vn corresponding to the common voltage VCOM to the pixel electrodes 15. Therefore, when the 1-line row inversion and the 2-line row inversion driving method are combined, the bias voltages provided to the pixels 13 on the illuminated state are not in a same bias direction. Thus, the brightness difference between adjacent frames does not exit or is not discernible. Flicker is then substantially eliminated.
In step S21, the method is initiated.
In step S22, one period of the VSYNC signal is set and counted as number “n.” When the timing controller 50 receives the VSYNC signal and detects a trigger (the voltage of the VSYNC from the low level (0) to the high level (1)) in the VSYNC signal, the timing controller 50 runs the control program in the memory 60 to set the period of the VSYNC having the trigger as number “n.” The “n” is an integer.
In step S23, the period of HSYNC signal is doubled to generate the polar inverse signal POL. The timing controller 50 runs the control program in the memory 60 to double the period of HSYNC signal to be the period of the polar inverse signal POL, and sends the polar inverse signal POL to the common voltage generating circuit 40.
In step S24, it is determined whether the trigger of a number “n+1” period of the VSYNC signal has been received. If so, S25 is implemented. If not, step S23 is repeated. The timing controller 50 continuously receives the VSYNC signal and detects whether the trigger of the number “n+1” period of the VSYNC signal has been read, that is, if a subsequent frame is to be displayed by the LCD device 1. If yes, the timing controller 50 implements step S25. If not, step S23 is repeated.
In step S25, the number of period of the VSYNC signal is set as “n+1.”
In step S26, the period of HSYNC signal is multiplied by 4 to generate the polar inverse signal POL. The timing controller 50 runs the control program in the memory 60 to multiply the period of HSYNC signal by 4 to be the period of the polar inverse signal POL, and sends the polar inverse signal POL to the common voltage generating circuit 40.
In step S27, the timing controller 50 determines whether the trigger of a number “n+2” period of the VSYNC signal has been received . If so, step S28, is implemented. In not, step S26 is repeated.
In step S28, the number of period of the VSYNC signal is set as “n+2.”
In step S29, the period of HSYNC signal is multiplied by 6 to generate the polar inverse signal POL. The timing controller 50 runs the control program in the memory 60 to multiply the period of HSYNC signal by 6 to be the period of the polar inverse signal POL, and sends the polar inverse signal POL to the common voltage generating circuit 40.
In step S30, it is determined whether the trigger of a number “n+3” period of the VSYNC signal has been received. If so, step S22 is repeated. If not, step S29 is repeated. The timing controller 50 continuously receives the VSYNC signal and determines whether the trigger of the number “n+2” period of the VSYNC signal has been read, that is, a subsequent frame is to be displayed by the LCD device 1. If so, the timing controller 50 implements step S22 and starts to generate the subsequent period of the polar inverse signal POL. If not, step S29 is repeated.
Moreover, the control program in the memory 60 may be designed to change the driving method of the LCD device 1. The period of the polar inverse signal POL may be extended by performing three steps, and the three steps includes a step of counting the period of the VSYNC signal, a step of multiplying the period of HSYNC signal, and a step of detecting whether the VSYNC signal is low voltage level (e.g., a logical zero) so that period of bias direction of the common voltage VCOM corresponding to polar inverse signal POL may also be extended, such like four frames, five frames or six frames as one period. Since the polar inverse signal POL and the corresponding common voltage VCOM may be extended unlimitedly to be random, the flicker is then substantially eliminated.
As an example, if the period of the common voltage VCOM is two frames, the period of the waveforms of the common voltage VCOM for the two frames may be respectively defined as two times and six times to the gate-scanning signals.
Also, if the period of the common voltage VCOM is two frames, the period of the waveforms of the common voltage VCOM for the two frames may be respectively defined as four times and six times to the gate-scanning signals.
Furthermore, when the period of the common voltage VCOM is three frames, the period of the waveforms in two of the frames of common voltage VCOM may be identical but inversed, and the waveform of a rest frame of the common voltage VCOM has a different period from the other two waveforms.
It is to be understood that even though numerous characteristics and advantages of the present embodiments have been set forth in the foregoing description with details of the structures and functions of the embodiments, the disclosure is illustrative only, and changes made in detail, especially in matters of shape, size, and arrangement of parts, within the principles of the embodiments, to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Number | Date | Country | Kind |
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200810067420.6 | May 2008 | CN | national |